Low Noise, 1 GHz FastFET Op Amps ADA4817-1/ADA4817-2 TOP VIEW (Not to Scale) 8 +VS FB 2 7 OUT –IN 3 6 NC +IN 4 5 –VS 07756-001 PD 1 NC = NO CONNECT Figure 1. 8-Lead ADA4817-1 LFCSP (CP-8-2) ADA4817-2 +IN1 2 12 –VS1 11 NC NC 3 10 +IN2 –VS2 4 9 –IN2 –IN1 1 NC = NO CONNECT 07756-003 14 +VS1 13 OUT1 16 FB1 15 PD1 TOP VIEW (Not to Scale) FB2 8 Photodiode amplifiers Data acquisition front ends Instrumentation Filters ADC drivers CCD output buffers ADA4817-1 PD2 7 APPLICATIONS CONNECTION DIAGRAMS +VS2 6 High speed −3 dB bandwidth (G = 1, RL = 100 Ω): 1050 MHz Slew rate: 870 V/μs 0.1% settling time: 9 ns Low input bias current: 2 pA Low input capacitance Common-mode capacitance: 1.5 pF Differential-mode capacitance: 0.1 pF Low noise 4 nV/√Hz @ 100 kHz 2.5 fA/√Hz @ 100 kHz Low distortion −90 dBc @ 10 MHz (G = 1, RL = 1 kΩ) Offset voltage: 2 mV maximum High output current: 70 mA Supply current per amplifier: 19 mA Power-down supply current per amplifier: 1 mA OUT2 5 FEATURES Figure 2. 16-Lead ADA4817-2 LFSCP (CP-16-4) GENERAL DESCRIPTION The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™ amplifiers are unity-gain stable, ultrahigh speed voltage feedback amplifiers with FET inputs. These amplifiers are developed in the Analog Devices, Inc., proprietary eXtra Fast Complementary Bipolar (XFCB) process, which allows the amplifiers to achieve ultralow noise (4 nV/√Hz; 2.5 fA/√Hz) as well as very high input impedances. With 1.5 pF of input capacitance, low noise (4 nV/√Hz), low offset voltage (2 mV maximum), and 1050 MHz −3 dB bandwidth, the ADA4817-1/ADA4871-2 are ideal for data acquisition front ends as well as wideband transimpedance applications, such as photodiode preamps. With a wide supply voltage range from 5 V to 10 V, the ability to operate on either single or dual supplies, the ADA4817-1/ ADA4817-2 are designed to work in a variety of applications including active filtering and ADC driving. The ADA4817-1 is available in a 3 mm × 3 mm 8-lead LFCSP and the ADA4817-2 is available in a 4 mm × 4 mm 16-lead LFSCP. Both packages feature a low distortion pinout, which improves second harmonic distortion and simplifies the layout of the circuit board. In addition, both packages feature an exposed paddle that provides a low thermal resistance path to the printed circuit board (PCB). This enables more efficient heat transfer and increases reliability. Both products are rated to work over the extended industrial temperature range (−40°C to +105°C). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADA4817-1/ADA4817-2 TABLE OF CONTENTS Features .............................................................................................. 1 Driving Capacitive Loads .......................................................... 14 Applications ....................................................................................... 1 Thermal Considerations............................................................ 14 Connection Diagrams ...................................................................... 1 Power-Down Operation ............................................................ 15 General Description ......................................................................... 1 Capacitive Feedback................................................................... 15 Revision History ............................................................................... 2 Layout, Grounding, and Bypassing Considerations .................. 16 Specifications..................................................................................... 3 Signal Routing............................................................................. 16 ±5 V Operation ............................................................................. 3 Power Supply Bypassing ............................................................ 16 5 V Operation ............................................................................... 4 Grounding ................................................................................... 16 Absolute Maximum Ratings............................................................ 5 Exposed Paddle........................................................................... 16 Thermal Resistance ...................................................................... 5 Leakage Currents ........................................................................ 17 Maximum Safe Power Dissipation ............................................. 5 Input Capacitance ...................................................................... 17 ESD Caution .................................................................................. 5 Input-to-Input/Output Coupling ............................................. 17 Pin Configurations and Function Descriptions ........................... 6 Applications Information .............................................................. 18 Typical Performance Characteristics ............................................. 7 Low Distortion Pinout ............................................................... 18 Test Circuits ..................................................................................... 12 Wideband Photodiode Preamp ................................................ 18 Theory of Operation ...................................................................... 13 High Speed JFET Input Instrumentation Amplifier.............. 20 Closed-Loop Frequency Response ........................................... 13 Active Low-Pass Filter (LPF) .................................................... 21 Noninverting Closed-Loop Frequency Response .................. 13 Outline Dimensions ....................................................................... 23 Inverting Closed-Loop Frequency Response ............................. 13 Ordering Guide .......................................................................... 23 Wideband Operation ................................................................. 14 REVISION HISTORY 11/08—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADA4817-1/ADA4817-2 SPECIFICATIONS ±5 V OPERATION TA = 25°C, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Gain Bandwidth Product 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Turn-On/Turn-Off Time Input Leakage Current POWER SUPPLY Operating Range Quiescent Current per Amplifier Powered Down Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection Unit 1050 200 390 ≥410 60 870 9 MHz MHz MHz MHz MHz V/μs ns f = 1 MHz, VOUT = 2 V p-p, RL = 1 kΩ f = 10 MHz, VOUT = 2 V p-p, RL = 1 kΩ f = 50 MHz, VOUT = 2 V p-p, RL = 1 kΩ f = 100 kHz f = 100 kHz −113/−117 −90/−94 −64/−66 4 2.5 dBc dBc dBc nV/√Hz fA/√Hz 62 0.4 7 2 100 1 65 −77 500 1.5 0.1 −5 to +2.3 −90 GΩ pF pF V dB 8 −3.6 to +3.7 −4.0 to +4.0 70 100/170 ns V V mA mA >+VS − 1 <+VS − 3 0.3/1 0.3 34 V V μs μA μA Common-mode Common-mode Differential-mode VCM = ±0.5 V VIN = ±2.5 V, G = 2 −3.5 to +3.5 −3.9 to +3.9 RL = 1 kΩ Linear Output Current Short-Circuit Current POWER-DOWN PD Pin Voltage Max VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 0.1 V p-p, G = 2 VOUT = 0.1 V p-p VOUT = 2 V p-p, RL = 100 Ω, G = 2 VOUT = 4 V step VOUT = 2 V step, G = 2 TMIN to TMAX Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Typ Sinking/sourcing Enabled Powered down PD = +VS PD = −VS 5 +VS = 4.5 V to 5.5 V, −VS = −5 V +VS = 5 V, −VS = −4.5 V to −5.5 V Rev. 0 | Page 3 of 24 −67 −67 19 1.5 −72 −72 2 20 3 55 10 21 3 mV μV/°C pA pA pA dB V mA mA dB dB ADA4817-1/ADA4817-2 5 V OPERATION TA = 25°C, +VS = 3 V, −VS = −2 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to midsupply, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Conditions Min Input Common-Mode Voltage Range Common-Mode Rejection OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Turn-On/Turn-Off Time Input Leakage Current POWER SUPPLY Operating Range Quiescent Current per Amplifier Powered Down Quiescent Current Positive Power Supply Rejection Negative Power Supply Rejection Unit 500 160 280 32 320 11 MHz MHz MHz MHz V/μs ns f = 1 MHz, VOUT = 1 V p-p, RL = 1 kΩ f = 10 MHz, VOUT = 1 V p-p, RL = 1 kΩ f = 50 MHz, VOUT = 1 V p-p, RL = 1 kΩ f = 100 kHz f = 100 kHz −87/−88 −68/−66 −57/−55 4 2.5 dBc dBc dBc nV/√Hz fA/√Hz 61 0.5 7 2 100 1 63 −72 500 1.3 0.1 0 to 2.3 −83 GΩ pF pF V dB 13 1 to 3.8 0.9 to 4.0 55 40/130 ns V V mA mA >+VS − 1 <+VS − 3 0.2/0.7 0.2 31 V V μs μA μA Common-mode Common-mode Differential-mode VCM = ±0.25 V VIN = ±1.25 V, G = 2 1.3 to 3.7 1 to 3.9 RL = 1 kΩ Linear Output Current Short-Circuit Current POWER-DOWN PD Pin Voltage Max VOUT = 0.1 V p-p VOUT = 1 V p-p VOUT = 0.1 V p- p, G = 2 VOUT = 1 V p-p, G = 2 VOUT = 2 V step VOUT = 1 V step, G = 2 TMIN to TMAX Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Typ Sinking/sourcing Enabled Powered Down PD = +VS PD = −VS 5 +VS = 4.75 V to 5.25 V, −VS = 0 V +VS = 5 V, −VS = −0.25 V to +0.25 V Rev. 0 | Page 4 of 24 −66 −63 14 1.5 −71 −69 2.3 20 3 45 10 15 2.5 mV μV/°C pA pA pA dB V mA mA dB dB ADA4817-1/ADA4817-2 ABSOLUTE MAXIMUM RATINGS PD = Quiescent Power + (Total Drive Power – Load Power) Table 3. ⎛V V PD = (VS × I S ) + ⎜⎜ S × OUT RL ⎝ 2 Rating 10.6 V See Figure 3 −VS − 0.5 V to +VS + 0.5 V ±VS −65°C to +125°C −40°C to +105°C 300°C PD = (VS × I S ) + 150°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in circuit board for surfacemount packages. (3) RL Airflow increases heat dissipation, effectively reducing θJA. More metal directly in contact with the package leads and exposed paddle from metal traces, throughholes, ground, and power planes also reduces θJA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle LFCSP_VD (single 94°C/W) and LFCSP_VQ (dual 64°C/W) package on a JEDEC standard 4-layer board. θJA values are approximations. 3.5 MAXIMUM POWER DISSIPATION (W) θJC 29 14 (VS /4 )2 In single-supply operation with RL referenced to −VS, worstcase situation is VOUT = VS/2. Table 4. θJA 94 64 (2) RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst-case scenario, when VOUT = VS/4 for RL to midsupply. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type LFCSP_VD (ADA4817-1) LFSCP_VQ (ADA4817-2) ⎞ VOUT ⎟– ⎟ RL ⎠ Unit °C/W °C/W MAXIMUM SAFE POWER DISSIPATION The maximum safe power dissipation for the ADA4817-1/ ADA4817-2 are limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C (which is the glass transition temperature), the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4817. Exceeding a junction temperature of 175°C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. 3.0 ADA4817-2 2.5 2.0 1.5 ADA4817-1 1.0 0.5 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 AMBIENT TEMPERATURE (°C) 07756-008 Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature (1) 2 Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4817-1/ADA4817-2 drive at the output. The quiescent power is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). Rev. 0 | Page 5 of 24 ADA4817-1/ADA4817-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4817-2 6 NC 5 –VS NC = NO CONNECT NOTES 1. EXPOSED PAD CAN BE CONNECTED TO GROUND PLANE OR NEGATIVE SUPPLY PLANE. 14 +VS1 9 –IN2 NC = NO CONNECT NOTES 1. EXPOSED PAD CAN BE CONNECTED TO THE GROUND PLANE OR NEGATIVE SUPPLY PLANE. Figure 4. 8-Lead LFCSP Pin Configuration 07756-107 –IN 3 +IN 4 10 +IN2 –VS2 4 FB2 8 7 OUT 11 NC NC 3 PD2 7 FB 2 12 –VS1 +VS2 6 8 +VS 07756-005 PD 1 –IN1 1 +IN1 2 OUT2 5 TOP VIEW (Not to Scale) 13 OUT1 16 FB1 ADA4817-1 15 PD1 TOP VIEW (Not to Scale) Figure 5. 16-Lead LFCSP Pin Configuration Table 5. 8-Lead LFCSP Pin Function Descriptions Table 6. 16-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 (EPAD) Pin No. 1 2 3, 11 4 5 6 7 8 9 10 12 13 14 15 16 17 (EPAD) Mnemonic PD FB −IN +IN −VS NC OUT +VS Exposed paddle (EPAD) Description Power-Down. Do not leave floating. Feedback Pin. Inverting Input. Noninverting Input. Negative Supply. No Connect. Output. Positive Supply. Exposed Pad. Can be connected to GND, −VS plane or left floating. Rev. 0 | Page 6 of 24 Mnemonic −IN1 +IN1 NC −VS2 OUT2 +VS2 PD2 FB2 −IN2 +IN2 −VS1 OUT1 +VS1 PD1 FB1 Exposed paddle (EPAD) Description Inverting Input 1. Noninverting Input 1. No Connect. Negative Supply 2. Output 2. Positive Supply 2. Power-Down 2. Do not leave floating. Feedback Pin 2. Inverting Input 2. Noninverting Input 2. Negative Supply 1. Output 1. Positive Supply 1. Power-Down 1. Do not leave floating. Feedback Pin 1. Exposed Pad. Can be connected to GND, −VS plane or left floating. ADA4817-1/ADA4817-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±5 V, G = 1, (RF = 348 Ω for G > 1), RL = 100 Ω to ground, small signal VOUT = 100 mV p-p, large signal VOUT = 2 V p-p, unless noted otherwise. 3 G =2 0 G=5 –3 –6 –9 –12 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G G = 1, SINGLE –3 G = 1, DUAL G=5 –6 –9 1M 10M 100M FREQUENCY (Hz) 1G 10G Figure 9. Large Signal Frequency Response for Various Gains 6 6 3 3 CLOSED-LOOP GAIN (dB) 0 VS = 10V –3 VS = 5V –6 –3 VS = 5V VOUT = 1V p-p –6 –9 1M 10M 100M FREQUENCY (Hz) 1G 1G –12 100k 07756-007 –12 100k CL = 6.6pF CL = 4.4pF 10M 100M FREQUENCY (Hz) 1G 10G Figure 10. Large Signal Frequency Response for Various Supplies Figure 7. Small Signal Frequency Response for Various Supplies 9 1M 07756-010 –9 VS = 10V VOUT = 2V p-p 0 9 CL = 2.2pF RF = 348Ω RF = 274Ω 6 6 CLOSED-LOOP GAIN (dB) CL = 0pF 3 0 –3 RF = 200Ω 3 0 –3 –6 –6 –9 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G 07756-068 G=2 RF = 274Ω G=2 –9 100k 1M 10M 100M FREQUENCY (Hz) 1G Figure 11. Small Signal Frequency Response for Various RF Figure 8. Small Signal Frequency Response for Various CL Rev. 0 | Page 7 of 24 10G 07756-011 CLOSED-LOOP GAIN (dB) 0 –12 100k Figure 6. Small Signal Frequency Response for Various Gains CLOSED-LOOP GAIN (dB) G=2 07756-009 3 G = 1, SINGLE NORMALIZED CLOSED-LOOP GAIN (dB) G = 1, DUAL 07756-066 NORMALIZED CLOSED-LOOP GAIN (dB) 6 ADA4817-1/ADA4817-2 6 G = 2, SS 3 CLOSED-LOOP GAIN (dB) G = 2, LS 0.2 0.1 G = 1, SS 0 G = 1, LS –0.1 –0.2 –0.3 –3 –6 –9 –0.4 –0.5 100k 1M 10M 100M FREQUENCY (Hz) 1G 10G –12 100k –40 –40 –60 –60 DISTORTION (dBc) –20 –80 HD2, RL = 1kΩ –100 HD3, RL = 100Ω –120 10M 100M FREQUENCY (Hz) Figure 13. Distortion vs. Frequency for Various Loads, VOUT = 2 V p-p 100M 1G 10G HD2, VS = 5V –80 –100 –120 HD2, VS = 10V –140 100k 07756-014 1M 10M HD3, VS = 5V HD3, RL = 1kΩ –140 100k 1M Figure 15. Small Signal Frequency Response vs. Temperature –20 HD2, RL = 100Ω TA = +25°C, SINGLE TA = +25°C, DUAL TA = –40°C, SINGLE TA = –40°C, DUAL TA = +105°C, SINGLE TA = +105°C, DUAL FREQUENCY (Hz) Figure 12. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage DISTORTION (dBc) 0 07756-036 0.3 HD3, VS = 10V 1M 100M 10M FREQUENCY (Hz) 07756-013 0.4 07756-012 NORMALIZED CLOSED-LOOP GAIN (dB) 0.5 Figure 16. Distortion vs. Frequency for Various Supplies, VOUT = 2 V p-p –20 –20 fC = 1MHz –40 HD2, VS = 5V –60 DISTORTION (dBc) DISTORTION (dBc) –40 HD2, VS = 10V –80 –100 –60 –80 HD2, RL = 100Ω HD2, RL = 1kΩ –100 HD3, VS = 5V HD3, VS = 10V 1M 10M FREQUENCY (Hz) 100M Figure 14. Distortion vs. Frequency for Various Supplies, G = 2, VOUT = 2 V p-p Rev. 0 | Page 8 of 24 –140 HD3, RL = 100Ω HD3, RL = 1kΩ 0 1 2 3 4 5 OUTPUT VOLTAGE (V p-p) Figure 17. Distortion vs. Output Voltage for Various Loads 6 07756-017 –140 100k –120 07756-016 –120 ADA4817-1/ADA4817-2 0.15 DUAL, CF = 0.5pF SINGLE, NO CF 0.10 SINGLE OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.10 DUAL, CF = 0.5pF SINGLE, NO CF 0.05 0 –0.05 DUAL –0.10 SINGLE 0.05 0 –0.05 DUAL 07756-018 –0.10 G=2 –0.15 –0.15 07756-021 0.15 VS = 5V G=2 TIME (5ns/DIV) TIME (5ns/DIV) Figure 18. Small Signal Transient Response Figure 21. Small Signal Transient Response 1.5 6 G=2 1.0 OUTPUT VOLTAGE (V) 4 VOUT VOLTAGE (V) 2 0 0.5 0 –0.5 DUAL –1.0 –4 –1.5 –6 07756-019 2 × VIN TIME (100 ns/DIV) 0.5 N: 4197 MEAN: –0.0248457 SD: 0.245658 SETTLING TIME 0.4 600 0.2 SETTLING TIME (%) 0.3 500 400 300 200 0.1 0 –0.1 –0.2 –1.0 –0.5 0 0.5 1.0 07756-023 –0.3 100 07756-025 NUMBER OF HITS Figure 22. Large Signal Transient Response 700 0 –1.5 SINGLE TIME (5ns/DIV) Figure 19. Output Overdrive Recovery 800 DUAL, CF = 0.5pF SINGLE, NO CF G=2 07756-022 –2 –0.4 –0.5 1.5 VOS (mV) TIME (5ns/DIV) Figure 23. 0.1% Short-Term Settling Time Figure 20. Input Offset Voltage Histogram Rev. 0 | Page 9 of 24 ADA4817-1/ADA4817-2 0.5 –10 0.4 –20 0.3 –40 –PSRR +PSRR –50 –60 –70 0.2 0.1 0 –0.1 –0.2 –80 –0.3 –90 –0.4 1M 10M 1G 100M FREQUENCY (Hz) –0.5 –40 07756-032 –100 100k 20 40 60 80 100 Figure 27. Offset Voltage vs. Temperature 1000 INPUT VOLTAGE NOISE (nV/ Hz) –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 1M 10M 100M 1G FREQUENCY (Hz) 100 10 1 10 07756-029 CMRR (dB) 0 TEMPERATURE (°C) Figure 24. PSRR vs. Frequency –90 –95 –100 100k –20 100 1k 10k 100k 1M 10M 100M 80 100 FREQUENCY (Hz) 07756-026 PSRR (dB) –30 07756-037 OFFSET VOLTAGE (mV) 0 Figure 28. Input Voltage Noise Figure 25. CMRR vs. Frequency 100 24 VS = ±5V SUPPLY CURRENT (mA) 10 1 0.1 20 18 16 VS = +5V 14 0.01 100k 1M 10M 100M FREQUENCY (Hz) Figure 26. Output Impedance vs. Frequency 1G 10 –40 07756-033 12 07756-030 OUTPUT IMPEDANCE (Ω) 22 –20 0 20 40 60 TEMPERATURE (°C) Figure 29. Quiescent Current vs. Temperature for Various Supply Voltages Rev. 0 | Page 10 of 24 ADA4817-1/ADA4817-2 1.5 –V-S + VOUT 1.4 10 60 –30 –70 50 1.3 PHASE –110 GAIN (dB) 40 +VS – VOUT +VS – VOUT 1.2 1.1 1.0 VS = +5V 0.9 –VS + VOUT 0.8 –40 70 –20 0 20 40 60 80 100 –150 30 GAIN 20 –190 10 –230 0 –270 –10 10k 100k 1M 10M 100M 1G –310 10G FREQUENCY (Hz) TEMPERATURE (°C) Figure 30. Output Saturation Voltage vs. Temperature Figure 31. Open-Loop Gain and Phase vs. Frequency Rev. 0 | Page 11 of 24 PHASE (Degrees) RL = 100Ω 07756-015 VS = ±5V 07756-034 OUTPUT SATURATION VOLTAGE (V) 1.6 ADA4817-1/ADA4817-2 TEST CIRCUITS The output feedback pins are used for ease of layout in Figure 32 to Figure 37. +VS +VS 10µF + 10µF + RG 0.1µF RF 0.1µF 0.1µF VOUT VIN VOUT VIN RL 49.9Ω 0.1µF RL 49.9Ω 10µF + –VS –VS Figure 32. G = 1 Configuration Figure 35. Noninverting Gain Configuration +VS +VS AC 0.1µF 07756-147 0.1µF 07756-141 + 10µF 10µF + 49.9Ω 0.1µF VOUT VOUT RL RL 49.9Ω + 10µF 07756-145 0.1µF –VS 07756-148 AC –VS Figure 33. Positive Power Supply Rejection Figure 36. Negative Power Supply Rejection +VS +VS 10µF 10µF + + RF 1kΩ 0.1µF RSNUB VIN 49.9Ω 0.1µF VOUT CL 0.1µF 1kΩ VIN RL VOUT 1kΩ 53.6Ω 10µF 0.1µF RL 1kΩ –VS + 07756-142 + 10µF 0.1µF 0.1µF –VS Figure 34. Capacitive Load Configuration Figure 37. Common-Mode Rejection Rev. 0 | Page 12 of 24 07756-146 RG ADA4817-1/ADA4817-2 THEORY OF OPERATION The ADA4817-1/ADA4817-2 are voltage feedback operational amplifiers that combine new architecture for FET input operational amplifiers with the eXtra Fast Complementary Bipolar (XFCB) process from Analog Devices resulting in an outstanding combination of speed and low noise. The innovative high speed FET input stage handles common-mode signals from the negative supply to within 2.3 V of the positive rail. This stage is combined with an H-bridge to attain a 870 V/μs slew rate and low distortion, in addition to 4 nV/√Hz input voltage noise. The amplifier features a high speed output stage capable of driving heavy loads sourcing and sinking up to 70 mA of linear current. Supply current and offset current are laser trimmed for optimum performance. These specifications make the ADA4817-1/ ADA4817-2 a great choice for high speed instrumentation and high resolution data acquisition systems. Its low noise, picoamp input current, precision offset, and high speed make them superb preamps for fast photodiode applications. Closed-loop −3 dB frequency f −3dB = f CROSSOVER × RG R F + RG (6) INVERTING CLOSED-LOOP FREQUENCY RESPONSE Solving for the transfer function, −2π × f CROSSOVER × R F VO = VI (R F + RG )S + 2π × f CROSSOVER × RG At dc (7) VO R =− F VI RG (8) Solve for closed-loop −3 dB frequency by, f −3dB = f CROSSOVER × RG R F + RG (9) A = (2π × fCROSSOVER )/s 80 The ADA4817-1/ADA4817-2 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 40. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown in Figure 38 and Figure 39. RF OPEN-LOOP GAIN (A) (dB) CLOSED-LOOP FREQUENCY RESPONSE 60 40 fCROSSOVER = 410MHz 20 RG 07756-044 0 RF VOUT 07756-045 Figure 39. Inverting Configuration Figure 41 shows a voltage feedback amplifier’s dc errors. For both inverting and noninverting configurations, NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE ⎛ R + RF VOUT (error ) = I b+ × RS ⎜⎜ G ⎝ RG Solving for the transfer function, 2π × f CROSSOVER (RG + R F ) VO = (RF + RG )S + 2π × f CROSSOVER × RG VI VO RF + RG = VI RG ⎞ ⎟ − I b − × R F + VOS ⎟ ⎠ (4) ⎛ RG + R F ⎞ ⎟ ⎜ ⎟ ⎜ R G ⎠ ⎝ (10) RF where fCROSSOVER is the frequency where the amplifier’s open-loop gain equals 0 dB. At dc 1000 +VOS – RG (5) VIN RS Ib – A VOUT Ib+ Figure 41. Voltage Feedback Amplifier’s DC Errors Rev. 0 | Page 13 of 24 07756-047 A 100 The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (RF + RG)/RG. This simple model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp. RG VE 10 FREQUENCY (MHz) Figure 40. Open-Loop Gain vs. Frequency and Basic Connections Figure 38. Noninverting Configuration VIN 1 0.1 07756-046 VOUT A VE VIN ADA4817-1/ADA4817-2 VOS = VOS nom + Δ VS Δ VCM + PSR CMR (11) where: VOSnom is the offset voltage specified at nominal conditions. ΔVS is the change in power supply from nominal conditions. PSR is the power supply rejection. ΔVCM is the change in common-mode voltage from nominal conditions. CMR is the common-mode rejection. WIDEBAND OPERATION If this pole occurs too close to the unity-gain crossover point, the phase margin degrades. This is due to the additional phase loss associated with the pole. Note that such capacitance introduces significant peaking in the frequency response. Larger capacitance values can be driven but must use a snubbing resistor (RSNUB) at the output of the amplifier, as shown in Figure 42. Adding a small series resistor, RSNUB, creates a zero that cancels the pole introduced by the load capacitance. Typical values for RSNUB can range from 10 Ω to 50 Ω. The value is typically based on the circuit requirements. Figure 42 also shows another way to reduce the effect of the pole created by the capacitive load (CL) by placing a capacitor (CF) in the feedback loop parallel to the feedback resistor Typical capacitor values can range from 0.5 pF to 2 pF. Figure 43 shows the effect of adding a feedback capacitor to the frequency response. +VS The ADA4817-1/ADA4817-2 provides excellent performance as a high speed buffer. Figure 38 shows the circuit used for wideband characterization for high gains. The impedance at the summing junction (RF || RG) forms a pole in the amplifier’s loop response with the amplifier’s input capacitance of 1.5 pF. This pole can cause peaking and ringing if its frequency is too low. Feedback resistances of 100 Ω to 400 Ω are recommended, because they minimize the peaking and they do not degrade the performance of the output stage. Peaking in the frequency response can also be compensated for with a small feedback capacitor (CF) in parallel with the feedback resistor, or a series resistor in the noninverting input as shown in Figure 42. 10µF + CF RG RF 0.1µF RSNUB VIN 49.9Ω 0.1µF VOUT CL RL + 10µF 0.1µF –VS 07756-143 The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG (though with the ADA4817-1/ADA4817-2 input currents in the picoamp range, this is likely not a concern). To include commonmode effects and power supply rejection effects, total VOS can be modeled by Figure 42. RSNUB or CF Used to Reduce Peaking The distortion performance depends on a number of variables: THERMAL CONSIDERATIONS • • • • • With 10 V power supplies and 19 mA quiescent current, the ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This implies that in the LFCSP, whose thermal resistance is 94°C/W for the ADA4817-1and 64°C/W for the ADA4817-2, the junction temperature is typically almost 25° higher than the ambient temperature. The ADA4817-1/ADA4817-2 are designed to maintain a constant bandwidth over temperature; therefore, an initial ramp up of the current consumption during warm-up is expected. The VOS temperature drift is below 12 μV/°C; therefore, it can change up to 0.3 mV due to warm-up effects for an ADA4817-1/ ADA4817-2 in a LFCSP on 10 V. The input bias current increases by a factor of 1.7 for every 10°C rise in temperature. The closed-loop gain of the application Whether it is inverting or noninverting Amplifier loading Signal frequency and amplitude Board layout The best performance is usually obtained in the G + 1 configuration with no feedback resistance, big output load resistors, and small board parasitic capacitances. DRIVING CAPACITIVE LOADS In general, high speed amplifiers have a difficult time driving capacitive loads. This is particularly true in low closed-loop gains, where the phase margin is the lowest. The difficulty arises because the load capacitance, CL, forms a pole with the output resistance, RO, of the amplifier. The pole can be described by the following equation: fP = 1 2πRO C L Heavy loads increase power dissipation and raise the chip junction temperature as described in the Absolute Maximum Ratings section. Care should be taken not to exceed the rated power dissipation of the package. (12) Rev. 0 | Page 14 of 24 ADA4817-1/ADA4817-2 POWER-DOWN OPERATION The ADA4817-1/ADA4817-2 are equipped with separate power-down pins (PD) pins for each amplifier. This allows the user the ability to reduce the quiescent supply current when an amplifier is inactive from 2 mA to 19 mA. The power-down threshold levels are derived from the voltage applied to the +VS pin. In ±5 V supply application, the enable voltage is greater than +4 V, and in a ±3 V supply application, the enable voltage is greater than +2 V. However, the amplifier is powered down whenever the voltage applied to the PD pin is 3 V below +VS. If the PD pin is not to be used, it is best to connect it to the positive supply. Figure 43 shows the small signal frequency response of the ADA4817-2 at a gain of 2 vs. CF. At first no CF was used to show the peaking then two other values of 0.5 pF and 1 pF were used to show how to reduce the peaking or even eliminate it. As shown in Figure 43, if the power consumption is a factor in the system, then using a larger feedback capacitor is acceptable as long as a feedback capacitor is used across it to control the peaking. However, if the power consumption is not an issue, then a lower value feedback resistor such as 100 Ω, would not require any additional feedback capacitance to maintain flatness and lower peaking. 9 CF = 0.5pF NO CF 6 ±5 V +3 V, −2 V Not active Active >4 V <2 V >2 V <0 V CAPACITIVE FEEDBACK Due to package variations and pin-to-pin parasitic between the single and the dual, the ADA4817-2 has a little more peaking then the ADA4817-1, especially at a gain of 2. The best way to tame the peaking is to place a feedback capacitor across the feedback resistor. CF = 1pF 3 0 –3 –6 RF = 348Ω G=2 VS = 10V VOUT = 100mV p-p RL = 100Ω –9 0.1 1 07756-049 PD Pin CLOSED-LOOP GAIN (dB) Table 7. Power-Down Voltage Control 10 100 1k 10k FREQUENCY (MHz) Figure 43. Small Signal Frequency Response vs. Feedback Capacitor (ADA4817-2) Rev. 0 | Page 15 of 24 ADA4817-1/ADA4817-2 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Laying out the PCB is usually the last step in the design process and often proves to be one of the most critical. A brilliant design can be rendered useless because of poor layout. Because the ADA4817-1/ADA4817-2 can operate into the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. SIGNAL ROUTING The ADA4817-1/ADA4817-2 feature the new low distortion pinout with a dedicated feedback pin that allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. When laying out the ADA4817-1/ADA4817-2 as a unity-gain amplifier, it is recommended that a short, but wide, trace be placed between the dedicated feedback pins, and the inverting input to the amplifier be used to minimize stray parasitic inductance. To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, the ADA4817-1/ADA4817-2 power supply pins need to be properly bypassed. A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins see a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next larger value capacitor. It is recommended that a 0.1 μF ceramic 0508 case be used for the ADA4817-1/ADA4817-2. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 μF provides low impedance at high frequencies. A 10 μF electrolytic capacitor should be placed in parallel with the 0.1 μF. The 10 μF capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors may be used depending on the circuit requirements. Additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary. Placement of the capacitor returns (grounds) is also important. Returning the capacitors grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short but equal from the load is optimal for performance. In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. It is another option to improve performance. Minimizing the trace length and widening the trace from the capacitors to the amplifier reduces the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins because vias can introduce parasitic inductance, which can lead to instability. When required to use vias, choose multiple large diameter vias because this lowers the equivalent parasitic inductance. GROUNDING The use of ground and power planes is encouraged as a method of providing low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifier’s input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin. EXPOSED PADDLE The ADA4817-1/ADA4817-2 feature an exposed paddle, which lowers the thermal resistance by 25% compared to a standard SOIC plastic package. The exposed paddle of the ADA4817-1/ ADA4817-2 floats internally which provides the maximum flexibility and ease of use. It can be connected to the ground plane or to the negative power supply plane. In cases where thermal heating is not an issue, the exposed pad could be left floating. The use of thermal vias or heat pipes can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias help to lower the overall junction-toambient temperature (θJA). Using a heavier weight copper on the surface to which the amplifier’s exposed paddle is soldered can greatly reduce the overall thermal resistance seen by the ADA4817-1/ADA4817-2. Rev. 0 | Page 16 of 24 ADA4817-1/ADA4817-2 LEAKAGE CURRENTS INPUT CAPACITANCE Poor PCB layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the ADA4817-1/ADA4817-2. Any voltage differential between the inputs and nearby runs sets up leakage currents through the PCB insulator, for example, 1 V/ 100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils on the board, can create significant leakage. To reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides (above and below) while using a multilayer board. Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, in turn increasing the amplifier’s gain, causing peaking of the frequency response or even oscillations if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. In addition, low absorption materials, such as Teflon® or ceramic, can be necessary in some instances. INPUT-TO-INPUT/OUTPUT COUPLING To minimize capacitive coupling between the inputs and outputs, the output signal traces should not be parallel with the inputs. In addition, the input traces should not be very close to each other. A minimum of 7 mils between the two inputs is recommended. Rev. 0 | Page 17 of 24 ADA4817-1/ADA4817-2 APPLICATIONS INFORMATION The ADA4817-1/ADA4817-2 feature a new low distortion pinout from Analog Devices. The new pinout provides two advantages over the traditional pinout. The first advantage is improved second harmonic distortion performance, which is accomplished by the physical separation of the noninverting input pin and the negative power supply pin. The second advantage is the simplification of the layout due to the dedicated feedback pin and easy routing of the gain set resistor back to the inverting input pin. This allows a compact layout, which helps to minimize parasitics and increase stability. The designer does not need to use the dedicated feedback pin to provide feedback for the ADA4817-1/ADA4817-2. The output pin of the ADA4817-1/ADA4817-2 can still be used to provide feedback to the inverting input of the ADA4817-1/ADA4817-2. WIDEBAND PHOTODIODE PREAMP The wide bandwidth and low noise of the ADA4817-1/ ADA4817-2 make it an ideal choice for transimpedance amplifiers, such as those used for signal conditioning with high speed photodiodes. Figure 44 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is I × RF (13) VOUT = PHOTO 1 + sC F R F where: IPHOTO is the output current of the photodiode. The parallel combination of RF and CF sets the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier’s summing junction, including the photodiode capacitance (CS) and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth obtained with a 45° phase margin (f(45)) is defined by f CR 2π × R F × (C S + C M + C D ) f ( 45) = where: fCR is the amplifier crossover frequency. RF is the feedback resistor. CS is the source capacitance including the photodiode and the board parasitic. CM is the common-mode capacitance of the amplifier. CD is the differential capacitance of the amplifier. The value of CF that produces f(45) can be shown to be CF = CS + C M + CD 2π × R F × f CR The preamplifier output noise over frequency is shown in Figure 45. VOLTAGE NOISE (nV/ Hz) RF CM RSH = 1011Ω CS CD VOUT 07756-048 CM VB (15) The frequency response shows less peaking if bigger CF values are used. CF IPHOTO (14) Figure 44. Wideband Photodiode Preamp f1 = 1 2 RF (CF + CS + CM + CD) f2 = 1 2 RFCF f3 = fCR (CF + CS + CM + CD)/CF RF NOISE VEN (CF + CS + CM + CD)/CF f3 f2 f1 VEN NOISE DUE TO AMPLIFIER FREQUENCY (Hz) Figure 45. Photodiode Voltage Noise Contributions Rev. 0 | Page 18 of 24 07756-043 LOW DISTORTION PINOUT ADA4817-1/ADA4817-2 45 bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. The current equivalent noise from the inverting terminal is typically negligible for most applications. The innovative architecture used in the ADA4817-1/ADA4817-2 makes balancing both inputs unnecessary, as opposed to traditional FET input amplifiers. Therefore, minimizing the impedance seen from the noninverting terminal to ground at all frequencies is critical for optimal noise performance. 40 35 MAGNITUDE (dB) 30 25 20 15 10 5 07756-051 G = 63V/V R = 100Ω 0 V L = 10V S VOUT = 6V p-p –5 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 46. Photodiode Preamp Frequency Response The pole in the loop transmission translates to a zero in the amplifier’s noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission zero introduced by CF limits the amplification. The noise gain Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 8 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with RF = 50 kΩ, CS = 30 pF, and CF = 0.5 pF (bandwidth of about 6.4 MHz) are also listed. Table 8. RMS Noise Contributions of Photodiode Preamp Contributor RF VEN Amp IEN Amp Expression RMS Noise with RF = 50 kΩ, CS = 30 pF, CF = 0.5 pF 94 μV 4kT × R F × f 2 × 1.57 VEN × CS + CM + C D + CF × f 3 × 1.57 CF 777.5 μV 0.4 μV IEN × R F × f 2 × 1.57 783 μV (total) Rev. 0 | Page 19 of 24 ADA4817-1/ADA4817-2 HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER approximated by: Figure 47 shows an example of a high speed instrumentation amplifier with a high input impedance using the ADA4817-1/ ADA4817-2. The dc transfer function is Common-mode rejection of the in-amp is primarily determined by the match of resistor ratios, R1:R2 to R3:R4. It can be estimated by ⎛ 2R VOUT = (VN − VP ) ⎜⎜1 + F RG ⎝ ⎞ ⎟ ⎟ ⎠ In-amp−3 dB = (fCR × RG)/(2 × RF) VO (δ1 − δ2 ) = VCM (1 + δ1) δ2 (16) (17) The summing junction impedance for the preamps is equal to RF || 0.5(RG). Keep this value relatively low to improve the bandwidth response like in the previous example. For G = 1, it is recommended that the feedback resistors for the two preamps be set to 0 Ω and the gain resistor be open. The system bandwidth for G = 1 is 400 MHz. For gains higher than 2, the bandwidth is set by the preamp, and it can be VCC 0.1µF 10µF RS1 VN R2 350Ω ADA4817-2 U1 0.1µF VCC 10µF VEE 0.1µF R1 350Ω 10µF RF = 500Ω VO ADA4817-1 RG R3 350Ω RF = 500Ω 0.1µF 10µF VCC R4 350Ω 0.1µF VEE 10µF ADA4817-2 U2 0.1µF VP 10µF 07756-050 RS2 VEE Figure 47. High Speed Instrumentation Amplifier Rev. 0 | Page 20 of 24 ADA4817-1/ADA4817-2 Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the corner frequency, fc, of the filter. The capacitor values shown in Figure 49 actually incorporate some stray PCB capacitance. ACTIVE LOW-PASS FILTER (LPF) Active filters are used in many applications such as antialiasing filters and high frequency communication IF strips. With a 410 MHz gain bandwidth product and high slew rate, the ADA4817-1/ADA4817-2 is an ideal candidate for active filters. Moreover, thanks to the low input bias current provided by the FET stage, the ADA4817-1/ADA4817-2 eliminate any dc errors. Figure 48 shows the frequency response of 90 MHz and 45 MHz LPFs. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 90 MHz bandwidth with a 2 V p-p output swing requires at least 870 V/μs. This performance is achievable at 90 MHz only because of the wide bandwidth and high slew rate of the ADA4817-1/ADA4817-2. The circuit shown in Figure 49 is a 4-pole, Sallen-Key, low-pass filter (LPF). The filter comprises two identical cascaded SallenKey LPF sections, each with a fixed gain of G = 2. The net gain of the filter is equal to G = 4 or 12 dB. The actual gain shown in Figure 48 is 12 dB. This does not take into account the output voltage being divided in half by the series matching termination resistor, RT, and the load resistor. Setting the resistors equal to each other greatly simplifies the design equations for the Sallen-Key filter. To achieve 90 MHz the value of R should be set to 182 Ω. However, if the value of R is doubled, the corner frequency is cut in half to 45 MHz. This would be an easy way to tune the filter by simply multiplying the value of R (182 Ω) by the ratio of 90 MHz and the new corner frequency in megahertz. Figure 48 shows the output of each stage is of the filter and the two different filters corresponding to R = 182 Ω and R = 365 Ω. It is not recommended to increase the corner frequency beyond 90 MHz due to bandwidth and slew rate limitations unless unity-gain stages are acceptable. 15 12 9 6 3 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 –30 –33 –36 –39 –42 100k OUT2, f = 90MHz OUT1, f = 90MHz OUT1, f = 45MHz OUT2, f = 45MHz 1M C3 3.9pF 10µF +5V RT 49.9Ω R U1 R R C2 5.6pF 10µF 0.1µF 10µF OUT1 U2 R C4 5.6pF 0.1µF RT 49.9Ω 10µF OUT2 0.1µF 0.1µF –5V R2 348Ω –5V R1 348Ω R4 348Ω R3 348Ω Figure 49. 4-Pole Sallen-Key Low-Pass Filter (ADA4817-2) Rev. 0 | Page 21 of 24 07756-054 +IN1 100M Figure 48. Low-Pass Filter Response C1 3.9pF +5V 10M FREQUENCY (Hz) 1G 07756-062 MAGNITUDE (dB) Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements. ADA4817-1/ADA4817-2 1.2 0.15 0.10 0.8 90MHz 90MHz 45MHz 45MHz 0.4 VOLTAGE (V) 0 –0.4 –0.05 –0.8 TIME (5ns/DIV) 07756-063 –0.10 –0.15 0 –1.2 TIME (5ns/DIV) Figure 51. Large Signal Transient Response (Low-Pass Filter) Figure 50. Small Signal Transient Response (Low-Pass Filter) Rev. 0 | Page 22 of 24 07756-064 VOLTAGE (V) 0.05 ADA4817-1/ADA4817-2 OUTLINE DIMENSIONS 0.60 MAX 0.50 BSC 0.60 MAX 5 2.95 2.75 SQ 2.55 TOP VIEW PIN 1 INDICATOR 8 (BOTTOM VIEW) 4 0.90 MAX 0.85 NOM 12° MAX 0.05 MAX 0.01 NOM 0.30 0.23 0.18 SEATING PLANE 1 0.50 0.40 0.30 0.70 MAX 0.65 TYP 1.60 1.45 1.30 EXPOSED PAD 1.89 1.74 1.59 PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 072408-B 3.25 3.00 SQ 2.75 Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters 4.00 BSC SQ 12° MAX 1.00 0.85 0.80 0.65 BSC TOP VIEW 3.75 BSC SQ 0.75 0.60 0.50 0.80 MAX 0.65 TYP SEATING PLANE 16 13 12 9 PIN 1 INDICATOR 1 2.25 2.10 SQ 1.95 8 5 4 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM 0.35 0.30 0.25 (BOTTOM VIEW) 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC 072808-A PIN 1 INDICATOR 0.60 MAX 0.60 MAX Figure 53.16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model ADA4817-1ACPZ-R2 1 ADA4817-1ACPZ-RL1 ADA4817-1ACPZ-R71 ADA4817-2ACPZ-R21 ADA4817-2ACPZ-RL1 ADA4817-2ACPZ-R71 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 Package Option CP-8-2 CP-8-2 CP-8-2 CP-16-4 CP-16-4 CP-16-4 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 Branding H1F H1F H1F ADA4817-1/ADA4817-2 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07756-0-11/08(0) Rev. 0 | Page 24 of 24