INTERSIL ISL6402IV

ISL6402
®
Data Sheet
November 8, 2004
300kHz Dual, 180° Out-of-Phase, StepDown PWM and Single Linear Controller
The ISL6402 is a high-performance, triple-output controller
optimized for converting wall adapter, battery or network
intermediate bus DC input supplies into the system supply
voltages required for a wide variety of applications. Each
output is adjustable down to 0.8V. The two PWMs are
synchronized 180o out of phase reducing the RMS input
current and ripple voltage.
The ISL6402 incorporates several protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the lower
MOSFET. Hiccup mode overcurrent operation protects the
DC-DC components from damage during output
overload/short circuit conditions. Each PWM has an
independent logic-level shutdown input (SD1 and SD2).
A single PGOOD signal is issued when soft-start is complete
on both PWM controllers and their outputs are within 10% of
the set point and the linear regulator output is greater than
75% of its setpoint. Thermal shutdown circuitry turns off the
device if the junction temperature exceeds +150°C.
Ordering Information
PART NUMBER
ISL6402IR
TEMP.
RANGE (°C)
-40 to 85
PACKAGE
28 Ld 5x5 QFN
PKG.
DWG. #
L28.5x5
ISL6402IR-T
28 Ld 5x5 QFN Tape & Reel
L28.5x5
ISL6402IR-TK
28 Ld 5x5 QFN Tape & Reel
L28.5x5
ISL6402IRZ (Note)
-40 to 85
28 Ld 5x5 QFN
(Pb-free)
ISL6402IRZ-TK
(Note)
28 Ld 5x5 QFN Tape & Reel
(Pb-free)
L28.5x5
28 Ld TSSOP
• Three Independently Programmable Output Voltages
• Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . 300kHz
• Out of Phase PWM Controller Operation
- Reduces Required Input Capacitance and Power
Supply Induced Loads
• No External Current Sense Resistor
- Uses Lower MOSFET’s rDS(ON)
• Bidirectional Frequency Synchronization for
Synchronizing Multiple ISL6402s
• Programmable Soft-Start
• Extensive circuit protection functions
- PGOOD
- UVLO
- Overcurrent
- Overtemperature
- Independent Shutdown for Both PWMs
• Excellent Dynamic Response
- Voltage Feed-Forward with Current Mode Control
• QFN Packages:
- QFN - Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
L28.5x5
-40 to 85
• Wide Input Supply Voltage Range . . . . . . . . . 4.5V to 24V
• Pb-Free Available (RoHS Compliant)
28 Ld 5x5 QFN Tape & Reel
(Pb-free)
ISL6402IV
Features
L28.5x5
ISL6402IRZ-T
(Note)
FN9123.3
• Power Supplies with Multiple Outputs
• xDSL Modems/Routers
M28.173
ISL6402IV-T
28 Ld TSSOP Tape & Reel
M28.173
ISL6402IV-TK
28 Ld TSSOP Tape & Reel
M28.173
• DSP, ASIC, and FPGA Power Supplies
• Set-Top Boxes
M28.173
• Dual Output Supplies for DSP, Memory, Logic, µP Core
and I/O
28 Ld TSSOP Tape & Reel
(Pb-free)
M28.173
• Telecom Systems
ISL6402IVZ-TK (Note) 28 Ld TSSOP Tape & Reel
(Pb-free)
M28.173
ISL6402IVZ (Note)
ISL6402IVZ-T (Note)
-40 to 85
28 Ld TSSOP
(Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
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ISL6402
Pinouts
LGATE2 1
28 LGATE1
BOOT2 2
27 BOOT1
BOOT2
LGATE2
LGATE1
BOOT1
UGATE1
PHASE1
ISL6402 (QFN)
TOP VIEW
UGATE2
ISL6402 (TSSOP)
TOP VIEW
UGATE2 3
26 UGATE1
28
27
26
25
24
23
22
PHASE2 4
25 PHASE1
ISEN2 5
24 ISEN1
PGOOD 6
23 PGND
VCC_5V 7
22 SD1
SD2 8
21 SS1
SS2 9
20 SGND
19 OCSET1
OCSET2 10
18 FB1
FB2 11
PHASE2
1
21 ISEN1
ISEN2
2
20 PGND
PGOOD
3
19 SD1
VCC_5V
4
18 SS1
SD2
5
17 SGND
SS2
6
16 OCSET1
OCSET2
7
15 FB1
2
11
12
13
14
GATE3
SGND
10
FB3
9
SYNC
8
VIN
15 FB3
SYNC 14
SGND
16 GATE3
VIN 13
FB2
17 SGND
SGND 12
FN9123.3
November 8, 2004
Block Diagram
SGND
VCC_5V
3
SS1
LDO &
POWER-ON
RESET (POR)
SS2
POR
VIN
SYNC
RAMP
CLOCK
PGOOD
SS1
FB1
SS2
FB2
FB3
OUTPUT
VOLTAGE
MONITOR
GATE3
LINEAR
CONTROLLER
FB3
+5V
REF
CLK
BOOT1
BOOT2
HGDR
UGATE1
HGDR
HI
GATE LOGIC
PWM1
PHASE1
VCC_5V
GATE LOGIC
PWM2
SD1
SHUTDOWN
SD2
PHASE2
VCC_5V
SHUTDOWN
PWM
LGDR
LO
LGATE2
LO
PGND
SD1
SD2
FB1
+
+
+
+
OC
COMP
-
R
+
-
PWM1
LATCH
-
Q S
R
PWM2
LATCH
+
S Q
CLK
CLK
OCSET2
∑
+
∑
REF
-
+
+
OC
LOGIC
-
-
+
SS2
+
OC
COMP
SS1
+
OC
LOGIC
-
-
REF
OCSET1
ISEN1
FB2
-
ISEN2
ISL6402
PWM
LGDR
LGATE1
UGATE2
HI
FN9123.3
November 8, 2004
ISL6402
Typical Application Schematic
+12V
+
C1
C4
VIN
SS1
D1
C3
9
SS2
BOOT1
27
2
UGATE1 26
3
PHASE1 25
4
BOOT2
Q1A
C7
L1
R3
Q1B
+ C9
R1
D2
C5
C2
VOUT1
+1.2V
21
VCC_5V
7
13
C6
Q1A
ISEN1
24
5
UGATE2
C8
PHASE2
ISEN2
R4
L2
VOUT2
+3.3V
LGATE1
PGND
FB1
28
ISL6402
23
11
18
12
R2
SD1
17
22
SD2
1 LGATE2
(See Note)
15
19
10
OCSET1
20 14
SGND
C10
+
R5
FB2
SGND
R6
SGND
16 GATE3
8
R7
Q2B
FB3
VOUT2
+3.3V
OCSET2
R10
6
SYNC
C11
R11
Q3
PGOOD
VOUT3
+2.5V
R8
R12
R9
+ C12
V
VCC_5V
R13
NOTE: Pin numbers correspond to the TSSOP pinout.
4
FN9123.3
November 8, 2004
ISL6402
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC_5V Pin) . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Input Voltage (VIN Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V
BOOT1, 2 and UGATE1, 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . +35V
PHASE1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
BOOT1, 2 with respect to PHASE1, 2 . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1, 2. . . . . . . . . . . . (PHASE1, 2 - 0.3V) to (BOOT1, 2 +0.3V)
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
28 Lead TSSOP (Note 1) . . . . . . . . . . .
75
NA
28 Lead QFN (Note 2) . . . . . . . . . . . . .
33
4
Maximum Junction Temperature (Plastic Package) . -55°C to 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(TSSOP - Lead Tips Only)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJC is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θJA
the “case temp” location is the center of the exposed metal pad on the underside of the package. See Tech Brief TB379.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 3),
Typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5.6
12
24
V
4.5
5.0
5.6
V
VIN SUPPLY
Input Voltage Range
VCC_5V SUPPLY (Note 4)
Input Voltage
Output Voltage
VIN > 5.6V, IL = 20mA
4.5
5.0
5.5
V
Maximum Output Current
VIN = 12V
60
-
-
mA
-
50
375
µA
-
2.0
4.0
mA
-
0.8
-
V
-1.0
-
1.0
%
Rising VCC_5V Threshold
4.25
4.45
4.5
V
Falling VCC_5V Threshold
3.95
4.2
4.4
V
270
300
330
kHz
VIN = 12V
-
1.6
-
V
VIN = 5V
-
0.667
-
V
Ramp Offset (Note 8)
-
1.0
-
V
SYNC Input Rise/Fall Time
-
-
10.0
ns
SYNC Frequency Range
5.1
5.6
6.0
MHz
SYNC Input HIGH Level
3.5
-
-
V
SYNC Input LOW Level
-
-
1.5
V
10
-
-
ns
VCC - 0.6V
-
-
V
SUPPLY CURRENT
Shutdown Current (Note 5)
SD1 = SD2 = GND
Operating Current (Note 6)
REFERENCE SECTION
Nominal Reference Voltage
Reference Voltage Tolerance
POWER-ON RESET
OSCILLATOR
Total Frequency Variation
Peak-to-Peak Sawtooth Amplitude (Note 7)
SYNC Input Minimum Pulse Width
SYNC Output HIGH Level
5
FN9123.3
November 8, 2004
ISL6402
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 3),
Typical values are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2.0
-
-
V
-
-
0.8
V
0.8
-
-
V
-
-
100
nA
Maximum Duty Cycle
93
-
-
%
Minimum Duty Cycle
-
4
-
%
DC Gain (Note 8)
80
88
-
dB
Gain-Bandwidth Product (Note 8)
5.9
-
-
MHz
-
2.0
-
V/µs
Maximum Output Voltage (Note 8)
0.9
-
-
V
Minimum Output Voltage (Note 8)
-
-
3.6
V
-
400
-
mA
SHUTDOWN1/SHUTDOWN2
HIGH Level (Converter Enabled)
Internal Pull-up (3µA)
LOW Level (Converter Disabled)
PWM CONVERTERS
Output Voltage
FB Pin Bias Current
PWM CONTROLLER ERROR AMPLIFIERS
Slew Rate (Note 8)
PWM CONTROLLER GATE DRIVERS (Note 9)
Sink/Source Current
Upper Drive Pull-Up Resistance
VCC_5V = 4.5V
-
8
-
Upper Drive Pull-Down Resistance
VCC_5V = 4.5V
-
3.2
-
Lower Drive Pull-Up Resistance
VCC_5V = 4.5V
-
8
-
Lower Drive Pull-Down Resistance
VCC_5V = 4.5V
-
1.8
-
Rise Time
COUT = 1000pF
-
18
-
ns
Fall Time
COUT = 1000pF
-
18
-
ns
50
-
-
mA
LINEAR CONTROLLER
Drive Sink Current
FB3 Feedback Threshold
I = 21mA
-
0.8
-
V
Undervoltage Threshold
VFB
-
75
-
%
-
-
45
nA
VFB = 0.8V, I = 21mA
-
2
-
A/V
Pull-up = 100kΩ
-
0.1
0.5
V
-
-
±1.0
µA
FB3 Input Leakage Current (Note 8)
Amplifier Transconductance
POWER GOOD AND CONTROL FUNCTIONS
PGOOD LOW Level Voltage
PGOOD Leakage Current
PGOOD Upper Threshold, PWM 1 and 2
Fraction of set point
105
-
120
%
PGOOD Lower Threshold, PWM 1 and 2
Fraction of set point
80
-
95
%
70
75
80
%
-
32
-
µA
-
64
-
µA
-
1.75
-
V
PGOOD for Linear Controller
ISEN and CURRENT LIMIT
Full Scale Input Current (Note 10)
Overcurrent Threshold (Note 10)
ROCSET = 110kΩ
OCSET (Current Limit) Voltage
6
FN9123.3
November 8, 2004
ISL6402
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, TA = -40°C to 85°C (Note 3),
Typical values are at TA = 25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
5
-
µA
Rising
-
150
-
°C
Hysteresis
-
20
-
°C
SOFT-START
Soft-Start Current
PROTECTION
Thermal Shutdown
NOTES:
3. Specifications at -40°C and 85°C are guaranteed by design, not production tested.
4. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min).
When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the
VCC_5V pin. (Refer to the Pin Descriptions section for more details.)
5. This is the total shutdown current with VIN = VCC_5V = PVCC = 5V.
6. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.
7. The peak-to-peak sawtooth amplitude is production tested at 12V only; at 5V this parameter is guaranteed by design.
8. Guaranteed by design; not production tested.
9. Not production tested; guaranteed by characterization only.
10. Guaranteed by design. The full scale current of 32µA is recommended for optimum current sample and hold operation. See the Feedback Loop
Compensation Section below.
7
FN9123.3
November 8, 2004
ISL6402
Typical Performance Curves
3.4
3.4
3.39
3.39
PWM2 OUTPUT VOLTAGE (V)
PWM1 OUTPUT VOLTAGE (V)
(Oscilloscope Plots Are Taken Using the ISL6402EVAL4A Evaluation Board, VIN = 12V, Unless Otherwise Noted)
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.3
0.5
0
LOAD CURRENT (A)
1.5
1
2
2.5
3
4
3.5
4.5
LOAD CURRENT (A)
FIGURE 1. PWM1 LOAD REGULATION
FIGURE 2. PWM2 LOAD REGULATION
PGOOD 5V/DIV
0.85
REFERENCE VOLTAGE (V)
0.84
0.83
VOUT3 2V/DIV
0.82
0.81
0.8
VOUT2 2V/DIV
0.79
0.78
0.77
0.76
VOUT1 2V/DIV
0.75
-40
-20
20
40
0
TEMPERATURE (°C)
60
80
FIGURE 3. REFERENCE VOLTAGE VARIATION OVER
TEMPERATURE
FIGURE 4. SOFT-START WAVEFORMS WITH PGOOD
VOUT2 20mV/DIV, AC COUPLED
VOUT1 20mV/DIV, AC COUPLED
IL2 0.5A/DIV, AC COUPLED
IL1 0.5A/DIV, AC COUPLED
PHASE2 10V/DIV
PHASE1 10V/DIV
FIGURE 5. PWM1 WAVEFORMS
8
FIGURE 6. PWM2 WAVEFORMS
FN9123.3
November 8, 2004
ISL6402
Typical Performance Curves
(Continued)
(Oscilloscope Plots Are Taken Using the ISL6402EVAL4A Evaluation Board, VIN = 12V, Unless Otherwise Noted)
VOUT1 200mV/DIV
AC COUPLED
VOUT1 200mV/DIV
AC COUPLED
IOUT1 1A/DIV
IOUT1 1A/DIV
FIGURE 7. LOAD TRANSIENT RESPONSE VOUT1 (3.3V)
VCC_5V 1V/DIV
FIGURE 8. LOAD TRANSIENT RESPONSE VOUT2 (3.3V)
VOUT1 2V/DIV
IL1 2A/DIV
SS1 2V/DIV
VOUT1 1V/DIV
FIGURE 10. OVERCURRENT HICCUP MODE OPERATION
FIGURE 9. PWM SOFT-START WAVEFORM
100
PWM2 EFFICIENCY (%)
PWM1 EFFICIENCY (%)
100
90
80
70
60
0
2
1
3
4
LOAD CURRENT (A)
FIGURE 11. PWM1 EFFICIENCY vs LOAD (3.3V), VIN = 12V
9
90
80
70
60
0
1
2
3
4
LOAD CURRENT (A)
FIGURE 12. PWM2 EFFICIENCY vs LOAD (3.3V), VIN = 12V
FN9123.3
November 8, 2004
ISL6402
Pin Descriptions
BOOT2, BOOT1 - These pins power the upper MOSFET
drivers of each PWM converter. Connect this pin to the
junction of the bootstrap capacitor and the cathode of the
bootstrap diode. The anode of the bootstrap diode is
connected to the VCC_5V pin.
UGATE2, UGATE1 - These pins provide the gate drive for
the upper MOSFETs.
PHASE2, PHASE1 - These pins are connected to the junction
of the upper MOSFETs source, output filter inductor and lower
MOSFETs drain.
LGATE2, LGATE1 - These pins provide the gate drive for
the lower MOSFETs.
PGND - This pin provides the power ground connection for
the lower gate drivers for both PWM1 and PWM2. This pin
should be connected to the sources of the lower MOSFETs
and the (-) terminals of the external input capacitors.
FB3, FB2, FB1 - These pins are connected to the feedback
resistor divider and provide the voltage feedback signals for
the respective controller. They set the output voltage of the
converter. In addition, the PGOOD circuit uses these inputs
to monitor the output voltage status.
ISEN2, ISEN1 - These pins are used to monitor the voltage
drop across the lower MOSFET for current loop feedback
and overcurrent protection.
PGOOD - This is an open drain logic output used to indicate
the status of the output voltages. This pin is pulled low when
either of the two PWM outputs is not within 10% of the
respective nominal voltage, or if the linear controller output is
less than 75% of it’s nominal value.
SGND - (Pin 20 on the TSSOP; Pin 17 on the QFN)
This is the small-signal ground, common to all 3 controllers,
and must be routed separately from the high current ground
(PGND). All voltage levels are measured with respect to this
pin. Connect the additional SGND pins to this pin. If using a
5V supply, connect this pin to VCC_5V. A small ceramic
capacitor should be connected right next to this pin for noise
decoupling.
VIN - Use this pin to power the device with an external
supply voltage with a range of 5.6V to 24V. For 5V ±10%
operation, connect this pin to VCC_5V.
VCC_5V - This pin is the output of the internal 5V linear
regulator. This output supplies the bias for the IC, the low
side gate drivers, and the external boot circuitry for the high
side gate drivers. The IC may be powered directly from a
single 5V (±10%) supply at this pin. When used as a 5V
supply input, this pin must be externally connected to VIN.
The VCC_5V pin must be always decoupled to power
ground with a minimum of 4.7µF ceramic capacitor, placed
very close to the pin.
10
SYNC - This pin may be used to synchronize two or more
ISL6402 controllers. This pin requires a 1K resistor to
ground if used; connect directly to VCC_5V if not used.
SS1, SS2 - These pins provide a soft-start function for their
respective PWM controllers. When the chip is enabled, the
regulated 5µA pull-up current source charges the capacitor
connected from this pin to ground. The error amplifier
reference voltage ramps from 0 to 0.8V while the voltage on
the soft-start pin ramps from 0 to 0.8V.
SD1, SD2 - These pins provide an enable/disable function
for their respective PWM output. The output is enabled when
this pin is floating or pulled HIGH, and disabled when the pin
is pulled LOW.
GATE3 - This pin is the open drain output of the linear
regulator controller.
OCSET2, OCSET1 - A resistor from this pin to ground sets
the overcurrent threshold for the respective PWM.
Functional Description
General Description
The ISL6402 integrates control circuits for two synchronous
buck converters and one linear controller. The two
synchronous bucks operate out of phase to substantially
reduce the input ripple and thus reduce the input filter
requirements. The chip has four control lines (SS1, SD1,
SS2, and SD2), which provide independent control for each
of the synchronous buck outputs.
The buck PWM controllers employ a free-running frequency
of 300kHz. The current mode control scheme with an input
voltage feed-forward ramp input to the modulator provides
excellent rejection of input voltage variations and provides
simplified loop compensations.
The linear controller can drive either a PNP or PFET to
provide ultra low-dropout regulation with programmable
voltages.
Internal 5V Linear Regulator (Vcc_5V)
All ISL6402 functions are internally powered from an onchip, low dropout 5V regulator. The maximum regulator input
voltage is 24V. Bypass the regulator’s output (Vcc_5V) with
a 4.7µF capacitor to ground. The dropout voltage for this
LDO is typically 600mV, so when Vcc_5V is greater then
5.6V, Vcc_5V is typically 5V. The ISL6402 also employs an
undervoltage lockout circuit that disables both regulators
when Vcc_5V falls below 4.4V.
The internal LDO can source over 60mA to supply the IC,
power the low side gate drivers, charge the external boot
capacitor and supply small external loads. When driving
large FETs especially at 300kHz frequency, little or no
regulator current may be available for external loads.
FN9123.3
November 8, 2004
ISL6402
For example, a single large FET with 15nC total gate charge
requires 15nC X 300kHz = 4.5mA. Also, at higher input
voltages with larger FETs, the power dissipation across the
internal 5V will increase. Excessive dissipation across this
regulator must be avoided to prevent junction temperature
rise. Larger FETs can be used with 5V ±10% input
applications. The thermal overload protection circuit will be
triggered, if the VCC_5V output is short circuited. Connect
VCC_5V to VIN for 5V ±10% input applications.
VOUT1 1V/DIV
VOUT2 1V/DIV
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the
enabled PWM channels starts to ramp gradually, due to the
5µA current sourced into the external capacitor. The output
voltage follows the soft-start voltage.
When the SS pin voltage reaches 0.8V, the output voltage of
the enabled PWM channel reaches the regulation point, and
the soft-start pin voltage continues to rise. At this point the
PGOOD and fault circuitry is enabled. This completes the
soft-start sequence. Any further rise of SS pin voltage does
not affect the output voltage. By varying the values of the
soft-start capacitors, it is possible to provide sequencing of the
main outputs at start-up. The soft-start time can be obtained
from the following equation:
C SS
T SOFT = 0.8V  -----------
 5µA
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING
STARTUP
Output Voltage Programming
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to FBx pin. The output voltage
value is determined by the following equation.
R1 + R2
V OUTx = 0.8V  ----------------------
 R2 
where R1 is the top resistor of the feedback divider network
and R2 is the resistor connected from FBx to ground.
Out-of-Phase Operation
VCC_5V 1V/DIV
VOUT1 1V/DIV
SS1 1V/DIV
FIGURE 13. SOFT-START OPERATION
The soft-start capacitors can be chosen to provide startup
tracking for the two PWM outputs. This can be achieved by
choosing the soft-start capacitors such that the soft-start
capacitor ration equals the respective PWM output voltage
ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V
then the soft-start capacitor ration should be, CSS1/CSS1 =
1.2/3.3 = 0.364. Figure 14 shows that soft-start waveform
with CSS1 = 0.01µF and CSS2 = 0.027µF.
11
The two PWM controllers in the ISL6402 operate 180o outof-phase to reduce input ripple current. This reduces the
input capacitor ripple current requirements, reduces power
supply-induced noise, and improves EMI. This effectively
helps to lower component cost, save board space and
reduce EMI.
Dual PWMs typically operate in-phase and turn on both
upper FETs at the same time. The input capacitor must then
support the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current. The higher RMS ripple current lowers
the efficiency due to the power loss associated with the ESR
of the input capacitor. This typically requires more low-ESR
capacitors in parallel to minimize the input voltage ripple and
ESR-related losses, or to meet the required ripple current
rating.
With dual synchronized out-of-phase operation, the highside MOSFETs of the ISL6402 turn on 180o out-of-phase.
The instantaneous input current peaks of both regulators no
longer overlap, resulting in reduced RMS ripple current and
input voltage ripple. This reduces the required input
capacitor ripple current rating, allowing fewer or less
expensive capacitors, and reducing the shielding
requirements for EMI. The typical operating curves show the
synchronized 180 degree out-of-phase operation.
FN9123.3
November 8, 2004
ISL6402
Input Voltage Range
The ISL6402 is designed to operate from input supplies
ranging from 4.5V to 24V. However, the input voltage range
can be effectively limited by the available maximum duty
cycle (DMAX = 93%).
V OUT + V d1
V IN ( min ) =  -------------------------------- + V d2 – V d1


0.93
where,
Vd1 = Sum of the parasitic voltage drops in the inductor
discharge path, including the lower FET, inductor and PC
board.
Vd2 = Sum of the voltage drops in the charging path,
including the upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum on-time (tON(min)).
V OUT
V IN ( max ) ≤ ---------------------------------------------------t ON ( min ) × 300kHz
where, tON(min) = 30ns
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing amplification, level shifting
and shoot-through protection. The gate drivers have some
circuitry that helps optimize the ICs performance over a wide
range of operational conditions. As MOSFET switching
times can vary dramatically from type to type and with input
voltage, the gate control logic provides adaptive dead time
by monitoring real gate waveforms of both the upper and the
lower MOSFETs. Shoot-through control logic provides a
20ns deadtime to ensure that both the upper and lower
MOSFETs will not turn on simultaneously and cause a shootthrough condition.
Gate Drivers
The low-side gate driver is supplied from VCC_5V and
provides a peak sink/source current of 400mA. The highside gate driver is also capable of 400mA current. Gate-drive
voltages for the upper N-Channel MOSFET are generated
by the flying capacitor boot circuit. A boot capacitor
connected from the BOOT pin to the PHASE node provides
power to the high side MOSFET driver. To limit the peak
current in the IC, an external resistor may be placed
between the UGATE pin and the gate of the external
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board an the FET’s input
capacitance.
12
VIN
VCC_5V
BOOT
UGATE
PHASE
ISL6402
FIGURE 15.
At start-up the low-side MOSFET turns on and forces
PHASE to ground in order to charge the BOOT capacitor to
5V. After the low-side MOSFET turns off, the high-side
MOSFET is turned on by closing an internal switch between
BOOT and UGATE. This provides the necessary gate-tosource voltage to turn on the upper MOSFET, an action that
boosts the 5V gate drive signal above VIN. The current
required to drive the upper MOSFET is drawn from the
internal 5V regulator.
Protection Circuits
The converter output is monitored and protected against
overload, short circuit and undervoltage conditions. A
sustained overload on the output sets the PGOOD low and
initiates hiccup mode.
Overcurrent Protection
Cycle by cycle current limiting scheme is implemented as
below. Both PWM controllers use the lower MOSFET’s onresistance, rDS(ON) , to monitor the current in the converter.
The sensed voltage drop is compared with a threshold set by
a resistor connected from the OCSETx pin to ground.
( 7 ) ( R CS )
R OCSET = -----------------------------------------( I OC ) ( R DS ( on ) )
where, IOC is the desired overcurrent protection threshold,
and RCS is a value of the current sense resistor connected
to the ISENx pin. If the lower MOSFET current exceeds the
overcurrent threshold, a pulse skipping circuit is activated.
Figure 16 shows the inductor current, output voltage, and the
PHASE node voltage just as an overcurrent trip occurs. The
upper MOSFET will not be turned on as long as the sensed
current is higher than the threshold value. This limits the
current supplied by the DC voltage source. If an overcurrent
is detected for 2 consecutive clock cycles then the IC enters
a hiccup mode by turning off the gate drivers and entering
into soft-start. The IC will cycle 2 times through soft-start
before trying to restart. The IC will continue to cycle through
soft-start until the overcurrent condition is removed.
Figure 17 shows this behavior.
FN9123.3
November 8, 2004
ISL6402
VOUT2 2V/DIV
resistor is required and must be sized to provide a low
enough time constant to pass the SYNC pulse. Connect this
pin to VCC_5V if not used. Figure 18 shows the SYNC pin
waveform operating at 16 times the switching frequency.
IL 2V/DIV
PHASE2 10V/DIV
FIGURE 16. OVERCURRENT TRIP WAVEFORMS
VOUT2 2V/DIV
IOUT2 2V/DIV
FIGURE 18. SYNC WAVEFORM
Feedback Loop Compensation
SS2 2V/DIV
FIGURE 17. OVERCURRENT CONTINUOUS HICCUP MODE
WAVEFORMS
Because of the nature of this current sensing technique, and
to accommodate a wide range of rDS(ON) variations, the
value of the overcurrent threshold should represent an
overload current about 150% to 180% of the maximum
operating current. If more accurate current protection is
desired place a current sense resistor in series with the
lower MOSFET source.
Over-Temperature Protection
The IC incorporates an over-temperature protection circuit
that shuts the IC down when a die temperature of 150°C is
reached. Normal operation resumes when the die
temperatures drops below 130°C through the initiation of a
full soft-start cycle.
Implementing Synchronization
The SYNC pin may be used to synchronize two or more
controllers. When the SYNC pins of two controllers are
connected together, one controller becomes the master and
the other controller synchronizes to the master. A pull-down
13
To reduce the number of external components and to
simplify the process of determining compensation
components, both PWM controllers have internally
compensated error amplifiers. To make internal
compensation possible several design measures were
taken.
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant with variation in the
input voltage. Second, the load current proportional signal is
derived from the voltage drop across the lower MOSFET
during the PWM time interval and is subtracted from the
amplified error signal on the comparator input. This creates
an internal current control loop. The resistor connected to
the ISEN pin sets the gain in the current feedback loop. The
following expression estimates the required value of the
current sense resistor depending on the maximum operating
load current and the value of the MOSFET’s rDS(ON).
( I MAX ) ( R DSon ) )
R CS ≥ --------------------------------------------32µA
Choosing RCS to provide 32µA of current to the current
sample and hold circuitry will ensure accurate overcurrent
detection.
FN9123.3
November 8, 2004
ISL6402
Due to the current loop feedback, the modulator has a single
pole response with -20dB slope at a frequency determined
by the load.
upper resistor R1 of the divider that sets the output voltage
value. Please refer to the output inductor and capacitor
selection sections for further details.
1
F PO = --------------------------------- ,
2π ⋅ R O ⋅ C O
Linear Regulator
where RO is load resistance and CO is load capacitance. For
this type of modulator, a Type 2 compensation circuit is
usually sufficient.
Figure 19 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.
1
F Z = ------------------------------- = 6kHz
2π ⋅ R 2 ⋅ C 1
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
charge may build up on the output capacitor making VLDO
rise above its set point. Care must be taken to insure that the
feedback resistor’s current exceeds the pass transistors
leakage current over the entire temperature range.
1
F P = ------------------------------- = 600kHz
2π ⋅ R 1 ⋅ C 2
C2
R2
C1
CONVERTER
R1
EA
TYPE 2 EA
GM = 17.5dB
GEA = 18dB
MODULATOR
FZ
FPO
The linear regulator controller is a transconductance
amplifier with a nominal gain of 2 A/V. The N-channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With zero volts differential at it’s
input, the controller sinks 21mA of current. An external PNP
transistor or PFET pass element can be used. The dominant
pole for the loop can be placed at the base of the PNP (or
gate of the PFET), as a capacitor from emitter to base
(source to gate of a PFET). Better load transient response is
achieved however, if the dominant pole is placed at the
output, with a capacitor to ground at the output of the
regulator.
FP
FC
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear will track the PWM supply after the PWM output rises
to a voltage greater than the threshold of the PFET pass
device. The voltage differential between the PWM and the
linear output will be the load current times the rDS(ON).
Figure 20 shows the linear regulator (2.5V) startup waveform
and the PWM (3.3V) startup waveform.
FIGURE 19. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor CZ in parallel with the
14
VOUT2 1V/DIV
VOUT3 1V/DIV
FIGURE 20. LINEAR REGULATOR STARTUP WAVEFORM
FN9123.3
November 8, 2004
ISL6402
energy so they tend to generate a large amount of noise.
The critical small signal components are those connected to
sensitive nodes or those supplying critical bias currents. A
multi-layer printed circuit board is recommended.
ERROR AMPLIFIER SINK
CURRENT (mA)
60
50
Layout Considerations
40
1. The Input capacitors, Upper FET, Lower FET, Inductor
and Output capacitor should be placed first. Isolate these
power components on the topside of the board with their
ground terminals adjacent to one another. Place the input
high frequency decoupling ceramic capacitor very close
to the MOSFETs.
30
20
10
0
0.79
0.8
0.82
0.83
0.81
FEEDBACK VOLTAGE (V)
0.84
0.85
FIGURE 21. LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly loaded.
Capacitively coupled switching noise or inductively coupled
EMI onto the base drive causes fluctuations in the base
current, which appear as noise on the linear regulator’s
output. Keep the base drive traces away from the step-down
converter, and as short as possible, to minimize noise
coupling. A resistor in series with the gate drivers reduces
the switching noise generated by PWM. Additionally, a
bypass capacitor may be placed across the base-to-emitter
resistor. This bypass capacitor, in addition to the transistor’s
input capacitor, could bring in second pole that will destabilize the linear regulator. Therefore, the stability
requirements determine the maximum base-to-emitter
capacitance.
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of a ISL6402 based DC-DC
converter. The ISL6402 switches at a very high frequency
and therefore the switching times are very short. At these
switching frequencies, even the shortest trace has
significant impedance. Also the peak gate drive current rises
significantly in extremely short time. Transition speed of the
current from one device to another causes voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
generate EMI, increase device overvoltage stress and
ringing. Careful component selection and proper PC board
layout minimizes the magnitude of these voltage spikes.
There are two sets of critical components in a DC-DC
converter using the ISL6402. The switching power
components and the small signal components. The
switching power components are the most critical from a
layout point of view because they switch a large amount of
15
2. Use separate ground planes for power ground and small
signal ground. Connect the SGND and PGND together
close of the IC. Do not connect them together anywhere
else.
3. The loop formed by Input capacitor, the top FET and the
bottom FET must be kept as small as possible.
4. Insure the current paths from the input capacitor to the
MOSFET; to the output inductor and output capacitor are
as short as possible with maximum allowable trace
widths.
5. Place The PWM controller IC close to lower FET. The
LGATE connection should be short and wide. The IC can
be best placed over a quiet ground area. Avoid switching
ground loop current in this area.
6. Place Vcc_5V bypass capacitor very close to Vcc_5V pin
of the IC and connect its ground to the PGND plane.
7. Place the gate drive components BOOT diode and BOOT
capacitors together near controller IC
8. The output capacitors should be placed as close to the
load as possible. Use short wide copper regions to
connect output capacitors to load to avoid inductance and
resistances.
9. Use copper filled polygons or wide but short trace to
connect junction of upper FET. Lower FET and output
inductor. Also keep the PHASE node connection to the IC
short. Do not unnecessary oversize the copper islands for
PHASE node. Since the phase nodes are subjected to
very high dv/dt voltages, the stray capacitor formed
between these islands and the surrounding circuitry will
tend to couple switching noise.
10. Route all high speed switching nodes away from the
control circuitry.
11. Create separate small analog ground plane near the IC.
Connect SGND pin to this plane. All small signal
grounding paths including feedback resistors, current
limit setting resistors, SYNC/SDx pull down resistors
should be connected to this SGND plane.
12. Ensure the feedback connection to output capacitor is
short and direct.
FN9123.3
November 8, 2004
ISL6402
Component Selection Guidelines
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency
given the potentially wide input voltage range and output
power requirements. Two N-Channel MOSFETs are used in
each of the synchronous-rectified buck converters for the
PWM1 and PWM2 outputs. These MOSFETs should be
selected based upon rDS(ON), gate supply requirements,
and thermal management considerations.
The power dissipation includes two loss components;
conduction loss and switching loss. These losses are
distributed between the upper and lower MOSFETs
according to duty cycle (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper MOSFET
has significant switching losses, since the lower device turns
on and off into near zero voltage. The equations assume
linear voltage-current transitions and do not model power
loss due to the reverse-recovery of the lower MOSFET’s
body diode.
2
( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW )
P UPPER = -------------------------------------------------------------- + -----------------------------------------------------------V IN
2
2
( I O ) ( r DS ( ON ) ) ( V IN – V OUT )
P LOWER = -----------------------------------------------------------------------------V IN
A large gate-charge increases the switching time, tSW,
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications.
Output Capacitor Selection
response time, as in a hard drive or CD drive, it reduces the
requirement on the output capacitor.
The maximum capacitor value required to provide the full,
rising step, transient load current during the response time of
the inductor is:
2
( L O ) ( I TRAN )
C OUT = ---------------------------------------------------------2 ( V IN – V O ) ( DV OUT )
where, COUT is the output capacitor(s) required, LO is the
output inductor, ITRAN is the transient load current step, VIN
is the input voltage, VO is output voltage, and DVOUT is the
drop in output voltage allowed during the load transient.
High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Equivalent Series Resistance) and
voltage rating requirements as well as actual capacitance
requirements.
The output voltage ripple is due to the inductor ripple current
and the ESR of the output capacitors as defined by:
V RIPPLE = ∆I L ( ESR )
where, IL is calculated in the Inductor Selection section.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load
circuitry for specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications at 300kHz for the bulk
capacitors. In most cases, multiple small-case electrolytic
capacitors perform better than a single large-case capacitor.
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements
including ripple voltage and load transients. Selection of
output capacitors is also dependent on the output inductor,
so some inductor analysis is required to select the output
capacitors.
The stability requirement on the selection of the output
capacitor is that the ‘ESR zero’, f Z, be between 1.2kHz and
30kHz. This range is set by an internal, single compensation
zero at 6kHz. The ESR zero can be a factor of five on either
side of the internal zero and still contribute to increased
phase margin of the control loop. Therefore,
One of the parameters limiting the converter’s response to a
load transient is the time required for the inductor current to
slew to it’s new level. The ISL6402 will provide either 0% or
71% duty cycle in response to a load transient.
In conclusion, the output capacitors must meet three criteria:
The response time is the time interval required to slew the
inductor current from an initial current value to the load
current level. During this interval the difference between the
inductor current and the transient current level must be
supplied by the output capacitor(s). Minimizing the response
time can minimize the output capacitance required. Also, if
the load transient rise time is slower than the inductor
16
1
C OUT = ------------------------------------2Π ( ESR ) ( f Z )
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load
transient,
2. The ESR must be sufficiently low to meet the desired
output voltage ripple due to the output inductor current,
and
3. The ESR zero should be placed, in a rather large range,
to provide additional phase margin.
FN9123.3
November 8, 2004
ISL6402
Output Inductor Selection
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and output capacitor(s) ESR. The ripple voltage
expression is given in the capacitor selection section and the
ripple current is approximated by the following equation:
( V IN – V OUT ) ( V OUT )
∆I L = --------------------------------------------------------( f S ) ( L ) ( V IN )
Input Capacitor Selection
The important parameters for the bulk input capacitor(s) are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and 1.5 times is a conservative
guideline. The AC RMS Input current varies with the load.
The total RMS current supplied by the input capacitance is:
2
2
I RMS1 + I RMS2
where,
I RMSx =
DC – DC
5
4.5
4
2
IN PHASE
3.5
3
2.5
OUT OF PHASE
2
1.5
5V
3.3V
1
0.5
0
For the ISL6402, use Inductor values between 1µH to 3.3µH.
I RMS =
reflected currents and is significantly less than the combined
in-phase current.
INPUT RMS CURRENT
The recommended output capacitor value for the ISL6402 is
between 150µF to 680µF, to meet stability criteria with
external compensation. Use of aluminum electrolytic,
POSCAP, or tantalum type capacitors is recommended. Use
of low ESR ceramic capacitors is possible but would take
more rigorous loop analysis to ensure stability.
0
1
2
3
3.3V AND 5V LOAD CURRENT
4
5
FIGURE 22. INPUT RMS CURRENT vs LOAD
Use a mix of input bypass capacitors to control the voltage
ripple across the MOSFETs. Use ceramic capacitors for the
high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors can be placed very
close to the upper MOSFET to suppress the voltage induced
in the parasitic circuit impedances.
For board designs that allow through-hole components, the
Sanyo OS-CON® series offer low ESR and good
temperature performance. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX is
surge current tested.
DC is duty cycle of the respective PWM.
Depending on the specifics of the input power and its
impedance, most (or all) of this current is supplied by the
input capacitor(s). Figure 22 shows the advantage of having
the PWM converters operating out of phase. If the
converters were operating in phase, the combined RMS
current would be the algebraic sum, which is a much larger
value as shown. The combined out-of-phase current is the
square root of the sum of the square of the individual
17
FN9123.3
November 8, 2004
ISL6402
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
9
MILLIMETERS
D/2
D1
D1/2
2X
N
6
INDEX
AREA
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE C)
0.15 C A
D
A
L28.5x5
0.15 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
0.30
5,8
A3
1
2
3
E1/2
b
E/2
E1
E
9
0.15 C B
2X
0.15 C A
4X
0
A
9
4X P
2.95
3.10
-
4.75 BSC
2.95
3.10
9
3.25
7,8
-
0.50 BSC
-
k
0.25
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
28
2
7
3
8
Ne
8
7
P
-
-
0.60
θ
-
-
12
7
NX k
D2
2 N
4X P
(DATUM A)
2
3
6
INDEX
AREA
E2/2
N e
9
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
8
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
9
NOTES:
(Ne-1)Xe
REF.
E2
7
NX L
3
Rev. 0 02/03
1
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
5
C
L
7,8
Nd
D2
8
3.25
5.00 BSC
0.10 M C A B
5
NX b
(DATUM B)
A1
A3
9
e
/ / 0.10 C
0.08 C
SIDE VIEW
-
4.75 BSC
E2
C
SEATING PLANE
5.00 BSC
E1
A2
9
D
E
B
TOP VIEW
0.23
D1
D2
2X
0.20 REF
0.18
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
L1
10
L
L1
e
10
L
e
C C
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
18
FN9123.3
November 8, 2004
ISL6402
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
α
e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
28
0o
28
7
8o
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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19
FN9123.3
November 8, 2004