Dual (180° Out-of-Phase) PWM and Linear Controller ISL6446 Features The ISL6446 is a high-performance, triple output controller that provides a single high-frequency power solution primarily for Broadband, DSL and Networking applications. This device integrates complete control, monitoring and protection functions for two synchronous buck PWM controllers and one linear controller. Input voltage ripple and total RMS input current is substantially reduced by synchronized 180° out-of-phase operation of the two PWMs. • 4.5V to 5.5V or 5.5V to 24V input voltage range The two PWM buck converters provide simple voltage mode control. The output voltage of the converters can be precisely regulated to as low as 0.6V, with a maximum tolerance of ±1.5% over-temperature and line variations. Programmable switching frequency down to 100kHz provides optimized low cost solution for ATX power supplies. It’s also able to operate up to 2.5MHz to deliver compact solutions. The linear controller provides a low-current output. • Three programmable power output voltages - Two PWM controllers with out-of-phase operation - Voltage-mode PWM control - One linear controller • Programmable switching frequency from 100kHz to 2.5MHz • Fast transient response - High-bandwidth error amplifier • Extensive circuit protection functions - Undervoltage, and over-temperature - Overvoltage with latch-off mode - Programmable overcurrent limit with latch-off mode - Lossless current sensing (no sense resistor needed) Each PWM controller has soft-start and independent enable functions combined on a single pin. A capacitor from SS/EN to ground sets the soft-start time; pulling SS/EN pin below 1V disables the controller. Both outputs can soft-start into a pre-biased load. • Externally adjustable soft-start time The ISL6446 incorporates robust protection features. An adjustable overcurrent protection circuit monitors the output current by sensing the voltage drop across the upper MOSFET rDS(ON). Latch-off mode overcurrent operation protects the DC/DC converters from damage under overload and short circuit conditions. A PGOOD signal is issued when soft-start is complete and PWM outputs are within 10% of their regulated values and the linear regulator output is higher than 75% of its nominal value. Thermal shut-down circuitry turns the device off if the IC temperature exceeds +150°C. • PGOOD output with delay VCC - Independent enable control - Voltage tracking capability - Able to soft-start into a pre-biased load Applications • ATX power supplies • DSP, ASIC, and FPGA point of load regulation • Industrial and security networking applications VIN CVCC VCC COMP1 FB1 R1 VOUT2 Feedback and Compensation Network COMP2 FB2 ROCSET1 VIN1 = VIN VIN COCSET1 OCSET1 C BOOT1 BOOT1 Q1 CIN1 UGATE1 VOUT1 PHASE1 L1 LGATE1 COUT1 Q2 ROCSET2 ISL6446 VIN2 = VIN COCSET2 OCSET2 C BOOT2 BOOT2 Q3 C IN2 UGATE2 R2 PGOOD RT SS1/EN1 SS2/EN2 SGND PHASE2 LGATE2 L2 Q4 LCDR LCFB PGND VOUT2 COUT2 100 98 96 94 EFFICIENCY (%) VOUT1 Feedback and Compensation Network VOUT = 5V 92 VOUT = 3.3V 90 88 86 84 82 80 0 5 10 15 20 25 LOAD CURRENT (A) FIGURE 1. TYPICAL APPLICATION October 15, 2013 FN7944.1 1 FIGURE 2. EFFICIENCY vs LOAD CURRENT (OBTAINED FROM ISL6446EVAL1Z) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL6446 Pin Configuration ISL6446 (24 LD QSOP) TOP VIEW OCSET1 1 24 VIN SS1/EN1 2 23 BOOT1 COMP1 3 22 UGATE1 FB1 4 21 PHASE1 RT 5 20 LGATE1 SGND 6 19 VCC LCDR 7 18 PGND LCFB 8 17 LGATE2 FB2 9 16 PHASE2 COMP2 10 15 UGATE2 SS2/EN2 11 14 BOOT2 OCSET2 12 13 PGOOD Pin Descriptions SYMBOL PIN # DESCRIPTION BOOT1, 2 23, 14 These pins power are the upper MOSFET drivers of each PWM converter. The anode of each internal bootstrap diode is connected to the VCC pin. The cathode of the bootstrap diode is connected to this pin, which should also connect to the bootstrap capacitor. UGATE1, 2 22, 15 These pins provide the gate drive for upper MOSFETs, bootstrapped from the VCC pin. PHASE1, 2 21, 16 These are the junction points of the upper MOSFET sources, the output filter inductor and lower MOSFET drains. Connect these pins accordingly to the respective converter. LGATE1, 2 20, 17 These are the outputs of the lower N-Channel MOSFET drivers, sourced from the VCC pin. PGND 18 This pin provides the power ground connection for the lower gate drivers. This pin should be connected to the source of the lower MOSFET for PWM1 and PWM2 and the negative terminals of the external input capacitors. FB1, 2 4, 9 These pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. They set the output voltage of the converter. In addition, the PGOOD circuit and OVP circuit use these inputs to monitor the output voltage status. COMP1, 2 3, 10 These pins are the error amplifier outputs for the respective PWM. They are used, along with the FB pins, as the compensation point for the PWM error amplifier. PGOOD 13 This is an open drain logic output used to indicate the status of the output voltages. This pin is pulled low when either of the two PWM outputs is not within 10% of the respective nominal voltage or when the linear output drops below 75% of its nominal voltage. To maintain the PGOOD function if the linear output is not used, connect LCFB to VCC. SGND 6 This is the signal ground, common to both controllers, and must be routed separately from the high current grounds (PGND). All voltage levels are measured with respect to this pin. VIN 24 This pin powers the controllers with an internal linear regulator (if VIN > 5.5V) and must be closely decoupled to ground using a ceramic capacitor as close to the VIN pin as possible. The VIN is the input voltage applied to the upper FET of both converters. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 5.5V to 24V Connect the input supply to the VIN pin. The VCC pin will provide a 5V output from the internal voltage regulator. 5V ±10% VCC 19 Connect the input supply to the VCC pin. This pin supplies the bias for the regulators, powers the low-side gate drivers and external boot circuitry for high-side gate drivers. The IC may be powered directly from a single 5V (±10%) supply at this pin; when used as a 5V supply input, this pin must be externally connected to VIN. When VIN > 5.5, VCC is the output of the internal 5V linear regulator output. The VCC pin must always be decoupled to power ground with a minimum of 1µF ceramic capacitor, placed very close to the pin. 2 FN7944.1 October 15, 2013 ISL6446 Pin Descriptions (Continued) SYMBOL PIN # DESCRIPTION RT 5 This is the operating frequency adjustment pin. By placing a resistor from this pin to the SGND, the oscillator frequency can be programmed from 100kHz to 2.5MHz. SS1/EN1 SS2/EN2 2, 11 These pins provide enable/disable and soft-start function for their respective controllers. The output is held off when the pin is pulled to ground. When the chip is enabled, the regulated 30µA pull-up current source charges the capacitor connected from the pin to ground. The output voltage of the converter follows the ramping voltage on the SS/EN pin. See “Soft-Start and Voltage Tracking” on page 11 for more details. LCFB 8 This pin is the feedback pin for the linear controller. An external voltage divider network connected to this pin sets the output voltage of the linear controller. If the linear controller is not used, tie this pin to the VCC. LCDR 7 Open drain output PNP Transistor or P-channel MOSFET Driver. The LCDR connects to the base of an external PNP pass transistor or the gate of the MOSFET to form a positive linear regulator. A small resistor can be inserted between the LCDR and the base of the PNP pass transistor or the gate of the MOSFET to alleviate thermal stress at output short condition. OCSET1, 2 1, 12 These pins are the overcurrent set points for the respective PWM controllers. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 110µA current source, and the upper MOSFET ON-resistance rDS(ON) set the converter overcurrent (OC) trip point according to Equation 1: I OCSET • R OCSET I OC = --------------------------------------------------r DS ( ON ) (EQ. 1) IOC includes the DC load current, as well as the ripple current. An overcurrent trip initiates hiccup mode. The voltage on the OCSET pin should not exceed 0.7V above the VIN pin voltage for proper current sensing when the UGATE is turned on. Ordering Information PART NUMBER (Notes 1, 2, 3) ISL6446IAZ PART MARKING ISL 6446IAZ TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-free) 24 Ld QSOP PKG. DWG. # M24.15 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6446. For more information on MSL please see tech brief TB363. 3 FN7944.1 October 15, 2013 ISL6446 Block Diagram VIN VCC VCC REFERENCE BIAS CURRENT POWER ON RESET AND CONTROL 30µA 100µA 0.6V 5V LINEAR REGULATOR 110µA OCSET1 VCC BOOT1 UVP1 OVP1 PG1 EN1 OUTPUT1 DRIVERS COMP1 FB1 PWM1 0.6V VCC5 30µA FAULT1 VCC5 30µA SS1 UVP1 OVP1 PG1 EN1 STARTUP SS1/EN1 SS1 EN1 SS2/EN2 SS2 EN2 UGATE1 GATE CONTROL LOGIC VCC DEAD-TIME CONTROL SS2 UVP2 OVP2 PG2 EN2 LGATE1 OVERCURRENT PGND RAMP1 0° 110µA CLOCK AND SAWTOOTH GENERATOR OCSET2 VCC FAULT2 PHASE1 BOOT2 UVP2 OVP2 PG2 EN2 RAMP2 180° UGATE2 OUTPUT2 DRIVERS PWM2 0.6V GATE CONTROL LOGIC VCC DEAD-TIME CONTROL PHASE2 LGATE2 FB2 OVERCURRENT PGND COMP2 FAULT3 PG3 LCFB RT PG1 PG2 PG3 PGOOD 0.6V gm*VE LCFB LCDR PGND SGND FIGURE 3. BLOCK DIAGRAM 4 FN7944.1 October 15, 2013 ISL6446 Typical Application Schematics VOLTAGE INPUTS REQUIRED VIN (4.5V TO 24V) = VIN1 = VIN2 VCC VCC (5V; INTERNAL IF VIN > 5.6V) VIN OPTIONAL CONNECTION (FOR VIN = VCC = 5V) VIN3 (≤ VCC) FOR LINEAR CVCC CVIN TYPE-3 COMPENSATION SHOWN ROCSET1 C102 VCC COMP1 C101 R102 OCSET1 BOOT1 R101 VOUT1 VIN1 = VIN VIN COCSET1 CBOOT1 FB1 C103 R103 UGATE1 R100 C202 R202 VOUT2 0.9µH LGATE1 COMP2 C201 C203 2x680µF/18m 2x100µF 1x47µF Q102 FB2 ROCSET2 OCSET2 TYPE-3 COMPENSATION SHOWN VIN2 = VIN BOOT2 COCSET2 CBOOT2 Q201 CIN2 UGATE2 0.9µH VOUT2 VCC L200 PHASE2 COUT2 Q202 LGATE2 RPGOOD 2x680µF/18m 2x100µF R304 PGOOD RT VIN3 C301 SS1/EN1 R303 R302 CIN3 LCDR SS2/EN2 Q301 VOUT3 LCFB RRT COUT1 ISL6446 R200 CSS1/EN1 CSS2/EN2 VOUT1 L100 PHASE1 R201 R203 CIN1 Q101 SGND PGND R300 R301 COUT3 FIGURE 4. ISL6446 TYPICAL APPLICATION 5 FN7944.1 October 15, 2013 ISL6446 Absolute Maximum Ratings Thermal Information (Note 4) SS1/EN1, SS2/EN2, COMP1, COMP2 to SGND . . . . . . . . . . -0.3V to +6.0V VCC, FB1, FB2, RT, PGOOD to SGND . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V LCDR, LCFB to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V VIN, OCSET1, and OCSET2 to PGND. . . . . . . . . . . . . . . . . . . . . -0.3V to +28V BOOT1 and BOOT2 to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT1 to PHASE1, and BOOT2 to PHASE2. . . . . . . . . . . . . . -0.3V to +6.0V UGATE1 to PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (BOOT1 +0.3V) UGATE2 to PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (BOOT2 +0.3V) LGATE1, LGATE2 to PGND . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VCC+0.3V) PHASE1, PHASE2 to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to 28V SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 2500V Machine Model (Tested per JESD22-115-A) . . . . . . . . . . . . . . . . . . . 150V Latch Up (Tested per JEDEC-78B Level II Class A) . . . . ±100mA @ +85°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) QSOP Package (Notes 5, 6). . . . . . . . . . . . . 75 36 Maximum Junction Temperature (Plastic Package) . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% VIN Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V to 24V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. All voltages are measured with respect to GND. 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical values are at +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C PARAMETER SYMBOL TEST CONDITIONS Input Operating Supply Current ICC_op VIN = 5.5V or 12V; LGATEx, UGATEx Open, FB forced above regulation point (no switching) Input Standby Supply Current ICC_sb VIN = 5.5V, 12V, 24V; SS1/EN1 = SS2/EN2 = 0V Output Voltage VVCC VIN = 5.6V, SS1/EN1 = SS2/EN2 = 0V No Additional Load Output Voltage VVCC VIN = 24V, SS1/EN1 = SS2/EN2 = 0V No Additional Load Output Voltage VVCC VIN = 12V, SS1/EN1 = SS2/EN2 = 0V IVCC= 80mA MIN (Note 9) TYP MAX (Note 9) UNITS 4.5 7.5 mA 1.25 3 mA VIN SUPPLY VCC INTERNAL REGULATOR VCC Current Limit (Note 7) IICC_CL VCC is pulled to PGND; (Note 8) VREF1, VREF2 VIN = 5V or 12V; TA = +25°C 4.5 5.35 5.36 4.5 V 5.6 V 5.2 V 300 mA 0.6000 V REFERENCE AND SOFT-START Reference Voltage at FB1, FB2 Reference Voltage at FB1, FB2 VREF1, VREF2 VIN = 5V or 12V; TA = 0°C to +85°C 0.5925 0.6085 V VIN = 5V or 12V; TA = -40°C to +85°C 0.5900 0.6085 V VIN = 24V; TA = +25°C 0.6015 V VIN = 24V; TA = 0°C to +85°C 0.5930 0.6100 V VIN = 24V; TA = -40°C to +85°C 0.5915 0.6100 V ENx/SSx Soft-Start Current ISSx 20 30 40 µA ENx/SSx Enable Threshold VENx 850 940 1050 mV ENx/SSx Enable Threshold Hysteresis 6 VENx_hys (Note 7) 15 mV FN7944.1 October 15, 2013 ISL6446 Electrical Specifications Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical values are at +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued) PARAMETER SYMBOL ENx/SSx Soft-Start Top of Ramp Voltage VSSx_top TEST CONDITIONS MIN (Note 9) (Note 7) TYP MAX (Note 9) 3.12 UNITS V POWER-ON RESET ON VCC Rising Threshold VPOR_r 4.2 4.4 4.48 V Falling Threshold VPOR_f 3.85 4.0 4.1 V PWM CONVERTERS Minimum UGATE on Time tUGATE_min (Note 7) 100 ns Maximum Duty Cycle DCmax VIN = 5.0V or 12V; FSW = 300kHz 95 % Maximum Duty Cycle DCmax VIN = 5.0V; FSW = 2.58MHz 80 % FBx Pin Bias Current IFBx VFB1 = VFB2 = 600mV Low End Frequency FSW VIN = 12V; RT = 163kΩ Oscillation Frequency FSW VIN = 5V or 12V; RT = 52.3kΩ 270 300 330 kHz VIN = 24V; RT = 52.3kΩ 270 305 340 kHz VIN = 5V; RT = 4.75kΩ 2.25 2.5 2.75 MHz VIN = 12V; RT = 4.75kΩ 2.25 2.59 2.85 MHz -250 30 250 nA OSCILLATOR High End Frequency FSW Frequency Adjustment Range FSW kHz RT = 163kΩ; (Note 7) 0.1 MHz RT = 4.75kΩ; (Note 7) 2.6 MHz (Note 8) 1.25 V VPWM_OFF (Note 8) 1.25 V 2.6 Ω 2 Ω 2.6 Ω 2 Ω PWM Sawtooth Ramp Amplitude (Peak-to-Peak) VP-P PWM Sawtooth Ramp Offset 103 PWM CONTROLLER GATE DRIVERS (Note 7) Upper Gate Pull-up Resistance Upper Gate Pull-down Resistance Lower Gate Pull-up Resistance Upper Gate Pull-down Resistance Rise Time CL = 3300pF 25 ns Fall Time CL = 3300pF 25 ns 20 ns Dead Time Between Drivers ERROR AMPLIFIERS DC Gain Gain-Bandwidth Product Slew Rate Gain (Note 8) 88 dB GBWP (Note 8) 15 MHz COMP = 10pF (Note 8) 5 V/µs 4.2 V SR Maximum Output Voltage VEA_H ICOMP_SRC = 40µA Minimum Output Voltage VEA_L ICOMP_SINK = 40µA 3.9 0.8 1.1 V PROTECTION AND OUTPUT MONITOR Overvoltage Threshold OV 111 116 121 % Undervoltage Threshold UV 77 82 88 % OCSET Current Source IOCSET 7 VOCSET = 4.5V, TA = -40°C 80 µA FN7944.1 October 15, 2013 ISL6446 Electrical Specifications Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical values are at +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued) PARAMETER SYMBOL TEST CONDITIONS OCSET Current Source IOCSET VOCSET = 4.5V, TA = +25°C OCSET Current Source IOCSET VOCSET = 4.5V, TA = +85°C Drive Sink Current ILCDR LCDR LCFB Feedback Threshold VLCFB TA = +25°C MIN (Note 9) TYP MAX (Note 9) 110 UNITS µA 140 µA LINEAR CONTROLLER LCFB Input Leakage Current ILCFB Error Amplifier Transconductance gm 50 mA 0.595 V TA = -40°C to +85°C 0.570 0.620 V TA = 0°C to +70°C 0.580 0.610 V (Note 7) 80 nA VLCFB = 0.6V, ILCDR = 21mA (Note 7) 2 A/V PGOOD Power-Good Lower Threshold PG_lowx LCFB = VCC, LDO disabled PGOOD for Ch1 and Ch2 only 88 93 97 % Power-Good Higher Threshold PG_hix LCFB = VCC, LDO disabled PGOOD for Ch1 and Ch2 only 105 110 115 % Power-Good Lower Threshold PG_low3 LDO enabled, PGOOD for LDO; Ch1 and Ch2 disabled; (Note 7) 72 % PGOOD Delay tPGOOD FSW = 1.4MHz (Note 7) 46 ms PGOOD Leakage Current IPGOOD VPULLUP = 5.5V 5 µA PGOOD Voltage Low VPG_low IPGOOD = -4mA 0.5 V THERMAL Shutdown Temperature (Note 8) 150 °C Shutdown Hysteresis (Note 8) 20 °C NOTES: 7. Limits established by characterization. 8. Design guideline only; not production tested. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8 FN7944.1 October 15, 2013 ISL6446 Typical Performance Curves Oscilloscope plots are taken using the ISL6446EVAL1Z evaluation board, VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, fs = 300kHz, unless otherwise noted. PHASE 1 48mVP-P PHASE 2 VOUT1/AC 43mVP-P FIGURE 5. OUTPUT RIPPLE (PWM1) VIN = 12V VOUT = 5V IOUT = 5A~15A VOUT2/AC FIGURE 6. OUTPUT RIPPLE (PWM2) VIN = 12V VOUT1 = 5V VOUT2 = 3.3V VOUT1/AC PHASE 1 IOUT1 = 0A IOUT2 = 0A ISTEP 1A/50mV IL1 PHASE 2 FIGURE 8. PWM INTERLEAVING FIGURE 7. LOAD TRANSIENT VIN = 12V VOUT1 = 5V VOUT2 = 3.3V PHASE 1 IOUT1 = 25A IOUT2 = 25A PHASE 2 FIGURE 9. PWM INTERLEAVING 9 FN7944.1 October 15, 2013 ISL6446 Typical Performance Curves Oscilloscope plots are taken using the ISL6446EVAL1Z evaluation board, VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, fs = 300kHz, unless otherwise noted. (Continued) VIN = 12V VOUT1 = 5V VOUT2 = 3.3V EN/SSx TIED TOGETHER EN/SSx EN/SSx TIED TOGETHER VIN = 12V VOUT1 = 5V VOUT2 = 3.3V VOUT1 VOUT1 VOUT2 VOUT2 IOUT1 = 0A IOUT2 = 0A IOUT1 = 25A IOUT2 = 25A FIGURE 11. EN/SS START-UP FIGURE 10. EN/SS START-UP VIN = 12V VOUT1 = 5V VOUT2 = 3.3V EN/SSx EN/SSx VIN = 12V VOUT1 = 5V VOUT2 = 3.3V EN/SSx VOUT1 VOUT1 VOUT2 IOUT1 = 0A IOUT2 = 0A FIGURE 12. EN/SS SHUT-DOWN VIN = 12V VOUT1 = 5V IOUT = 0A VOUT2 IOUT1 = 25A IOUT2 = 25A FIGURE 13. EN/SS SHUT-DOWN VIN = 12V VOUT1 = 5V IOUT = 10A~20A EN/SSx EN/SS VOUT PHASE IL LGATE VOUT PHASE FIGURE 14. PRE-BIASED START-UP (VOUT PRE-BIASED AT 3.5V) 10 FIGURE 15. OVERCURRENT PROTECTION FN7944.1 October 15, 2013 ISL6446 Typical Performance Curves Oscilloscope plots are taken using the ISL6446EVAL1Z evaluation board, VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, fs = 300kHz, unless otherwise noted. (Continued) VIN = 12V VOUT1 = 5V IOUT = S/C VIN = 12V VOUT1 = 5V IOUT = 10, FB = 1V EN/SSx EN/SSx VOUT IL IL VOUT PHASE PHASE FIGURE 16. START-UP WITH OC FIGURE 17. OVERVOLTAGE PROTECTION Functional Description Soft-Start and Voltage Tracking After the VCC pin exceeds its rising POR trip point (nominal 4.4V), the chip operation begins. Both 30µA current sources will start charging up the soft-starting capacitors respectively. The charging continues until the voltage across the soft-start capacitor reaches about 3.2V. From 1.0V to 1.6V, the outputs will ramp individually from zero to full-scale. Now, if V = 0.6V, C = 0.1µF, and I = 30µA, then t = 2ms. Figure 18 shows the typical waveforms for SS2/EN2 and VOUT2; SS1/EN1 and VOUT1 are similar. SS2/EN2 (0.5V/DIV) Finally, there is a delay after 1.6V, until the ramp gets to ~3.2V, which signals that the ramp is done; when both ramps are done, the PGOOD delay begins. To guarantee the soft-start is completed, please make sure the EN/SSx pin voltage is able to reach above 3.2V at normal operation. VOUT2 (1V/DIV) VOUT (1V/DIV) GND> 1.6V 1.0V 1.6V SS1/EN1 (0.5V/DIV) SS2/EN2 (0.5V/DIV) 1.0V VOUT2 (2V/DIV) GND> FIGURE 19. VOLTAGE TRACKING GND> FIGURE 18. SOFT-START The soft-start ramps for each output can be selected independently. The basic timing is shown in Equation 2: dV t = C • ------I (EQ. 2) Figure 20 shows pre-biased outputs before soft-start. The solid blue curve shows no pre-bias; the output starts ramping from GND. The magenta dotted line shows the output pre-biased to a voltage less than the final output. The FETs don’t turn on until the soft-start ramp voltage exceeds the output voltage; then the output starts ramping seamlessly from there. The cyan dotted line shows the output pre-biased above the final output (but below the OVP (Overvoltage Protection)). The FETs will not turn on until the end of the soft-start ramp; then the output will be quickly pulled down to the final value. If the output is pre-biased above the OVP level, the ISL6446 will go into OVP at the end of soft-start, which will keep the FETs off. See “Protection Mechanisms” on page 13 for more details. where: t is the charge time C is the external capacitance dV is the voltage charged I is the charging current (nominal 30µA) 11 FN7944.1 October 15, 2013 ISL6446 VOUT1 has the same functionality as previously described for VOUT2. Each output should react independently of the other, unless they are related by the circuit configuration. . PGOOD (5V/DIV) GND> SS2/EN2 (0.5V/DIV) VOUT3 (2V/DIV) GND> VOUT2 (2V/DIV) GND> VOUT2 OVER-CHARGED VOUT2 (2V/DIV) VOUT1 (2V/DIV) GND> VOUT2 PRE-BIASED FIGURE 21. PGOOD DELAY GND> Switching Frequency FIGURE 20. SOFT-START WITH PRE-BIAS The linear output does not have a soft-start ramp; however, it may follow the ramp of its input supply, if timed to coincide with its rise, after the VCC rising POR trip. If the input to the linear is from one of the two switcher outputs, then it will share the same ramp rate as the switcher. PGOOD A group of comparators (separate from the protection comparators) monitor the output voltages (via the FB pins) for PGOOD. Each switcher has a lower and upper boundary (nominally around 90% and 110% of the target value) and the linear has a lower boundary (around 75% of the target). Once both switcher output ramps are done, and all 3 outputs are within their expected ranges, the PGOOD will start an internal timer, with Equation 3: 0.065 t PGOOD = --------------F SW The switching frequency of the ISL6446 is determined by the external resistor placed from the RT pin to SGND. See Figure 22 for a graph of Frequency vs RT Resistance. Use Equation 4 to calculate the approximate RT resistor value for the desired switching frequency. The typical resistance for 100kHz operation is 163kΩ. Running at both high frequency and high VIN voltages is not recommended, due to the increased power dissipation on-chip (mostly from the internal VCC regulator, which supplies gate drivers). The user should check the maximum acceptable IC temperature, based on their particular conditions. F SW – 1.093 R T = ⎛ ----------------⎞ ⎝ 11290⎠ 300k (EQ. 3) tPGOOD is the delay time (in sec) FSW is the switching frequency (in MHz) Once the time-out is complete, the internal pull-down device will shut off, allowing the open-drain PGOOD output to rise through an external pull-up resistor, to a 5V (or lower) supply, which signals that the “Power is GOOD”. Figure 21 shows the three outputs turning on, and the delay for PGOOD. If any of the conditions is subsequently violated, then PGOOD goes low. Once the voltage returns to the normal region, a new delay will start, after which the PGOOD will go high again. 100k RT VALUE (Ω) where: (EQ. 4) 50k 30k 10k 3k 100k 200k 500k 1M 2M SWITCHING FREQUENCY (Hz) FIGURE 22. FREQUENCY vs RT RESISTOR The PGOOD delay is inversely proportional to the clock frequency. If the clock is running as slow as 524kHz, the delay will be 125ms long. There is no way to adjust the PGOOD delay independently of the clocK. 12 FN7944.1 October 15, 2013 ISL6446 Figure 23 shows the generic feedback resistor circuit for any of the two PWM VOUT’s; the VOUT is divided down to equal the reference. All three use a 0.6V internal reference (check the “Electrical Specifications” Table on page 6 for the exact reference value at 24V). The RUP is connected to the VOUT; the RLOW to GND; the common point goes to the FB pin. VOUT FB EA RUP COMP RLOW 0.6V VOUT must be greater than 0.6V and 2 resistors are needed, and their accuracy directly affect the regulator tolerance. UP (EQ. 5) LOW Use Equation 6 to choose the resistor values. RUP is part of the compensation network for the switchers, and should be selected to be compatible; 1kΩ to 5kΩ is a good starting value. Find FB from the “Electrical Specifications” Table on page 7 (for the right condition), plug in the desired value for VOUT, and solve for RLOW. FB ⋅ R UP R LOW = -----------------------------V OUT – FB (EQ. 6) The maximum duty cycle of the ISL6446 approaches 100% at low frequency, but falls off at higher frequency; see the “Electrical Specifications” Table on page 7. In addition, there is a minimum UGATE pulse width, in order to properly sense overcurrent. The two switchers are 180° out of phase. Linear Regulator The linear regulator controller is a trans-conductance amplifier with a nominal gain of 2A/V. The N-Channel MOSFET output buffer can sink a minimum of 50mA. The reference voltage is 0.6V. With 0V differential at its input, the controller sinks 21mA of current. For better load regulation, it is recommended that the resistor from the LDO input to the base of the PNP (or gate of the PFET) is set so that the sink current at G4 pin is within 9mA to 31mA over the entire load and temperature range. An external PNP transistor or P-Channel MOSFET pass device can be used. The dominant pole for the loop can be placed at the base of the PNP (or gate of the PFET), as a capacitor from emitter-to-base (source to gate of a PFET). Better load transient response is achieved however, if the dominant pole is placed at 13 60 50 40 30 20 10 0 0.59 FIGURE 23. OUTPUT REGULATION R LOW FB = V OUT ⋅ ----------------------------------R +R the output with a capacitor to ground at the output of the regulator. ERROR AMPLIFIER SINK CURRENT (mA) Output Regulation 0.6 0.62 0.63 0.61 FEEDBACK VOLTAGE (V) 0.64 0.65 FIGURE 24. LINEAR CONTROLLER GAIN Protection Mechanisms OCP - (Function independent for both PWM). The overcurrent function protects the PWM Converter from a shorted output by using the upper MOSFET’s ON-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function latches off the outputs to provide fault protection. A resistor connected to the drain of the upper MOSFET and OCSET pin programs the overcurrent trip level. The PHASE node voltage will be compared against the voltage on the OCSET pin, while the upper MOSFET is on. A current (typically 110µA) is pulled from the OCSET pin to establish the OCSET voltage. If PHASE is lower than OCSET while the upper MOSFET is on then an overcurrent condition is detected for that clock cycle. The upper gate pulse is immediately terminated, and a counter is incremented. If an overcurrent condition is detected for 32 consecutive clock cycles, the ISL6446 output is latched off with gate drivers three-stated. The switcher will restart when the SS/EN pin is externally driven below 1V, or if power is recycled to the chip. During soft-start, both pulse termination current limiting and the 32-cycle counter are enabled. UVP - (Function independent for both PWM). If the voltage on the FB pin falls to 82% (typical) of the reference voltage for 8 consecutive PWM cycles, then the circuit enters into soft-start hiccup mode. During hiccup, the external capacitor on the SS/EN pin is discharged, then released and a soft-start cycle is initiated. The UVP comparator is separate from the one sensing for PGOOD, which should have already detected a problem, before the UVP trips. OVP - (Function independent for both PWM). OVP function is enabled after the soft start has finished. If voltage on the FB pin rises to 116% (typical) of the reference voltage, the lower gate driver is turned on continuously. If the overvoltage condition continues for 32 consecutive PWM cycles, then that output is latched off with the gate drivers three-stated. The capacitor on the SS/EN pin will not be discharged. The switcher will restart when the SS/EN pin is externally driven below 1V, or if power is recycled to the chip. The OVP comparator is separate from the one sensing for PGOOD, which should have already detected a problem, before the OVP trips. FN7944.1 October 15, 2013 ISL6446 Application Guidelines L OUT × I TRAN t FALL = --------------------------------------V OUT PWM Controller DISCUSSION The PWM must be compensated such that it achieves the desired transient performance goals, stability, and DC regulation requirements. The first parameter that needs to be chosen is the switching frequency, FSW. This decision is based on the overall size constraints and the frequency plan of the end equipment. Smaller space requires higher frequency. This allows the output inductor, input capacitor bank, and output capacitor bank to be reduced in size and/or value. The power supply must be designed such that the frequency and its distribution over component tolerance, time and temperature causes minimal interference in RF stages, IF stages, PLL loops, mixers, etc. INDUCTOR SELECTION The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current, and the ripple voltage is a function of the ripple current. The ripple current and voltage are approximated by the following Equations 7 and 8, where ESR is the output capacitance ESR value. V IN - V OUT V OUT I = -------------------------------- • ---------------F SW • L V IN (EQ. 7) ΔVOUT = ΔI x ESR (EQ. 8) Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance value reduces the converter’s response time to a load transient (and usually increases the DCR of the inductor, which decreases the efficiency). Increasing the switching frequency (FSW) for a given inductor also reduces the ripple current and voltage. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6446 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. (EQ. 10) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Finally, check that the inductor Isat rating is sufficiently above the maximum output current (DC load plus ripple current). OUTPUT CAPACITOR SELECTION An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Keep in mind that not all applications have the same requirements; some may need many ceramic capacitors in parallel; others may need only one. Use only specialized low-ESR capacitors intended for switchingregulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slewrate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. The response time to a transient is different for the application of load and the removal of load. The following Equations give the approximate response time interval for application and removal of a transient load: L OUT × I TRAN t RISE = --------------------------------------V IN – V OUT (EQ. 9) 14 FN7944.1 October 15, 2013 ISL6446 INPUT CAPACITOR SELECTION Feedback Compensation Equations Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 (upper FET) turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 (lower FET). This section highlights the design consideration for a voltage mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 25). The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. SWITCHER MOSFET SELECTION VIN for the ISL6446 has a wide operating voltage range allowed, so both FETs should have a source-drain breakdown voltage (VDS) above the maximum supply voltage expected; 20V or 30V are typical values available. The ISL6446 gate drivers (UGATEx and LGATEx) were designed to drive single FETs (for up to ~10A of load current) or smaller dual FETs (up to 4A). Both sets of drivers are sourced by the internal VCC regulator (unless VIN = VCC = 5V, in which case the gate driver current comes from the external 5V supply). The maximum current of the regulator (ICC_max) is listed in the “Electrical Specifications” Table on page 6; this may limit how big the FETs can be. In addition, the power dissipation of the regulator is a major contributor to the overall IC power dissipation (especially as Cin of the FET or VIN or FSW increases). Since VCC is around 5V, that affects the FET selection in two ways. First, the FET gate-source voltage rating (VGS) can be as low as 12V (this rating is usually consistent with the 20V or 30V breakdown chosen above). Second, the FETs must have a low threshold voltage (around 1V), in order to have its rDS(ON) rating at VGS = 4.5V in the 10mΩ to 40mΩ range that is typically used for these applications. While some FETs are also rated with gate voltages as low as 2.7V, with typical thresholds under 1V, these can cause application problems. As LGATE shuts off the lower FET, it does not take much ringing in the LGATE signal to turn the lower FET back on, while the Upper FET is starting to turn on, causing some shoot-through current. Therefore, avoid FETs with thresholds below 1V. . C2 R2 C1 COMP FB R1 C3 ISL6446 R3 VOUT FIGURE 25. COMPENSATION CONFIGURATION FOR ISL6446 CIRCUIT Figure 26 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable to the ISL6446 circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) modified sawtooth wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank’s equivalent series resistance is represented by the series resistor E. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis, L and D represent the channel inductance and its DCR, while C and E represent the total output capacitance and its equivalent series resistance. If the power efficiency of the system is important, then other FET parameters are also considered. Efficiency is a measure of power losses from input to output, and it contains two major components: losses in the IC (mostly in the gate drivers) and losses in the FETs. For low duty cycle applications (such as 12V in to 1.5V out), the upper FET is usually chosen for low gate charge, since switching losses are key, while the lower FET is chosen for low rDS(ON), since it is on most of the time. For high duty cycles (such as 5.0V in to 3.3V out), the opposite may be true. 15 FN7944.1 October 15, 2013 ISL6446 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). C2 R2 COMP C3 R3 C1 1 C1 = -----------------------------------------------2π ⋅ R2 ⋅ 0.5 ⋅ F LC E/A R1 FB + Ro 3. Calculate C2 such that FP1 is placed at FCE. VREF C1 C2 = --------------------------------------------------------2π ⋅ R2 ⋅ C1 ⋅ F CE – 1 VOUT OSCILLATOR VIN PWM CIRCUIT VOSC UGATE HALF-BRIDGE DRIVE L D PHASE LGATE ISL6446 (EQ. 14) C E EXTERNAL CIRCUIT FIGURE 26. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN 1 F LC = --------------------------2π ⋅ L ⋅ C (EQ. 11) 1 F CE = -----------------------2π ⋅ C ⋅ E (EQ. 12) (EQ. 15) 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R1 R3 = ---------------------F SW ------------ – 1 F LC 1 C3 = ------------------------------------------------2π ⋅ R3 ⋅ 0.7 ⋅ F SW (EQ. 16) It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): d MAX ⋅ V IN 1 + s(f) ⋅ E ⋅ C G MOD ( f ) = ------------------------------ ⋅ ---------------------------------------------------------------------------------------2 V OSC 1 + s( f) ⋅ (E + D) ⋅ C + s (f) ⋅ L ⋅ C (EQ. 17) The compensation network consists of the error amplifier (internal to the ISL6446) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1 , R2, R3, C1 , C2, and C3) in Figure 26. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate the value for R2 for desired converter bandwidth (F0). If setting the output voltage via an offset resistor connected to the FB pin, Ro in Figure 26, the design procedure can be followed as presented in Equation 13. V OSC ⋅ R1 ⋅ F 0 R2 = --------------------------------------------d MAX ⋅ V IN ⋅ F LC (EQ. 13) 16 1 + s ( f ) ⋅ R2 ⋅ C1 G FB ( f ) = ------------------------------------------------------ ⋅ s ( f ) ⋅ R1 ⋅ ( C1 + C2 ) 1 + s ( f ) ⋅ ( R1 + R3 ) ⋅ C3 ⋅ ----------------------------------------------------------------------------------------------------------------------------C1 ⋅ C2 ( 1 + s ( f ) ⋅ R3 ⋅ C3 ) ⋅ ⎛ 1 + s ( f ) ⋅ R2 ⋅ ⎛ ----------------------⎞ ⎞ ⎝ C1 + C2⎠ ⎠ ⎝ G CL ( f ) = G MOD ( f ) ⋅ G FB ( f ) (EQ. 18) (EQ. 19) where: s ( f ) = 2π ⋅ f ⋅ j COMPENSATION BREAK FREQUENCY EQUATIONS 1 F Z1 = -------------------------------2π ⋅ R2 ⋅ C1 (EQ. 20) 1 F Z2 = --------------------------------------------------2π ⋅ ( R1 + R3 ) ⋅ C3 (EQ. 21) 1 F P1 = ----------------------------------------------C1 ⋅ C2 2π ⋅ R2 ⋅ ---------------------C1 + C2 (EQ. 22) 1 F P2 = -------------------------------2π ⋅ R3 ⋅ C3 (EQ. 23) FN7944.1 October 15, 2013 ISL6446 VIN ISL6446 UGATE Q1 LOUT PHASE CIN Q2 LGATE VOUT COUT LOAD Figure 27 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the previously mentioned guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 27 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. PGND RETURN FP2 R2 20 log ⎛⎝ --------⎞⎠ R1 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN d MAX ⋅ V IN 20 log ----------------------------V OSC 0 FIGURE 28. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS CVCC GFB PGND FCE F0 LOG FIGURE 27. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW. Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Figure 28 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 28 should be located as close together as possible. Please note that the capacitors CIN and COUT each represent numerous physical capacitors. Locate the ISL6446 within 1 inch of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6446 must be sized to handle up to 2A peak current. 17 PHASE +VIN RT FREQUENCY Q1 L OUT ISL6446 SS Q2 COUT VOUT VIN GMOD FLC BOOT CBOOT C IN GCL LOG +VIN VCC LOAD FP1 GAIN FZ1 FZ2 SGND PGND RRT CSS CVIN PGND SGND FIGURE 29. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 29 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Locate the RT resistor as close as possible to the RT pin and the SGND pin. Provide local decoupling between VCC and GND pins. For each switcher, minimize any leakage current paths on the SS/EN pin and locate the capacitor, CSS close to the SS/EN pin because the internal current source is only 30µA. All of the compensation network components for each switcher should be located near the associated COMP and FB pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins (but keep the noisy PHASE plane away from the IC (except for the PHASE pin connection). The OCSET circuits (see Figure 4 on page 5) should have a separate trace from the upper FET to the OCSET R and C; that will more accurately sense the VIN at the FET than just tying them to the VIN plane. The OCSET R and C should be placed near the IC pins. FN7944.1 October 15, 2013 ISL6446 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE October 15, 2013 FN7944.1 Figure 1 on page 1: Changed CVCC from common ground tied to PGND earth ground. Figure 4 on page 5: Changed CVIN from common ground tied to PGND earth ground . Figure 29 on page 17: Changed CVCC from common ground tied to PGND earth ground . On page 6, Absolute Maximum Rating table under ESD rating: changed HBM from 2000V to 2500V and changed MM from 200V to 150V. Converted to new POD format. Added land pattern. July 10, 2012 FN7944.0 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. 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For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7944.1 October 15, 2013 ISL6446 Package Outline Drawing M24.15 24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (QSOP/SSOP) 0.150” WIDE BODY Rev 3, 2/13 24 6.19 5.80 INDEX 3.98 3.81 AREA 5 4 0.25(0.010) M B M -B- 1 TOP VIEW DETAIL “X” SEATING PLANE -A- 8.74 8.55 3 1.75 1.35 GAUGE PLANE -C- SIDE VIEW 1 1.27 0.41 0.25 0.10 0.635 BSC 7 0.30 0.20 0.25 0.010 0.10(0.004) 0.49 x 45° 5 0.26 0.17(0.007) M C A M B S 7.11 8° 0° 5.59 1.54 SIDE VIEW 2 0.25 0.18 4.06 0.38 0.635 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Terminal numbers are shown for reference only. 7. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 8. Controlling dimension: MILLIMETER. TYPICAL RECOMMENDED LAND PATTERN 19 FN7944.1 October 15, 2013