SPM1006EVM User Guide SPM1006 Evaluation Board User Guide Introduction The SPM1006 Evaluation Board (EVM) is designed as an easy to use platform to facilitate an extensive evaluation of the features and performance of the Sumida integrated Point of Load (POL) power supply series, SPM1006. Sumida's PSI2 (Power Supply in Inductor) technology achieves optimal inductor design, low temperature rise and uniform thermal distribution. Instant PWM control is used to achieve excellent transient response to line and load changes without sacrificing stability. It is highly recommended that readers review the SPM1006 datasheet before using this EVM board. The SPM1006 power module has adjustable output voltage. The SPM1006EVM is initially set to provide an output of 5V, but the output voltage can be changed to any voltage between 0.6V and 5V by changing a single resistor on the board. Refer to page 3 for more details. Fig. 1 SPM1006 Evaluation Board (EVM) Brief Description The SPM1006EVM features an SPM1006 integrated Point of Load (POL) using Sumida's PSI2 technology for operation with nominal 12 V or 24V input bus applications. The input voltage range is from 4V to 28V. The output voltage is set to 5V when the SPM1006EVM is shipped, but can be set to any required voltage between 0.6V and 5V by changing one resistor. The SPM1006EVM uses a recommended PCB layout that maximizes thermal performance and minimizes output ripple and noise. The full 6A rated continuous output current (8A peak current) can be supplied by the EVM without thermal derating up to 85°C - refer to the datasheet for details. A recommended amount of input and output capacitance is included on the evaluation board. The SPM1006 includes an internal soft-start function that provides a soft-start time of approximately 600μs. The loop compensation components are also internal to the SPM1006. The switching frequency is not fixed, and changes with the load current as described on page 5. Version 1.0 November 13, 2015 Page 1 of 11 SPM1006EVM User Guide Test points (TP) are provided to allow measurement of efficiency, power dissipation, input voltage ripple, output voltage ripple, line and load regulation, and transient response. Additional test points are provided to monitor the power-good (PWRGD) and enable (EN) features of SPM1006. Getting Started CAUTION: The Evaluation Board does not include protection against excessive input voltage or reversed polarity. Make sure the input and output wires are correctly connected to the board, and take care not to exceed the ratings of the SPM1006. Fig.1 shows the interface items associated with the SPM1006EVM. The polarized power input PVIN terminal block (TB1) is used for connection to the input power supply and the polarized VOUT terminal block (TB2) is used for connection to the load. The power terminal blocks (TB1 and TB2) can accept up to 12 AWG (2mm diameter) wire. Wire-loop test points have been provided as convenient connection points for digital voltmeters (DVM) or oscilloscope probes to help evaluation of the SPM1006. The first set of PVIN-PGND (TP1, TP3) and VOUT-PGND (TP13, TP14) test points located close to the power terminal blocks are intended for voltage monitoring (e.g. efficiency measurements) where voltmeters can be connected to measure PVIN (TP1 and TP3) and VOUT (TP13 and TP14). Do not use these PVIN and VOUT test points as the input supply or output load connection points. The PCB traces connected to these test points are not designed to support high currents. The second set of PVIN-PGND (TP2 and TP4) and VOUT-PGND (TP12 and TP15) test points located closer to the SPM1006 module are intended to measure the voltage ripple via oscilloscope probes for either PVIN or VOUT. To test the features of the device, some control test points are also provided and are located around the power module on the EVM. Any external connections made to these test points should be referenced to one of the two AGND analog ground test points (TP7 or TP16). Refer to Table 1 of this user guide for more information on the individual control test points. Version 1.0 November 13, 2015 Page 2 of 11 SPM1006EVM User Guide Fig. 2 Interface Items of the SPM1006EVM showing voltage setting resistor (R4) Test Point Descriptions A description of each test point is listed in Table 1. Table 1. Test Point Descriptions TEST POINT PVIN (TP1, TP2) DESCRIPTION Power Input voltage monitor. The DC input voltage can be measured by connecting DVM terminals across TP1 and TP3 (PGND). The input voltage ripple can be measured by connecting a scope probe across TP2 and TP4 (PGND). PGND (TP3, TP4, TP14, TP15) Power ground reference. Reference terminal to measure voltages of PVIN or VOUT. AGND (TP16, TP17) The analog or signal ground of the EVM board. These test points are provided to serve as reference voltage for control signals of the module (such as PWRGD, EN, SS) and for VAUX. The AGND traces are not designed for high currents and should not be used as a current return path for input or output power. AGND is connected to PGND at a single point by a zero ohms resistor (R22) to prevent any induced circulating current or voltage drop caused by large currents of the power stage. Version 1.0 November 13, 2015 Page 3 of 11 SPM1006EVM User Guide TEST POINT VOUT (TP11, TP12, TP13) VAUX (TP8) PWRGD (TP6) EN (TP5) PHASE (TP9) DESCRIPTION Output voltage monitor. The output voltage of the SPM1006 module can be measured by connecting a DVM across TP11 and TP14 (PGND). The output voltage of this EVM board can be measured by connecting DVM terminals across TP13 and TP14 (PGND). The output voltage ripple and transient response can be measured by connecting the scope probe across TP12 and TP15 (PGND). Note that TP11 is connected directly to the output pins of the SPM1006 and TP13 is connected to the output terminal of the EVM board. Depending on the load current there may be a very small voltage drop between TP11 and TP13 caused by the PCB track. The voltage sensing pin (VSENSE+) of the SPM1006 is connected to the output capacitors in the EVM board. The voltage at TP11 will change slightly for different load currents to compensate the voltage drop across the PCB track. TP11 should be used if very accurate efficiency measurement of the SPM1006 is needed. Connected to the auxiliary output of an LDO in the module, which is referenced to AGND. A 22µF capacitor is connected on the EVM board. The VAUX pin can only provide 10mA maximum current. The power good signal of the SPM1006 module. A 100kΩ pull-up resistor is connected on the EVM between PWRGD and the auxiliary voltage (VAUX). PWRGD is pulled high if the output voltage is within 95% to 104% of its nominal value. PWRGD becomes low if the output voltage is outside of the above range. Enable (EN) pin of the module. Once the EN pin exceeds the threshold voltage (1.3V) or is left open, the power module starts operation when the input voltage reaches the start-up voltage. When the voltage at the EN pin is pulled below the threshold voltage, the switching converter stops switching and the power module enters a low quiescent current state. If an application requires controlling the EN pin, an open drain or open collector output logic can be used to interface with the pin. Provides a direct connection to the switching node of the SPM1006. This test point can be used to monitor the performance of the module using an oscilloscope. It should appear as a repetitive square pulse waveform during normal operation. The frequency varies with load as described on page 5. The SPM1006EVM demonstrates the full functionality of the SPM1006 power module, through several test point connections and optional component additions. Following is the detailed description of setting up and operation of the EVM board for evaluation of the module. Output Voltage Adjustment The output voltage of the SPM1006 is controlled by a programming resistor (R4) on the SPM1006EVM, which is initially set for 5V (1.5kΩ). To change the output voltage, use a suitable value resistor as indicated in the table below. Note: if the resistor is left open, the output voltage will default to 0.6V. Table 1 - Output Voltage Programming Resistor 0.6V 0.8V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V Open 33.2kΩ 16.5kΩ 11kΩ 7.32kΩ 5.49kΩ 3.48kΩ 2.43kΩ 1.5kΩ The programming resistor can be calculated for any output voltage using equation (1). R4 Version 1.0 11k VOUT / 0.6V 1 November 13, 2015 (1) Page 4 of 11 SPM1006EVM User Guide Switching Frequency The SPM1006 uses instant PWM control and the operational switching frequency depends on the load current. The following figure shows the approximate frequency vs. load curve for the SPM1006 module set at 5V output. Up to about 2.5A the controller operates in discontinuous mode to maintain high efficiency, and the frequency increases with load current. Above 2.5A the controller operates in continuous mode and the frequency is approximately constant at about 750 kHz. 800 700 Frequency (kHz) 600 500 400 300 200 100 0 0 2 4 6 8 Current(A) Fig. 3 Switching Frequency vs Output Current for SPM1006 Start Up Voltage and Under Voltage Lockout (UVLO) By default, the start-up voltage of the SPM1006 is 3.5V and the UVLO is 3.9V. If desired, the start-up voltage of the module can be increased by adding a resistor R1 to the evaluation board. Note: R1 is not populated, but pads are provided on the top side of the EVM. The value can be calculated according to Equation (2). Note that VSTART must always be higher than 3.5V. The maximum operating input voltage for the SPM1006 is 28V. R1 400 (5VSTART 4) kΩ (2) For example, to set the start-up voltage to 8.0V the value of R1 will be 11.1 kΩ. Soft Start and Power Good After application of the input voltage, the output voltage of the SPM1006 will ramp to its final value in approximately 600μs. This soft-start time is set internally and cannot be adjusted. The Power Good (PWRGD) output of the SPM1006 is an open drain signal and is pulled high by resistor R2 in the EVM once the SPM1006 output voltage is within approximately 90% of the set voltage. PWRGD is pulled low when the output drops below 80% or exceeds 120% of the nominal value. Version 1.0 November 13, 2015 Page 5 of 11 SPM1006EVM User Guide This signal can be used to implement sequencing between multiple EVMs. Connecting the PWRGD signal to the EN pin of another EVM will delay the start-up of the second EVM until the first one reaches regulation. This signal can be used to control multiple modules. Sequencing and soft start features can help reduction of initial inrush currents when several modules are in use on the same input bus. Note: The SPM1006 can start in sequence with another SPM1006 or with any other POL having a compatible Power Good output. Schematic of SPM1006EVM Evaluation Board Fig. 4 and Fig. 5 give the schematics of the SPM1006EVM board and the pin out of the SPM1006 power module. The components that are labelled as NC (not connected) in the schematic are not mounted on the EVM by default. The user can select and mount them based on any specific requirements, as explained in this user guide and in the SPM1006 datasheet. Fig. 4 Schematic of the SPM1006EVM Evaluation Board Version 1.0 November 13, 2015 Page 6 of 11 SPM1006EVM User Guide Fig. 5 Pin-out of SPM1006 Integrated Power Module. Version 1.0 November 13, 2015 Page 7 of 11 SPM1006EVM User Guide PCB Layout The following figures show the layout for each of the different PCB layers. Fig. 6 Top Layer PGND Fig. 7 Internal Layer 1 (one layer below top layer) Version 1.0 November 13, 2015 Page 8 of 11 SPM1006EVM User Guide PGND Fig. 8 Internal Layer 2 (two layers below top layer) AGND PVIN VOUT PGND Fig. 9 Bottom Layer Version 1.0 November 13, 2015 Page 9 of 11 SPM1006EVM User Guide Fig. 10 and Fig. 11 show the component placement on the top and bottom layers. Fig. 10 Top Layer Component Placement Fig. 11 Bottom Layer Component Placement Version 1.0 November 13, 2015 Page 10 of 11 SPM1006EVM User Guide Table 2 gives the list of components used in the SPM1006EVM board, as well as the part number. “NC” indicates that components are not connected in the EVM board, but can be added if required. Table 2. List of Components for SPM1006EVM Designator * NC C1 C2, C4, C5 Description Part Number Manufacturer Cap polymer, 25V, 20%, NC, D3L,TC7343-2917 CAP CER 22UF 35V 20% X5R 1206 -55°C ~ 85°C C3216X5R1V226M160AC TDK CAP CER 22UF 35V 20% X5R 1206 -55°C ~ 85°C C3216X5R1V226M160AC TDK CAP CER 0.1UF 35V 10% X5R 0603 -55°C ~ 85°C GMK107BJ104KAHT Murata CAP CER 0.1UF 35V 10% X5R 0603 -55°C ~ 85°C GMK107BJ104KAHT Murata C12 220pF/50V 10% 0603 X7R GRM188R71H221KA01D Murata C13 0.1uF/25V ±10% 0603 X5R GRM188R71E104KA01D Murata 2.2uF/25V ±10% 0603 X5R GRM31CR61E226KE15L Murata 0.1uF/25V ±10% 0603 X5R GRM188R71E104KA01D Murata CAP CER 22UF 6.3V 20% X5R 1206 -55°C ~ 85°C C3216X5R0J226M085AC TDK CAP CER 22UF 6.3V 20% X5R 1206 -55°C ~ 85°C C3216X5R0J226M085AC TDK 100uF/10V 20% 1812 X5R -55°C ~ 85°C C4532X5R1A107M280KC TDK 1% 1/10W 0603 STD STD R4 1.5K 1% 1/10W 0603 See Page 4 for value to set different output voltage STD STD R2 100K 1% 1/10W 0603 STD STD R5 0 1% 1/10W 0603 STD STD Test Point, Red, Thru hole, 1.32mm 2622214 RS Test Point, black, Thru hole, 1.32mm 2622220 RS C3, C8, C9 NC C6, C7 C10, C11 NC C14 NC C15 C16, C17, C18 C19, C20, C21 NC C22 R1, R3 NC SPM1004 TB1, TB2 TP1, TP2, TP5, TP6, TP8, TP9, TP10, TP11, TP12, TP13 TP3, TP4, TP7, TP14, TP15, TP16 Terminal block, 2 pin, 15 A, 5.1 mm, 0.40 inch x 0.35 inch * Indicates components not populated when the evaluation board is delivered. Ordering Information Output Voltage EVM Part Number Adjustable SPM1006EVM Version 1.0 Description Evaluation kit includes the SPM1006 evaluation board, input and output connectors, and USB memory stick with documentation. November 13, 2015 Page 11 of 11