INTERSIL CA5130E

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PO Data Sheet
15MHz, BiMOS Microprocessor
Operational Amplifiers with MOSFET
Input/CMOS Output
CA5130A and CA5130 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. They are designed
and guaranteed to operate in microprocessors or logic
systems that use +5V supplies.
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA5130 Series circuits operate at supply voltages ranging
from 4V to 16V, or ±2V to ±8V when using split supplies. They
can be phase compensated with a single external capacitor,
and have terminals for adjustment of offset voltage for
applications requiring offset null capability. Terminal provisions
are also made to permit strobing of the output stage.
The CA5130A, CA5130 have guaranteed specifications for
5V operation over the full military temperature range of
-55oC to 125oC.
Pinout
CA5130, CA5130A
March 2000
File Number
1923.6
Features
• MOSFET Input Stage
- Very High Zl . . . . . . . . . . . . . 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low ll . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or Both)
Supply Rails
• CA5130A, CA5130 Have Full Military Temperature Range
Guaranteed Specifications for V+ = 5V
• CA5130A, CA5130 Are Guaranteed to Operate Down to
V+ = 4.5V for AOL
• CA5130A, CA5130 Are Guaranteed to Operate at ±7.5V
CA3130A, CA3130 Specifications
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• High Input lmpedance Comparators (Ideal Interface with
Digital CMOS)
• High lnput Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single-Supply
D/A Converter)
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
CA5130 (PDIP)
TOP VIEW
• Peak Detectors
OFFSET NULL
1
8
STROBE
INV. INPUT
2
7
V+
NON-INV. INPUT
3
6
OUTPUT
V-
4
5
OFFSET NULL
• Single Supply Full Wave Precision Rectifiers
• Photo Diode Sensor Amplifiers
+
• 5V Logic Systems
• Microprocessor Interface
Part Number Information
PART NUMBER
(BRAND)
1
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CA5130AE
-55 to 125
8 Ld PDIP
E8.3
CA5130E
-55 to 125
8 Ld PDIP
E8.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
CA5130, CA5130A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
120
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
TA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
CA5130
CA5130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
2
10
-
1.5
4
mV
Input Offset Current
IIO
VO = 2.5V
-
0.1
10
-
0.1
5
pA
II
VO = 2.5V
-
2
15
-
2
10
pA
VCM = 0V to 1V
70
85
-
75
87
-
dB
VCM = 0V to 2.5V
60
69
-
60
69
-
dB
Input Current
Common Mode Rejection Ratio
CMRR
Input Common Mode Voltage
Range
VICR+
2.5
2.8
-
2.5
2.8
-
V
VICR-
-
-0.5
0
-
-0.5
0
V
Power Supply Rejection Ratio
PSRR
∆+ = 1V; ∆- = 1V
55
73
-
60
75
-
dB
AOL
VO = 0.1V to 4.1V
RL = ∞
95
105
-
100
105
-
dB
VO = 0.1V to 3.6V
RL = 10kΩ
85
95
-
90
97
-
dB
ISOURCE
VO = 0V
1.0
2.6
4.0
1.0
3.1
4.0
mA
Sink Current
ISINK
VO = 5V
1.0
1.7
4.0
1.0
1.4
4.0
mA
Output Voltage
VOUT
RL = ∞
4.99
5
-
4.99
5
-
V
-
0
0.01
-
0
0.01
V
4.4
4.7
-
4.4
4.7
-
V
-
0
0.01
-
0
0.01
V
2.5
3.5
-
2.5
3.5
-
V
-
0
0.01
-
0
0.01
V
VO = 0V
-
50
100
-
50
100
µA
VO = 2.5V
-
260
400
-
260
400
µA
Large Signal Voltage Gain
(Note 3)
Source Current
VOM+
VOMVOM+
RL = 10kΩ
VOMVOM+
RL = 2kΩ
VOMSupply Current
ISUPPLY
NOTE:
3. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
2
CA5130, CA5130A
TA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
CA5130
CA5130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
3
15
-
2
10
mV
Input Offset Current
IIO
VO = 2.5V
-
0.1
10
-
0.1
5
nA
II
VO = 2.5V
-
2
15
-
2
10
nA
VCM = 0V to 1V
60
80
-
60
80
-
dB
VCM = 0V to 2.5V
50
80
-
55
80
-
dB
Input Current
Common Mode Rejection Ratio
CMRR
Input Common Mode Voltage
Range
VICR+
2.5
2.8
-
2.5
2.8
-
V
VICR-
-
-0.5
0
-
-0.5
0
V
Power Supply Rejection Ratio
PSRR
∆+ = 1V; ∆- = 1V
40
66
-
45
70
-
dB
AOL
VO = 0.1V to 4.1V
RL = ∞
90
98
-
94
98
-
dB
VO = 0.1V to 3.6V
RL = 10kΩ
75
85
-
80
88
-
dB
ISOURCE
VO = 0V
0.6
-
5.0
0.6
2.2
5.0
mA
Sink Current
ISINK
VO = 5V
0.6
-
5.0
0.6
1.15
5.0
mA
Output Voltage
VOUT
RL = ∞
4.99
5
-
4.99
5
-
V
-
0
0.01
-
0
0.01
V
4.0
4.6
-
4.0
4.6
-
V
-
0
0.01
-
0
0.01
V
2.0
3.0
-
2.0
3.0
-
V
-
0
0.01
-
0
0.01
V
VO = 0V
-
80
220
-
80
220
µA
VO = 2.5V
-
300
500
-
300
500
µA
Large Signal Voltage Gain
(Note 4)
Source Current
VOM+
VOMVOM+
RL = 10kΩ
VOMVOM+
RL = 2kΩ
VOMSupply Current
ISUPPLY
NOTE:
4. For V+ = 4.5V and V- = GND; VOUT = 0.5V to 3.2V at RL = 10kΩ.
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
CA5130
CA5130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
V± = ±7.5V
-
8
15
-
2
5
mV
Input Offset Current
IIO
V± = ±7.5V
-
0.5
30
-
0.5
20
pA
II
V± = ±7.5V
-
5
50
-
5
30
pA
CMRR
70
90
-
80
90
-
dB
Input Common Mode Voltage
Range
VICR
10
-0.5 to
12
0
10
-0.5 to
12
0
V
Power Supply Rejection Ratio
PSRR
-
32
320
-
32
150
µV/V
50
320
-
50
320
-
kV/V
94
110
-
94
110
-
dB
Input Current
Common Mode Rejection Ratio
Large Signal Voltage Gain
AOL
3
∆VIO/∆V±
V± = ±7.5V
VO = 10VP-P
RL = 2kΩ
CA5130, CA5130A
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued)
Electrical Specifications
PARAMETER
TEST
CONDITIONS
SYMBOL
CA5130
CA5130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Maximum Output Current
Source
IOM+
VO = 0V
12
22
45
12
22
45
mA
Sink
IOM-
VO = 15V
12
20
45
12
20
45
mA
VO = 7.5V, RL = ∞
-
10
15
-
10
15
mA
VO = 0V, RL = ∞
-
2
3
-
2
3
mA
14.99
15
-
14.99
15
-
V
-
0
0.01
-
0
0.01
V
12
13.3
-
12
13.3
-
V
-
0.002
0.01
-
0.002
0.01
V
-
10
-
-
10
-
µV/oC
Supply Current
ISUPPLY
Maximum Output Voltage
VOUT
RL = ∞
VOM+
VOMVOM+
RL = 2kΩ
VOM∆VIO/∆T
Input Offset Voltage
Temperature Drift
Typical Values Intended Only for Design Guidance, At TA = 25oC, VSUPPLY = ±7.5V
Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
Input Offset Voltage Adjustment Range
TEST CONDITIONS
10kΩ Across Terminals 4 and 5 or 4 and 1
CA5130
CA5130A
TYP
TYP
UNITS
±22
±22
mV
1.5
1.5
TΩ
Input Resistance
RI
Input Capacitance
CI
f = 1MHz
4.3
4.3
pF
Equivalent Input Noise Voltage
eN
BW = 0.2MHz, RS = 1MΩ (Note 5)
23
23
µV
Open Loop Crossover Frequency
For Unity Gain Stability ≥47pF Required
fT
CC = 0
15
15
MHz
CC = 47pF
4
4
MHz
Slew Rate
SR
Open Loop
CC = 0
30
30
V/µs
Closed Loop
CC = 56pF
10
10
V/µs
0.09
0.09
µs
10
10
%
1.2
1.2
µs
Transient Response
Rise Time
tr
Overshoot
OS
Settling Time (To <0.1%, VIN = 4VP-P)
tS
CC = 56pF, CL = 25pF, RL = 2kΩ
(Voltage Follower)
CC = 56pF, CL = 25pF, RL = 2kΩ
(Voltage Follower)
NOTE:
5. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
4
CA5130, CA5130A
Schematic Diagram
CURRENT SOURCE FOR
Q6 AND Q7
BIAS CIRCUIT
Q1
“CURRENT SOURCE
LOAD” FOR Q11
Q2
7
V+
Q3
D1
Z1
8.3V
D2
R1
D4
Q4
Q5
D3
40kΩ R
2
5kΩ
SECOND
STAGE
INPUT
STAGE
D5
NON-INV.
INPUT
D6
(NOTE 6) D7
D8
OUTPUT
STAGE
3
+
INV. INPUT
2
Q6
Q8
OUTPUT
Q7
-
6
R3
1kΩ
R4
1kΩ
Q10
Q9
R5
1kΩ
5
Q11
Q12
R6
1kΩ
1
OFFSET NULL
COMPENSATION
8
STROBING
4
V-
NOTE:
6. Diodes D5 through D8 provide gate oxide protection for MOSFET Input Stage.
Block Diagram
V+
CA5130
7
200µA
1.35mA
200µA
NOTES:
8mA (NOTE 7)
7. Total supply voltage (for indicated voltage gains)
= 15V with input terminals biased so that
Terminal 6 potential is +7.5V above Terminal 4.
0mA (NOTE 8)
BIAS CKT.
+
3
INPUT
AV ≈
6000X
AV ≈ 5X
AV ≈
30X
OUTPUT
6
2
-
V4
CC
5
1
OFFSET
NULL
8
COMPENSATION
(WHEN REQUIRED)
5
STROBE
8. Total supply voltage (for indicated voltage gains)
= 15V with output terminal driven to either
supply rail.
CA5130, CA5130A
Application Information
Circuit Description
The input terminals shown in the block diagram of the CA5130
Series CMOS Operational Amplifiers may be operated down to
0.5V below the negative supply rail, and the output can be
swung very close to either supply rail in many applications.
Consequently, the CA5130 Series circuits are ideal for single
supply operation. Three Class A amplifier stages, having the
individual gain capability and current consumption shown in the
Block Diagram, provide the total gain of the CA5130. A biasing
circuit provides two potentials for common use in the first and
second stages. Terminal 8 can be used both for phase
compensation and to strobe the output stage into quiescence.
When Terminal 8 is tied to the negative supply rail (Terminal 4)
by mechanical or electrical means, the output potential at
Terminal 6 essentially rises to the positive supply rail potential
at Terminal 7. This condition of essentially zero current drain in
the output stage under the strobed “OFF” condition can only be
achieved when the ohmic load resistance presented to the
amplifier is very high (e.g., when the amplifier output is used to
drive CMOS digital circuits in comparator applications).
Input Stages
The circuit of the CA5130 is shown in the Schematic Diagram.
It consists of a differential input stage using PMOS field-effect
transistors (Q6, Q7) working into a mirror pair of bipolar
transistors (Q9, Q10) functioning as load resistors together
with resistors R3 through R6. The mirror pair transistors also
function as a differential-to-single-ended converter to provide
base drive to the second stage bipolar transistor (Q11). Offset
nulling, when desired, can be effected by connecting a
100,000Ω potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascode connected
PMOS transistors Q2, Q4 are the constant current source for
the input stage. The biasing circuit for the constant current
source is subsequently described. The small diodes D5
through D8 provide gate oxide protection against high voltage
transients, e.g., including static electricity during handling for
Q6 and Q7.
Second Stage
Most of the voltage gain in the CA5130 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascode connected load resistance provided by
PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is subsequently described.
Miller-Effect compensation (roll-off) is accomplished by
simply connecting a small capacitor between Terminals 1
and 8. A 47pF capacitor provides sufficient compensation for
stable unity gain operation in most applications.
Bias Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R2
and zener diode Z1 serve to establish a voltage of 8.3V
across the series connected circuit, consisting of resistor R1,
diodes D1 through D4, and PMOS transistor Q1. A tap at the
6
junction of resistor R1 and diode D4 provides a gate bias
potential of about 4.5V for PMOS transistors Q4 and Q5 with
respect to Terminal 7. A potential of about 2.2V is developed
across diode connected PMOS transistor Q1 with respect to
Terminal 7 to provide gate bias for PMOS transistors Q2 and
Q3. It should be noted that Q1 is “mirror connected” to both
Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be
identical, the approximately 200µA current in Q1 establishes
a similar current in Q2 and Q3 as constant current sources
for both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes nonconductive and the potential, developed
across series connected R1, D1-D4, and Q1, varies directly with
variations in supply voltage. Consequently, the gate bias for Q4,
Q5 and Q2, Q3 varies in accordance with supply voltage
variations. This variation results in deterioration of the power
supply rejection ratio (PSRR) at total supply voltages below
8.3V. Operation at total supply voltages below about 4.5V
results in seriously degraded performance.
Output Stage
The output stage consists of a drain loaded inverting amplifier
using CMOS transistors operating in the Class A mode. When
operating into very high resistance load, the output can be
swung within mV of either supply rail. Because the output stage
is a drain loaded amplifier, its gain is dependent upon the load
impedance. The transfer characteristics of the output stage for
a load returned to the negative supply rail are shown in Figure
15. Typical op amp loads are readily driven by the output stage.
Because large signal excursions are nonlinear, requiring
feedback for good waveform reproduction, transient delays may
be encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA5130 Series Op Amps is typically 5pA at
TA = 25oC when Terminals 2 and 3 are at a common mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 24 contains data showing the variation of input current
as a function of common mode input voltage at TA = 25oC. This
data shows that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA5130 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
CA5130, CA5130A
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000Ω
potentiometer connected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Terminal 4. A fine offset
null adjustment usually can be effected with the slider arm
positioned in the midpoint of the potentiometer's total range.
V+
7
3
CA5130
+
Q8
6
Input Current Variation with Temperature
The input current of the CA5130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate protective diodes in the input
circuit. As with any semiconductor junction device, including
op amps with a junction FET input stage, the leakage current
approximately doubles for every 10oC increase in
temperature. Figure 25 provides data on the typical variation
of input bias current as a function of temperature in the
CA5130.
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA5130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input
current variations.
Input Offset Voltage (VIO) Variation with DC Bias vs
Device Operating Life
It is well known that the characteristics of a MOS/FET device
can change slightly when a DC gate source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA5130 should be alert to the possible impacts
of this effect if the application of the device involves extended
operation at high temperatures with a significant differential
DC bias voltage applied across Terminals 2 and 3. Figure 26
shows typical data pertinent to shifts in offset voltage
encountered with CA5130 devices (metal can package)
during life testing. At lower temperatures (metal can and
plastic packages), for example at 85oC, this change in voltage
is considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2V differential voltage
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
Power-Supply Considerations
Because the CA5130 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA5130 connected for both dual and single supply operation.
7
2
Q12
-
RL
4
8
V-
FIGURE 1A. DUAL POWER SUPPLY OPERATION
V+
7
3
CA5130
+
Q8
6
2
Q12
-
RL
4
8
FIGURE 1B. SINGLE POWER SUPPLY OPERATION
FIGURE 1. CA5130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
Dual supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single supply operation: Initially, let it be assumed that the
value of RL is very high (or disconnected), and that the input
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops across
Q8 and Q12 are of equal magnitude. Figure 16 shows typical
quiescent supply current vs supply voltage for the CA5130
operated under these conditions. Since the output stage is
operating as a Class A amplifier, the supply current will remain
constant under dynamic operating conditions as long as the
transistors are operated in the linear portion of their voltage
transfer characteristics (see Figure 15). If either Q8 or Q12 are
swung out of their linear regions toward cutoff (a nonlinear
region), there will be a corresponding reduction in supply
current. In the extreme case, e.g., with Terminal 8 swung down
to ground potential (or tied to ground), NMOS transistor Q12 is
completely cut off and the supply current to series connected
CA5130, CA5130A
transistors Q8, Q12 goes essentially to zero. The two preceding
stages in the CA5130, however, continue to draw modest
supply current (see the lower curve in Figure 16) even though
the output stage is strobed off. Figure 1A shows a dual supply
arrangement for the output stage that can also be strobed off,
assuming RL = ∞, by pulling the potential of Terminal 8 down to
that of Terminal 4.
Let it now be assumed that a load resistance of nominal value
(e.g., 2kΩ) is connected between Terminal 6 and ground in
the circuit of Figure 1B. Let it further be assumed that the
input terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8
must now supply quiescent current to both RL and transistor
Q12, it should be apparent that under these conditions the
supply current must increase as an inverse function of the RL
magnitude. Figure 22 shows the voltage drop across PMOS
transistor Q8 as a function of load current at several supply
voltages. Figure 15 shows the voltage transfer characteristics
of the output stage for several values of load resistance.
Wideband Noise
From the standpoint of low noise performance considerations,
the use of the CA5130 is most advantageous in applications
where the source resistance of the input signal is on the order
of 1MΩ or more. In this case, the total input referred noise
voltage is typically only 23µV when the test circuit amplifier of
Figure 2 is operated at a total supply voltage of 15V. This
value of total input referred noise remains essentially
constant, even though the value of source resistance is raised
by an order of magnitude. This characteristic is due to the fact
that reactance of the input capacitance becomes a significant
factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1MΩ, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.
+7.5V
0.01µF
Rs
3
7
+
1MΩ
NOISE
VOLTAGE
OUTPUT
6
2
4
8
30.1kΩ
1
0.01
µF
47pF -7.5V
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)
1kΩ
FIGURE 2. CA5130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
8
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA5130, are particularly suited to service as voltage
followers. Figure 3 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA5130 in a split supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 4, together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 4A with input
signal ramping. The waveforms in Figure 4B show that the
follower does not lose its input-to-output phase sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 4B
also shows the manner in which the CMOS output stage
permits the output signal to swing down to the negative supply
rail potential (i.e., ground in the case shown). The digital-toanalog converter (DAC) circuit, described in the following
section, illustrates the practical use of the CA5130 in a single
supply voltage follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
(see Note) is shown in Figure 5. This system combines the
concepts of multiple switch CMOS lCs, a low cost ladder
network of discrete metal-oxide film resistors, a CA5130 op
amp connected as a follower, and an inexpensive monolithic
regulator in a simple single power supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 5.
NOTE: “Digital-to-Analog Conversion Using the Intersil CD4007A
CMOS lC”, Application Note AN6080.
CA5130, CA5130A
+7.5V
0.01µF
7
3
+
2
-
10kΩ
6
4
2kΩ
8
1
0.01µF
-7.5V
25pF
CC = 56pF
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs
0.1µF
Top Trace: Output
Bottom Trace: Input
FIGURE 3A. SMALL SIGNAL RESPONSE (50mV/DIV.,
200ns/DIV.)
Top Trace: Output Signal = 2V/Div., 5µs/Div.
Center Trace: Difference Signal = 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal = 2V/Div., 5µs/Div.
FIGURE 3B. INPUT OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 3. CA5130 SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
9
CA5130, CA5130A
+15V
0.01µF
7
3
+
2
-
10kΩ
6
4
1
8
56pF
5
100kΩ
OFFSET
ADJUST
2kΩ
0.1µF
0V
0V
0V
2V/Div., 500µs/Div.
FIGURE 4A. OUTPUT WAVEFORM WITH INPUT SIGNAL
RAMPING
Top Trace: Output = 5V/Div., 200µs/Div.
Bottom Trace: Input = 5V/Div., 200µs/Div.
FIGURE 4B. OUTPUT WAVEFORM WITH GROUND REFERENCE
SINE WAVE INPUT
FIGURE 4. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SINGLE SUPPLY
D/A CONVERTER; SEE FIGURE 9 IN AN6080)
The circuit uses an R/2R voltage ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single pole double throw switch to
terminate an arm of the R/2R network at either the positive or
negative power supply terminal. The resistor ladder is an
assembly of one percent tolerance metal oxide film resistors.
The five arms requiring the highest accuracy are assembled
with series and parallel combinations of 806,000Ω resistors
from the same manufacturing lot.
A single 15V supply provides a positive bus for the CA5130
follower amplifier and feeds the CA3085 voltage regulator. A
“scale adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line
voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
10
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single Supply, Absolute Value, Ideal Full Wave
Rectifier
The absolute value circuit using the CA5130 is shown in Figure
6. During positive excursions, the input signal is fed through the
feedback network directly to the output. Simultaneously, the
positive excursion of the input signal also drives the output
terminal (No. 6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects the
amplifier from the signal path. During a negative going
excursion of the input signal, the CA5130 functions as a normal
inverting amplifier with a gain equal to -R2/R1. When the
equality of the two equations shown in Figure 6 is satisfied, the
full wave output is symmetrical.
CA5130, CA5130A
Peak Detectors
Function Generator
Peak detector circuits are easily implemented with the
CA5130, as illustrated in Figure 7 for both the peak positive
and the peak negative circuit. It should be noted that with
large signal inputs, the bandwidth of the peak negative
circuit is much less than that of the peak positive circuit. The
second stage of the CA5130 limits the bandwidth in this
case. Negative going output signal excursion requires a
positive going signal excursion at the collector of transistor
Q11, which is loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the other hand, during
a negative going signal excursion at the collector of Q11, the
transistor functions in active “pull down” mode so that the
intrinsic capacitance can be discharged more expeditiously.
Figure 11 contains a schematic diagram of a function
generator using the CA5130 in the integrator and threshold
detector functions. This circuit generates a triangular or
square wave output that can be swept over a 1,000,000:1
range (0.1Hz to 100kHz) by means of a single control, R1. A
voltage control input is also available for remote sweep
control.
Error Amplifier In Regulated Power Supplies
The CA5130 is an ideal choice for error amplifier service in
regulated power supplies since it can function as an error
amplifier when the regulated output voltage is required to
approach 0V. Figure 8 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
13V. Q3 and Q4 in IC2 (a CA3066 transistor array lC)
function as zeners to provide supply voltage for the CA5130
comparator (lC1). Q1, Q2, and Q5 in lC2 are configured as a
low impedance, temperature compensated source of
adjustable reference voltage for the error amplifier.
Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086
transistor array lC) are connected in parallel as the series
pass element. Transistor Q5 in lC3 functions as a current
limiting device by diverting base drive from the series pass
transistors, in accordance with the adjustment of resistor R2.
Figure 9 contains the schematic diagram of a regulated
power supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC1) and circuitry
associated with lC2 function as previously described,
although the output of lC1 is boosted by a discrete transistor
(Q4) to provide adequate base drive for the Darlington
connected series pass transistors Q1, Q2. Transistor Q3
functions in the previously described current limiting circuit.
Multivibrators
The exceptionally high input resistance presented by the
CA5130 is an attractive feature for multivibrator circuit
design because it permits the use of timing circuits with high
R/C ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 10. Resistors R1
and R2 are used to bias the CA5130 to the midpoint of the
supply voltage and R3 is the feedback resistor. The pulse
repetition rate is selected by positioning S1 to the desired
position and the rate remains essentially constant when the
resistors which determine “on period” and “off period” are
adjusted.
11
The heart of the frequency determining system is an
operational transconductance amplifier (OTA) (see Note 9),
lC1, operated as a voltage controlled current source. The
output, IO, is a current applied directly to the integrating
capacitor, C1, in the feedback loop of the integrator lC2,
using a CA5130, to provide the triangular wave output.
Potentiometer R2 is used to adjust the circuit for slope
symmetry of positive going and negative going signal
excursions.
Another CA5130, lC3, is used as a controlled switch to set
the excursion limits of the triangular output from the
integrator circuit. Capacitor C2 is a “peaking adjustment” to
optimize the high frequency square wave performance of the
circuit.
Potentiometer R3 is adjustable to perfect the “amplitude
symmetry” of the square wave output signals. Output from
the threshold detector is fed back via resistor R4 to the input
of lC1 so as to toggle the current source from plus to minus
in generating the linear triangular wave.
Operation with Output Stage Power-Booster
The current sourcing and sinking capability of the CA5130
output stage is easily supplemented to provide power boost
capability. In the circuit of Figure 12, three CMOS transistor
pairs in a single CA3600E (see Note 10) lC array are shown
parallel connected with the output stage in the CA5130. In
the Class A mode of CA3600E shown, a typical device
consumes 20mA of supply current at 15V operation. This
arrangement boosts the current handling capability of the
CA5130 output stage by about 2.5X.
The amplifier circuit in Figure 12 employs feedback to
establish a closed-loop gain of 48dB. The typical large signal
bandwidth (-3dB) is 50kHz.
NOTES:
9. See File No. 475 and AN6668.
10. See File No. 619 for technical information.
CA5130, CA5130A
10V LOGIC INPUTS
+10.010V
LSB
9
8
7
6
3
10
14
11
6
5
4
3
2
MSB
1
6
3
10
6
3
10
BIT
1
2
3
4
5
6-9
2
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
CD4007A
“SWITCHES”
9
13
1
13
1
8
5
12
7
8
5
4
806K
1%
402K
1%
200K
1%
100K
1%
806K
1%
806K
1%
+15V
8
5
NOTE: All Resistances are In Ohms.
12
(2)
806K
1%
806K
1%
750K
1%
(4)
806K
1%
(8)
806K
1%
PARALLELED
RESISTORS
10K
7
LOAD
22.1K
1%
6
7
0.001µF
4
5
2
1
8
REGULATED
VOLTAGE
1K
ADJ.
3.83K
1%
4
VOLTAGE
FOLLOWER
CA5130
6
8
3
3
+
OUTPUT
+10.010V
CA3085
-
1
62
1
2µF
25V
1%
806K
1%
13
+15V
VOLTAGE
REGULATOR
2
+
12
806K
REQUIRED
RATIO-MATCH
STANDARD
±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS
100K
OFFSET
NULL 2K
56pF
0.1µF
FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA5130
R2
2kΩ
+15V
0.01
µF
R1
7
-
2
4kΩ
CA5130
3
+
6
4
0V
1N914
5.1kΩ
5
1
8
R3
100kΩ
OFFSET
ADJUST
20pF
PEAK
ADJUST
2kΩ
0V
R2
R3
Gain = ------ = X = --------------------------------R1
R1 + R2 + R3
X + X2
R 3 = R 1  ----------------
 1–X 
R2
2kΩ
ForX = 0.5: ---------- = -----R1
4kΩ
Top Trace: Output Signal = 2V/Div.
Bottom Trace: Input Signal = 10V/Div.
Time base on both traces = 0.2ms/Div.
0.75
R 3 = 4kΩ  ---------- = 6kΩ
 0.5 
20VP-P Input: BW (-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW (-3dB) = 130kHz, DC Output (Avg) = 160mV
FIGURE 6. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
12
CA5130, CA5130A
6VP-P INPUT;
BW (-3dB) = 1.3MHz
6VP-P INPUT;
BW (-3dB) = 360kHz
+7.5V
0.3 VP-P INPUT;
0.3 VP-P INPUT;
0.01µF
BW (-3dB) = 240kHz
+
CA5130
2
-
10kΩ
0.01µF
BW (-3dB) = 320kHz
7
3
+7.5V
+DC
OUTPUT
7
3
+
CA5130
2
-
10kΩ
6
1N914
4
6
1N914
4
+
100
kΩ
-DC
OUTPUT
100
kΩ
5µF
-
0.01µF
2kΩ
2kΩ
FIGURE 7A. PEAK POSITIVE DETECTOR CIRCUIT
-7.5V
FIGURE 7B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 7. PEAK-DETECTOR CIRCUITS
CURRENT
LIMIT
ADJ
3Ω
+
R2
1kΩ
IC3
1kΩ
Q5
CA3086
10
7
Q4
12
Q1
3
Q3
9
8
Q2
6
2
1
13
14
4
5
+
390Ω
56pF
5µF
25V
2.2kΩ
+
IC2
+20V
INPUT
OUTPUT
0 TO 13V
AT
40mA
20kΩ
1kΩ
0.01µF
-
CA3086 10
11 1, 2
Q4
9
1
7
Q1
6
3
Q3
6
Q2
4
12
62kΩ
CA5130
+
IC1
Q5
ERROR
AMPLIFIER
+
-
8
25µF
6, 5
8, 7
3
30kΩ
4
14
13
2
50kΩ
R1
100kΩ
VOLTAGE
ADJUST
0.01µF
-
-
NOTES:
11. Regulation (no load to full load): <0.01%.
12. Input Regulation: 0.02%/V.
13. Hum and noise output: <25µV up to 100kHz.
FIGURE 8. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
13
5µF
0.01µF
-7.5V
11
+
CA5130, CA5130A
2N3055
1Ω
Q2
+
+
10kΩ
2N2102
1kΩ
CURRENT
LIMIT
ADJUST
Q1
4.3kΩ
1W
Q3
3.3kΩ
1W
2N5294
+
+55V
INPUT
43kΩ
1000pF
100µF
-
2.2kΩ
1
+
5µF
IC2
CA3086
8
-
2N2102
Q4
+
9
8, 7
3
5
6
Q1
Q2
Q3
Q5
14
12
13
Q4
ERROR
AMPLIFIER
7
10, 11 1, 2
3
-
100µF
OUTPUT:
0.1 TO 50V
AT 1A
10kΩ
CA5130
IC1
+
2
4
8.2kΩ
4
6
50kΩ
1kΩ
VOLTAGE
ADJUST
62kΩ
-
-
NOTES:
14. Regulation (no load to full load): <0.005%.
15. Input Regulation: 0.01%/V.
16. Hum and noise output: <250µVRMS up to 100kHz.
FIGURE 9. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
+15V
0.01µF
R1
100kΩ
ON-PERIOD
ADJUST
1MΩ
OFF-PERIOD
ADJUST
1MΩ
2kΩ
FREQUENCY RANGE:
POSITION OF S1
0.001µF
0.01µF
0.1µF
1µF
2kΩ
R3
100kΩ
PULSE PERIOD
4µs to 1ms
40µs to 10ms
0.4ms to 100ms
4ms to 1s
7
3
+
6
CA5130
S1
1µF
R2
100kΩ
2
-
OUTPUT
4
2kΩ
0.1µF
0.01µF
0.001µF
FIGURE 10. PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS FOR INDEPENDENT CONTROL OF “ON” AND “OFF”
PERIODS
14
CA5130, CA5130A
R4
INTEGRATOR
C1
270kΩ
VOLTAGE-CONTROLLED
CURRENT SOURCE
+7.5V
7
IC1
3
3kΩ
IC2
IO
+
-
2
4
+7.5V
R2
100kΩ
-7.5V
5
10MΩ
3
IC3 7
C2
CA5130
+
39kΩ
CA5130
8
4
5
-7.5V
VOLTAGE
CONTROLLED
INPUT
1
R3
100kΩ
56pF
FREQUENCY
ADJUST
(100kHz MAX)
R1
10kΩ
6
-
2
1
+7.5V
SLOPE
SYMMETRY 10kΩ
ADJUST
+
3
6
4
-7.5V
150kΩ
+7.5V
7
-
2
6
3kΩ
+7.5V
CA3080A (NOTE)
THRESHOLD
DETECTOR
HIGH - FREQ.
ADJUST
3 - 30pF
100pF
AMPLITUDE
SYMMETRY
ADJUST
-7.5V
NOTE: See File Number 475 and AN6668 for technical information.
FIGURE 11. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
+15V
0.01µF
14
1MΩ
CA3600E
(NOTE)
1µF
QP2
11
QP3
7
750kΩ
3
+
CA5130
2kΩ
INPUT
QP1
2
2
6
13
1
3
10
-
1µF
500µF
8
6
12
4
RL = 100Ω
(PO = 150mW
AT THD = 10%)
8
AV(CL) = 48dB
QN1
LARGE SIGNAL
BW (-3dB) = 50kHz
7
5
QN2
4
QN3
9
510kΩ
NOTE: Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the
CA5130. See File Number 619.
FIGURE 12. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA5130
15
CA5130, CA5130A
Typical Performance Curves
AOL
SUPPLY VOLTAGE: V+ = 15V;
V- = 0V; TA = 25oC
φ OL
3
40
-100
2
2
60
4
3
1
80
150
-200
1
-300
4
20
0
101
102
103
104
105
106
FREQUENCY (Hz)
1: CL = 9pF, CC = 0pF, RL = ∞
2: CL = 30pF, CC = 15pF, RL = 2kΩ
107
LOAD RESISTANCE = 2kΩ
OPEN LOOP VOLTAGE GAIN (dB)
100
OPEN LOOP PHASE (DEGREES)
OPEN LOOP VOLTAGE GAIN (dB)
120
108
130
120
110
100
90
80
-100
15
QUIESCENT SUPPLY CURRENT (mA)
SUPPLY VOLTAGE: V+ = 15V, V- = 0V
TA = 25oC
RL = 5kΩ
12.5
2kΩ
1kΩ
10.0
0
50
TEMPERATURE (oC)
500Ω
7.5
5.0
2.5
100
FIGURE 14. OPEN LOOP GAIN vs TEMPERATURE
17.5
15.0
-50
3: CL = 30pF, CC = 47pF, RL = 2kΩ
4: CL = 30pF, CC = 150pF, RL = 2kΩ
FIGURE 13. OPEN LOOP VOLTAGE GAIN AND PHASE SHIFT vs
FREQUENCY
OUTPUT VOLTAGE (V)
140
LOAD RESISTANCE = ∞
TA = 25oC, V- = 0V
12.5
OUTPUT VOLTAGE
BALANCED = V+/2
10
7.5
5
OUTPUT VOLTAGE
HIGH = V+ OR LOW = V-
2.5
0
0
2.5
5
7.5
10
12.5
15 17.5 20
GATE VOLTAGE, TERMINALS 4 AND 8 (V)
6
22.5
FIGURE 15. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
18
FIGURE 16. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
14
600
OUTPUT VOLTAGE = V+/2
V- = 0V
12
V+ = 5V, V- = 0V
TA = -55oC
10
25oC
8
125oC
6
4
2
525
SUPPLY CURRENT (µA)
QUIESCENT SUPPLY CURRENT (mA)
8
10
12
14
16
TOTAL SUPPLY VOLTAGE (V)
125oC
450
375
25oC
300
-55oC
225
150
75
0
0
2
4
6
8
10
12
14
TOTAL SUPPLY VOLTAGE (V)
16
FIGURE 17. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
16
0
0
0.5
1
1.5
2
2.5
3
3.5
OUTPUT VOLTAGE (V)
4
4.5
FIGURE 18. SUPPLY CURRENT vs OUTPUT VOLTAGE
5
CA5130, CA5130A
Typical Performance Curves
(Continued)
8
9
V+ = 5V, V- = 0V
7
8
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE SWING (V)
V+ = 5V, V- = 0V
6
5
4
3
-55oC
2
125oC
25oC
1
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
LOAD RESISTANCE (kΩ)
9
10
0
0.1 0.2
11
FIGURE 19. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
50
V+ = 5V, V- = 0V
VOLTAGE DROP ACROSS PMOS
OUTPUT TRANSISTOR (Q8) (V)
OUTPUT CURRENT (mA)
6
5
4
SINK
3
2
SOURCE
1
-40
-20
0
20
40
60
80
100
120
10
V- = 0V
TA = 25oC
140
0.01
0.01
0.1
1
10
100
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT
10.0
50
V+ = 15V
V+ = 10V
V+ = 5V
INPUT VOLTAGE (V)
VOLTAGE DROP ACROSS PMOS
OUTPUT TRANSISTOR (Q12) (V)
V+ = 15V
V+ = 10V
V+ = 5V
MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 21. OUTPUT CURRENT vs TEMPERATURE
10
1000
0.1
TEMPERATURE (oC)
V- = 0V
TA = 25oC
200
1
0.001
0.001
0
-60
2 4 68
20 40 80
LOAD RESISTANCE (kΩ)
FIGURE 20. OUTPUT SWING vs LOAD RESISTANCE
8
7
0.6 1
1
0.1
TA = 25oC
7.5
V+
15V TO 5V
7
5.0
2
6
3
2.5
0.01
CA5130
PA
VIN
8
4
0V TO -10V
V-
0.001
0.001
0
0.01
0.1
1
10
MAGNITUDE OF LOAD CURRENT (mA)
100
FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q12) vs LOAD CURRENT
17
-1
0
1
2
3
4
5
6
INPUT CURRENT (pA)
7
FIGURE 24. INPUT CURRENT vs COMMON MODE VOLTAGE
CA5130, CA5130A
Typical Performance Curves
7
VS = ±7.5V
OFFSET VOLTAGE SHIFT (mV)
4000
(Continued)
INPUT CURRENT (pA)
1000
100
10
1
-80
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
6
5
TA = 125oC FOR
METAL CAN PACKAGE
4
3
2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMS. 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
1
0
-60
-40
-20
0
20 40 60 80
TEMPERATURE (oC)
100 120 140
FIGURE 25. INPUT CURRENT vs TEMPERATURE
18
0
500
1000
1500
2000 2500 3000
TIME (HOURS)
3500
4000
FIGURE 26. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
CA5130, CA5130A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
A1
D1
e
B1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
8
0.355
10.16
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
10.92
7
3.81
4
8
9
Rev. 0 12/93
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