S E M I C O N D U C T O R CA3240, CA3240A Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output November 1996 Features Description • Dual Version of CA3140 The CA3240A and CA3240 are dual versions of the popular CA3140 series integrated circuit operational amplifiers. They combine the advantages of MOS and bipolar transistors on the same monolithic chip. The gate-protected MOSFET (PMOS) input transistors provide high input impedance and a wide common-mode input voltage range (typically to 0.5V below the negative supply rail). The bipolar output transistors allow a wide output voltage swing and provide a high output current capability. • Internally Compensated • MOSFET Input Stage - Very High Input Impedance (ZIN) 1.5TΩ (Typ) - Very Low Input Current (II) 10pA Typ. at ±15V - Wide Common-Mode Input Voltage Range (VICR): Can Be Swung 0.5V Below Negative Supply Voltage Rail • Directly Replaces Industry Type 741 in Most Applications Applications • Ground Referenced Single Amplifiers in Automobile and Portable Instrumentation The CA3240A and CA3240 are compatible with the industry standard 1458 operational amplifiers in similar packages.The offset null feature is available only when these types are supplied in the 14 lead PDIP package (E1 suffix). Ordering Information • Sample and Hold Amplifiers PART NUMBER • Long Duration Timers/Multivibrators (MicrosecondsMinutes-Hours) • Photocurrent Instrumentation • Intrusion Alarm System • Active Filters • Comparators • Function Generators • Instrumentation Amplifiers • Power Supplies Pinouts TEMP. RANGE (oC) PKG. NO. PACKAGE CA3240AE -40 to 85 8 Ld PDIP E8.3 CA3240AE1 -40 to 85 14 Ld PDIP E14.3 CA3240E -40 to 85 8 Ld PDIP E8.3 CA3240E1 -40 to 85 14 Ld PDIP E14.3 Functional Diagram CA3240, CA3240A, (PDIP) TOP VIEW OUTPUT (A) INV. INPUT (A) NON-INV. INPUT (A) 1 8 V+ 2 V- 4 7 OUTPUT INV. 6 INPUT (B) 5 NON-INV. INPUT (B) 3 2mA 4mA V+ BIAS CIRCUIT CURRENT SOURCES AND REGULATOR 200µA 1.6mA 200µA 2µA 2mA + CA3240, CA3240A, (PDIP) TOP VIEW INV. INPUT (A) NON-INV. INPUT (A) OFFSET NULL (A) VOFFSET NULL (B) NON - INV. INPUT (B) INV. INPUT (B) 1 OFFSET 14 NULL (A) 2 13 V+† 3 12 OUTPUT (A) 4 11 NC 5 10 OUTPUT (B) 6 9 V+† 7 8 OFFSET NULL (B) INPUT A ≈ 10 A ≈ 10,000 - A≈1 OUTPUT C1 12pF V- OFFSET NULL NOTE: Only available with 14 lead DIP (E1 Suffix). † Pins 9 and 13 internally connected through approximately 3Ω. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1996 3-115 File Number 1050.3 CA3240, CA3240A Absolute Maximum Ratings Thermal Information Supply Voltage (Between V+ and V-) . . . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite Thermal Resistance (Typical, Note 2) θJA (oC/W) 8 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . 100 14 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or ±2V to ±18V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within maximum rating. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications For Equipment Design, VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified CA3240 PARAMETER SYMBOL MIN Input Offset Voltage VIO Input Offset Current IIO Input Current Large-Signal Voltage Gain (See Figures 13, 28) (Note 3) CA3240A TYP MAX MIN - 5 15 - - 0.5 30 - TYP MAX UNITS 2 5 mV 0.5 20 pA II - 10 50 - 10 40 pA AOL 20 100 - 20 100 - kV/V 86 100 - 86 100 - dB CMRR - 32 320 - 32 320 µV/V 70 90 - 70 90 - dB Common Mode Input Voltage Range (See Figure 25) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V Power Supply Rejection Ratio (See Figure 20) PSRR - 100 150 - 100 150 µV/V Common Mode Rejection Ratio (See Figure 18) (∆VIO/∆V±) 76 80 - 76 80 - dB Maximum Output Voltage (Note 4) (See Figures 24, 25) VOM+ 12 13 - 12 13 - V VOM- -14 -14.4 - -14 -14.4 - V Maximum Output Voltage (Note 5) VOM- 0.4 0.13 - 0.4 0.13 - V Total Supply Current (See Figure 16) For Both Amps I+ - 8 12 - 8 12 mA Total Device Dissipation PD - 240 360 - 240 360 mW NOTES: 3. At VO = 26VP-P, +12V, -14V and RL = 2kΩ. 4. At RL = 2kΩ. 5. At V+ = 5V, V- = GND, ISINK = 200µA. Electrical Specifications For Equipment Design, VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified TYPICAL VALUES PARAMETER SYMBOL Input Offset Voltage Adjustment Resistor (E1 Package Only) Input Resistance TEST CONDITIONS Typical Value of Resistor Between Terminals 4 and 3(5) or Between 4 and 14(8) to Adjust Maximum VIO RI CA3240A CA3240 UNITS 18 4.7 kΩ 1.5 1.5 TΩ Input Capacitance CI 4 4 pF Output Resistance RO 60 60 Ω Equivalent Wideband Input Noise Voltage (See Figure 2) eN 48 48 µV BW = 140kHz, RS = 1MΩ 3-116 CA3240, CA3240A Electrical Specifications For Equipment Design, VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified TYPICAL VALUES PARAMETER SYMBOL Equivalent Input Noise Voltage (See Figure 19) eN Short-Circuit Current to Opposite Supply TEST CONDITIONS CA3240A CA3240 UNITS f = 1kHz, RS = 100Ω 40 40 nV/√Hz f = 10kHz, RS = 100Ω 12 12 nV/√Hz IOM+ Source 40 40 mA IOM- Sink 11 11 mA fT 4.5 4.5 MHz SR 9 9 V/µs Gain Bandwidth Product (See Figures 14, 28) Slew Rate (See Figure 15) Transient Response (See Figure 1) Settling Time at 10 VP-P (See Figure 26) tr RL = 2kΩ, CL = 100pF Rise Time 0.08 0.08 µs OS RL = 2kΩ, CL = 100pF Overshoot 10 10 % AV = +1, RL = 2kΩ, CL = 100pF, Voltage Follower To 1mV 4.5 4.5 µs To 10mV 1.4 1.4 µs 120 120 dB tS Crosstalk (See Figure 23) f = 1kHz Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = -40 to 85oC, Unless Otherwise Specified TYPICAL VALUES SYMBOL CA3240A CA3240 UNITS Input Offset Voltage PARAMETER |VIO| 3 10 mV Input Offset Current (Note 8) |IIO| 32 32 pA II 640 640 pA AOL 63 63 kV/V 96 96 dB Input Current (Note 8) Large Signal Voltage Gain (See Figures 13, 28), (Note 6) Common Mode Rejection Ratio (See Figure 18) CMRR 32 32 µV/V 90 90 dB Common Mode Input Voltage Range (See Figure 25) VICR -15 to +12.3 -15 to +12.3 V Power Supply Rejection Ratio (See Figure 20) PSRR 150 150 µV/V (∆VIO/∆V±) 76 76 dB VOM+ 12.4 12.4 V VOM- -14.2 -14.2 V I+ 8.4 8.4 mA PD 252 252 mW ∆VIO/∆T 15 15 µV/oC Maximum Output Voltage (Note 7) (See Figures 24, 25) Supply Current (See Figure 16) Total For Both Amps Total Device Dissipation Temperature Coefficient of Input Offset Voltage NOTES: 6. At VO = 26VP-P, +12V, -14V and RL = 2kΩ. 7. At RL = 2kΩ. 8. At TA = 85oC. Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified TYPICAL VALUES PARAMETER SYMBOL CA3240A CA3240 UNITS Input Offset Voltage |VIO| 2 5 mV Input Offset Current |IIO| 0.1 0.1 pA II 2 2 pA Input Resistance RIN 1 1 TΩ Large Signal Voltage Gain (See Figures 13, 28) AOL 100 100 kV/V 100 100 dB Input Current 3-117 CA3240, CA3240A Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified (Continued) TYPICAL VALUES PARAMETER SYMBOL Common-Mode Rejection Ratio CA3240A CMRR Common-Mode Input Voltage Range (See Figure 25) VICR CA3240 UNITS 32 32 µV/V 90 90 dB -0.5 -0.5 V 2.6 2.6 V 31.6 31.6 µV/V Power Supply Rejection Ratio PSRR 90 90 dB Maximum Output Voltage (See Figures 24, 25) VOM+ 3 3 V Maximum Output Current VOM- 0.3 0.3 V Source IOM+ 20 20 mA Sink IOM- 1 1 mA Slew Rate (See Figure 15) SR 7 7 V/µs Gain Bandwidth Product (See Figure 14) fT 4.5 4.5 MHz Supply Current (See Figure 16) I+ 4 4 mA Device Dissipation PD 20 20 mW Test Circuits and Waveforms 50mV/Div., 200ns/Div. Top Trace: Input, Bottom Trace: Output 5V/Div., 1µs/Div. Top Trace: Input, Bottom Trace: Output FIGURE 1A. SMALL SIGNAL RESPONSE FIGURE 1B. LARGE SIGNAL RESPONSE +15V 0.1µF 10kΩ SIMULATED LOAD + CA3240 - 100pF 2kΩ 0.1µF -15V 2kΩ BW (-3dB) = 4.5MHz SR = 9V/µs 0.05µF FIGURE 1C. TEST CIRCUIT FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS 3-118 CA3240, CA3240A Test Circuits and Waveforms (Continued) +15V 0.01µF RS + 1MΩ NOISE VOLTAGE OUTPUT CA3240 - 30.1kΩ 0.01µF -15V 1kΩ BW (-3dB) = 140kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 48µV (TYP) FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT Schematic Diagram (One Amplifier of Two) BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK V+ D7 D1 Q2 Q1 Q3 Q4 R11 20Ω Q7 Q17 R1 8K Q20 D8 R10 Q19 1K Q5 Q6 R13 15K R9 50Ω R12 12K R14 20K Q21 R8 1K Q8 OUTPUT Q18 D2 D4 D3 D5 INVERTING INPUT - Q9 Q10 NON-INVERTING INPUT + R2 500Ω Q11 R4 500Ω C1 12pF R3 500Ω Q13 Q14 Q15 Q16 D6 Q12 R6 50Ω R5 500Ω OFFSET NULL (NOTE 9) R7 30Ω V- NOTES: 9. Only available with 14 Lead DIP (E1 Suffix). 10. All resistance values are in ohms. 3-119 CA3240, CA3240A Application Information Circuit Description The schematic diagram details one amplifier section of the CA3240. It consists of a differential amplifier stage using PMOS transistors (Q9 and Q10) with gate-to-source protection against static discharge damage provided by zener diodes D3, D4, and D5. Constant current bias is applied to the differential amplifier from transistors Q2 and Q5 connected as a constant current source. This assures a high common-mode rejection ratio. The output of the differential amplifier is coupled to the base of gain stage transistor Q13 by means of an NPN current mirror that supplies the required differential-to-single-ended conversion. Provision for offset null for types in the 14 lead plastic package (E1 suffix) is provided through the use of this current mirror. CA3240 is used as a unity-gain voltage follower. This resistance prevents the possibility of extremely large input-signal transients from forcing a signal through the input-protection network and directly driving the internal constant-current source which could result in positive feedback via the output terminal. A 3.9kW resistor is sufficient. The typical input current is on the order of 10pA when the inputs are centered at nominal device dissipation. As the output supplies load current, device dissipation will increase, rasing the chip temperature and resulting in increased input current. Figure 4 shows typical input-terminal current versus ambient temperature for the CA3240. +HV V+ The gain stage transistor Q13 has a high impedance active load (Q3 and Q4) to provide maximum open-loop gain. The collector of Q13 directly drives the base of the compound emitter-follower output stage. Pulldown for the output stage is provided by two independent circuits: (1) constant-current-connected transistors Q14 and Q15 and (2) dynamic current-sink transistor Q16 and its associated circuitry. The level of pulldown current is constant at about 1mA for Q15 and varies from 0 to 18mA for Q16 depending on the magnitude of the voltage between the output terminal and V+. The dynamic current sink becomes active whenever the output terminal is more negative than V+ by about 15V. When this condition exists, transistors Q21 and Q16 are turned on causing Q16 to sink current from the output terminal to V-. This current always flows when the output is in the linear region, either from the load resistor or from the emitter of Q18 if no load resistor is present. The purpose of this dynamic sink is to permit the output to go within 0.2V (VCE (sat)) of Vwith a 2kΩ load to ground. When the load is returned to V+, it may be necessary to supplement the 1mA of current from Q15 in order to turn on the dynamic current sink (Q16). This may be accomplished by placing a resistor (Approx. 2kΩ) between the output and V-. LOAD CA3240 RL RS LOAD 120VAC 30V NO LOAD CA3240 MT2 MT1 RL FIGURE 3. METHODS OF UTILIZING THE VCE (SAT) SINKING CURRENT CAPABILITY OF THE CA3240 SERIES Output Circuit Considerations 10K Figure 3 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. VS = ±15V INPUT CURRENT (pA) Figure 24 shows output current-sinking capabilities of the CA3240 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level-shifting circuitry usually associated with the 741 series of operational amplifiers. 1K 100 10 -60 Input Circuit Considerations As indicated by the typical VICR, this device will accept inputs as low as 0.5V below V-. However, a series currentlimiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current-limiting resistance should be provided between the inverting input and the output when the -40 -20 0 20 40 60 80 TEMPERATURE (oC) 100 120 140 FIGURE 4. INPUT CURRENT vs TEMPERATURE It is well known that MOSFET devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures. 3-120 CA3240, CA3240A Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite polarity reverse the offset. In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. Offset-Voltage Nulling The input offset voltage of the CA3240AE1 and CA3240E1 can be nulled by connecting a 10kΩ potentiometer between Terminals 3 and 14 or 5 and 8 and returning its wiper arm to Terminal 4, see Figure 5A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors that may be placed at either end of the potentiometer, see Figure 5B, to optimize its utilization range are given in the table “Electrical Specifications for Equipment Design” shown on third page of this data sheetAn alternate system is shown in Figure 5C. This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to 0Ω at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used. Typical Applications On/Off Touch Switch The on/off touch switch shown in Figure 6 uses the CA3240E to sense small currents flowing between two contact points on a touch plate consisting of a PC board metalli- zation “grid”. When the “on” plate is touched, current flows between the two halves of the grid causing a positive shift in the output voltage (Terminal 7) of the CA3240E. These positive transitions are fed into the CA3059, which is used as a latching circuit and zero-crossing TRIAC driver. When a positive pulse occurs at Terminal 7 of the CA3240E, the TRIAC is turned on and held on by the CA3059 and its associated positive feedback circuitry (51kΩ resistor and 36kΩ/42kΩ voltage divider). When the positive pulse occurs at Terminal 1 (CA3240E), the TRIAC is turned off and held off in a similar manner. Note that power for the CA3240E is supplied by the CA3059 internal power supply. The advantage of using the CA3240E in this circuit is that it can sense the small currents associated with skin conduction while allowing sufficiently high circuit impedance to provide protection against electrical shock. Dual Level Detector (Window Comparator) Figure 7 illustrates a simple dual liquid level detector using the CA3240E as the sensing amplifier. This circuit operates on the principle that most liquids contain enough ions in solution to sustain a small amount of current flow between two electrodes submersed in the liquid. The current, induced by an 0.5V potential applied between two halves of a PC board grid, is converted to a voltage level by the CA3240E in a circuit similar to that of the on/off touch switch shown in Figure 6. The changes in voltage for both the upper and lower level sensors are processed by the CA3140 to activate an LED whenever the liquid level is above the upper sensor or below the lower sensor.. V+ V+ 13(9) 1(7) CA3240 12(10) CA3240 2(6) 4 14 (8) 3 (5) R (NOTE 11) 10kΩ R (NOTE 11) 10kΩ V- V- FIGURE 5A. BASIC FIGURE 5B. IMPROVED RESOLUTION V+ CA3240 10kΩ (NOTE 11) R V- FIGURE 5C. SIMPLER IMPROVED RESOLUTION NOTE: 11. See Electrical Specification Table on Third page of this data sheet for value of R. FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1, CA3240E1 ONLY) 3-121 CA3240, CA3240A 44M 10K (2W) 120V/220V AC 60Hz/50Hz +6V +6V “ON” 51K 8 1M 6 +6V 0.01µF 5 5.1M 36K - 1/2 CA3240 5 7 1M 3 2 0.01µF 1N914 9 MT2 8 40W 120V LIGHT T2300B (NOTE 10) CA3059 G 10 MT1 4 11 + 1/2 CA3240 COMMON 7 1 2 1N914 - 1M 12K 13 + 42K “OFF” RS (NOTE 10) + +6V SOURCE 4 - 100µF (16V) 44M NOTE: 12. At 220V operation, TRIAC should be T2300D, RS = 18K, 5W. FIGURE 6. ON/OFF TOUCH SWITCH 12M +15V 8 100K 3 +15V - 1/2 2 +15V 0.1µF CA3240 + 1 7 33K 3 240K HIGH LEVEL 160K (0.5V) 8.2K 2 5 100K 6 + 1/2 CA3240 + CA3140 100K - LED 7 4 LOW LEVEL 6 680Ω 4 100K 0.1µF LED ON WHEN LIQUID OUTSIDE OF LIMITS 12M FIGURE 7. DUAL LEVEL DETECTER Constant-Voltage/Constant-Current Power Supply Precision Differential Amplifier The constant-voltage/constant-current power supply shown in Figure 8 uses the CA3240E1 as a voltage-error and current-sensing amplifier. The CA3240E1 is ideal for this application because its input common-mode voltage range includes ground, allowing the supply to adjust from 20mV to 25V without requiring a negative supply voltage. Also, the ground reference capability of the CA3240E1 allows it to sense the voltage across the 1Ω current-sensing resistor in the negative output lead of the power supply. The CA3086 transistor array functions as a reference for both constantvoltage and constant-current limiting. The 2N6385 power Darlington is used as the pass element and may be required to dissipate as much as 40W. Figure 9 shows the transient response of the supply during a 100mA to 1A load transition. Figure 10 shows the CA3240E in the classical precision differential amplifier circuit. The CA3240E is ideally suited for biomedical applications because of its extremely high input impedance. To insure patient safety, an extremely high electrode series resistance is required to limit any current that might result in patient discomfort in the event of a fault condition. In this case, 10MΩ resistors have been used to limit the current to less than 2µA without affecting the performance of the circuit. Figure 11 shows a typical electrocardiogram waveform obtained with this circuit. 3-122 CA3240, CA3240A VO IO V+ 2N6385 2 10K 13 3 DARLINGTON 75Ω - 1/2 CA3240E1 + 12 3K 1 1 180K 2 + 4 - 100Ω 1N914 2.7K VI = 30V + - 100K 2000µF 50V 0.056µF 2.2K 82K V+ 10 2 + 5µF 16V - 11 9 1 100K 7 14 CA3086E 9 TRANSISTOR ARRAY 8 100K 6 12 3 - 1/2 CA3240E1 + 13 5 820Ω 7 680K 50K 1K 4 6 6.2K 100K CHASSIS GROUND VO RANGE = 20mV TO 25V LOAD REGULATION: VOLTAGE <0.08% CURRENT <0.05% 1Ω 1W OUTPUT HUM AND NOISE ≤ 150µVRMS (10MHz BANDWIDTH) SINE REGULATION ≤ 0.1%/VO IO RANGE = 10mA - 1.3A FIGURE 8. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY Top Trace: Output Voltage; 500mV/Div., 5µs/Div. Bottom Trace: Collector Of Load Switching Transistor Load = 100mA to 1A; 5V/Div., 5µs/Div. FIGURE 9. TRANSIENT RESPONSE 3-123 10 500 µF CA3240, CA3240A +15V 0.1µF 8 100K 1% 10M + 1/2 CA3240 3 - 2 GAIN CONTROL 1 2000pF 2000pF +15V 1% 5.1K 100K 1% 100K 7 0.1µF OUTPUT 2 6 CA3140 3.9K 3 100K 1% TWO COND. SHIELDED CABLE 6 5 - 5.1K 1% 2K 4 0.1µF 2000pF 1/2 CA3240 + -15V 7 FREQUENCY RESPONSE (-3dB) DC TO 1MHz SLEW RATE = 1.5V/µs COMMON MODE REJ: 86dB GAIN RANGE: 35dB TO 60dB 10M 4 0.1µF -15V FIGURE 10. PRECISION DIFFERENTIAL AMPLIFIER Vertical: 1.0mV/Div. Amplifier Gain = 100X Scope Sensitivity = 0.1V/Div. Horizontal: >0.2s/Div. (Uncal) FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM Differential Light Detector In the circuit shown in Figure 12, the CA3240E converts the current from two photo diodes to voltage, and applies 1V of reverse bias to the diodes. The voltages from the CA3240E outputs are subtracted in the second stage (CA3140) so that only the difference is amplified. In this manner, the circuit can be used over a wide range of ambient light conditions without circuit component adjustment. Also, when used with a light source, the circuit will not be sensitive to changes in light level as the source ages. 3-124 CA3240, CA3240A 0.015µF 100K +15V +15V 8 2 +15V 1/2 CA3240E 5.1K C30809 PHOTO DIODE - 3 1 3 200K 1.3 K 5 13K 6 7 2K + + 1/2 CA3240E + CA3140 2 2K 7 OUTPUT 6 4 - -15V 4 C30809 PHOTO DIODE -15V 200k 100K 0.015µF FIGURE 12. DIFFERENTIAL LIGHT DETECTOR RL = 2kΩ 125 GAIN BANDWIDTH PRODUCT (MHz) OPEN LOOP VOLTAGE GAIN (dB) Typical Performance Curves TA = -40oC 100 25oC 75 85oC 50 25 RL = 2kΩ CL = 100pF 20 10 TA = -40oC 25oC 85oC 1 0 5 10 15 20 0 25 5 10 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE TOTAL SUPPLY CURRENT (mA) FOR BOTH AMPS RL = 2kΩ CL = 100pF SLEW RATE (V/µs) 15 25oC TA = -40oC 10 85oC 5 0 25 FIGURE 14. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 10 20 20 RL = ∞ 9 25oC TA = -40oC 8 85oC 7 6 5 4 3 2 0 5 10 15 20 0 25 FIGURE 15. SLEW RATE vs SUPPLY VOLTAGE 5 10 15 20 25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 16. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 3-125 CA3240, CA3240A Typical Performance Curves (Continued) COMMON MODE REJECTION RATIO (dB) SUPPLY VOLTAGE: VS = ±15V TA = 25oC OUTPUT VOLTAGE (VP-P) 25 20 15 10 5 0 10K 100K 1M 120 SUPPLY VOLTAGE: VS = ±15V TA = 25oC 100 80 60 40 20 0 101 4M 102 103 FREQUENCY (Hz) POWER SUPPLY REJECTION RATIO (dB) EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz) RS = 100Ω 10 1 101 1 102 103 FREQUENCY (Hz) 104 +PSRR 60 -PSRR 40 20 102 103 104 105 106 107 FREQUENCY (Hz) FIGURE 20. POWER SUPPLY REJECTION RATIO vs FREQUENCY 17.5 SUPPLY CURRENT (mA) PER AMP (DOUBLE FOR BOTH) OUTPUT SINK CURRENT (mA) PER AMP 80 101 TA = 25oC VS = ±15V ONE AMPLIFIER OPERATING 10 107 SUPPLY VOLTAGE: VS = ±15V TA = 25oC POWER SUPPLY REJECTION RATIO = ∆VIO/∆VS 100 105 FIGURE 19. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 12 106 FIGURE 18. COMMON MODE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE: VS = ±15V TA = 25oC 100 105 FREQUENCY (Hz) FIGURE 17. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 1000 104 8 6 4 2 0 TA = 25oC VS = ±15V RL = ∞ 15 12.5 10 7.5 5 2.5 -15 -10 -5 0 5 OUTPUT VOLTAGE (V) 10 -15 15 FIGURE 21. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE -10 -5 0 5 10 OUTPUT VOLTAGE (V) 15 FIGURE 22. SUPPLY CURRENT vs OUTPUT VOLTAGE 3-126 CA3240, CA3240A 130 120 110 100 90 80 0.1 101 1 102 1000 SATURATION VOLTAGE (mV) TA = 25oC AMP A → AMP B AMP B → AMP A VS = ±15V VO = 5VRMS 140 CROSSTALK (dB) (Continued) OUTPUT STAGE TRANSISTOR (Q15, Q16) Typical Performance Curves 103 V- = 0V TA = 25oC V+ = +5V 100 +30V 10 1.0 0.01 0.1 FREQUENCY (Hz) RL = ∞ INPUT AND OUTPUT VOLTAGE REFERENCED TO TERMINAL 4 (V) INPUT AND OUTPUT VOLTAGE REFERENCED TO TERMINAL 7 (V) RL = ∞ OUTPUT VOLTAGE (+VO) COMMON MODE VOLTAGE (+VICR) -1 TA = 25oC TA = 85oC TA = 85oC -2 -2.5 TA = 25oC -3 0 10 FIGURE 24. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15 AND Q16 vs LOAD CURRENT 0 -1.5 1.0 LOAD (SINKING) CURRENT (mA) FIGURE 23. CROSSTALK vs FREQUENCY -0.5 +15V 5 TA = -40oC TA = -40oC 10 15 SUPPLY VOLTAGE (V) 20 25 1.5 OUTPUT VOLTAGE (+VO) COMMON MODE VOLTAGE (+VICR) 1.0 0.5 TA = -40oC TO 85oC 0 TA = 85oC -0.5 TA = -40oC -1.0 TA = 25oC -1.5 0 5 10 15 20 SUPPLY VOLTAGE (V) FIGURE 25A. FIGURE 25B. FIGURE 25. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE 3-127 25 CA3240, CA3240A Typical Performance Curves (Continued) SUPPLY VOLTAGE: VS = ±15V TA = 25oC, RL = 2kΩ, CL = 100pF +15V 10 1mV INPUT VOLTAGE (V) 8 10mV 1mV 0.1µF 10mV 6 SIMULATED LOAD + 10kΩ 4 CA3240 - 2 2kΩ 100pF FOLLOWER 0 INVERTING 0.1µF -2 -15V -4 1mV -6 -8 10mV -10 0.1 2 4 6 1mV 2kΩ 10mV 8 2 1.0 TIME (µs) 4 6 8 0.05µF 10 FIGURE 26A. SETTLING TIME vs INPUT VOLTAGE FIGURE 26B. TEST CIRCUIT (FOLLOWER) 5kΩ +15V 0.1µF 5kΩ SIMULATED LOAD CA3240 + 200Ω 2kΩ 100pF 0.1µF -15V 4.99kΩ 5.11kΩ SETTLING POINT D2 1N914 D1 1N914 FIGURE 26C. TEST CIRCUIT (INVERTING) FIGURE 26. INPUT VOLTAGE vs SETTLING TIME OPEN LOOP VOLTAGE GAIN (dB) INPUT CURRENT (pA) 1K 100 10 1 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 27. INPUT CURRENT vs TEMPERATURE 100 PHASE RL = 2kΩ, CL = 0pF -105 -135 RL = 2kΩ, CL = 100pF 60 -150 GAIN 40 20 102 103 104 105 106 107 108 FREQUENCY (Hz) FIGURE 28. OPEN LOOP VOLTAGE GAIN AND PHASE vs FREQUENCY 3-128 -90 -120 80 0 101 140 -75 VS = ±15V TA = 25oC VS = ±15V OPEN LOOP PHASE (DEGREES) 10K