LT1671 60ns, Low Power, Single Supply, Ground-Sensing Comparator U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Power: 450µA Fast: 60ns at 20mV Overdrive 85ns at 5mV Overdrive Low Offset Voltage: 0.8mV Operates Off Single 5V or Dual ±5V Supplies Input Common Mode Extends to Negative Supply No Minimum Input Slew Rate Requirement Complementary TTL Outputs Inputs Can Exceed Supplies without Phase Reversal Pin Compatible with LT1394, LT1016 and LT1116 Output Latch Capability Available in 8-Lead MSOP and SO Packages U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ High Speed A/D Converters Zero-Crossing Detectors Current Sense for Switching Regulators Extended Range V/F Coverters Fast Pulse Height/Width Discriminators High Speed Triggers Line Receivers High Speed Sampling Circuits The LT ®1671 is a low power 60ns comparator with complementary outputs and latch. The input common mode range extends from 1.5V below the positive supply down to the negative supply rail. Like the LT1394, LT1016 and LT1116, this comparator has complementary outputs designed to interface directly to TTL or CMOS logic. The LT1671 may operate from either a single 5V supply or dual ±5V supplies. Low offset voltage specifications and high gain allow the LT1671 to be used in precision applications. The LT1671 is designed for improved speed and stability for a wide range of operating conditions. The output stage provides active drive in both directions for maximum speed into TTL, CMOS or passive loads with minimal cross-conduction current. Unlike other fast comparators, the LT1671 remains stable even for slow transitions through the active region, which eliminates the need to specify a minimum input slew rate. The LT1671 has an internal, TTL/CMOS compatible latch for retaining data at the outputs. The latch holds data as long as the LATCH pin is held high. Device parameters such as gain, offset and negative power supply current are not significantly affected by variations in negative supply voltage. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Propagation Delay vs Overdrive 140 1MHz Crystal Oscillator VS = ±5V VSTEP = 100mV TA = 25°C RL = 1M 120 5V 1MHz CRYSTAL (AT-CUT) 100 TIME (ns) 2k + 2k LT1671 OUTPUT 80 FALLING EDGE (tPDHL) 60 – 40 2k 0.068µF 20 1671 TA01 1671 TA01 RISING EDGE (tPDLH) 0 10 20 30 OVERDRIVE (mV) 40 50 1671 TA02 1 LT1671 U W W W ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V–) ............................... 12V Positive Supply Voltage ............................................. 7V Negative Supply Voltage .......................................... – 7V Differential Input Voltage ....................................... ±12V Input and Latch Current (Note 2) ........................ ±10mA Output Current (Continuous)(Note 2) ................. ±20mA Operating Temperature Range ................ – 40°C to 85°C Specified Temperature Range (Note 3) ... – 40°C to 85°C Junction Temperature ........................................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................. 300°C W U U PACKAGE/ORDER INFORMATION ORDER PART NUMBER TOP VIEW V+ 1 +IN 2 –IN 3 V– 4 8 7 6 5 Q OUT Q OUT GND LATCH ENABLE MS8 PACKAGE 8-LEAD PLASTIC MSOP LT1671CMS8 V+ 1 +IN 2 –IN 3 MS8 PART MARKING TJMAX = 150°C, θJA = 250°C/ W LTCT ORDER PART NUMBER TOP VIEW V– 4 8 Q OUT + – LT1671CS8 LT1671IS8 7 Q OUT 6 GND 5 LATCH ENABLE S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO 1671 1671I TJMAX = 150°C, θJA = 190°C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V + = 5V, V – = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage RS ≤ 100Ω (Note 4) MIN TYP MAX 0.8 2.5 4.0 ● ∆VOS ∆T IOS Input Offset Voltage Drift Input Offset Current 10 100 150 nA nA 120 280 350 nA nA 3.5 3.5 V V ● IB Input Bias Current (Note 5) ● VCMR Input Voltage Range (Note 6) Single 5V Supply CMRR Common Mode Rejection Ratio –5 0 – 5V ≤ VCM ≤ 3.5V, TA > 0°C – 5V ≤ VCM ≤ 3.3V, TA ≤ 0°C 55 55 100 dB dB Single 5V Supply 0V ≤ VCM ≤ 3.5V, TA > 0°C 0V ≤ VCM ≤ 3.3V, TA ≤ 0°C 55 55 100 dB dB 50 60 85 90 dB dB 2500 5000 V/V PSRR Power Supply Rejection Ratio 4.6V ≤ V + ≤ 5.4V – 7V ≤ V – ≤ – 2V AV Small Signal Voltage Gain 1V ≤ VOUT ≤ 2V 2 ● ● mV mV µV/°C 4 ● UNITS ● ● LT1671 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V + = 5V, V – = – 5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOH Output Voltage Swing High V+ ≥ 4.6V, IOUT = 400µA V + ≥ 4.6V, IOUT = 4mA ● ● VOL Output Voltage Swing Low IOUT = – 400µA IOUT = – 4mA ● I+ Positive Supply Current MIN TYP 2.7 2.4 3.1 3.0 Negative Supply Current LATCH Pin High Input Voltage ● VIL LATCH Pin Low Input Voltage ● IIL LATCH Pin Current VLATCH = 0V t PD1 Propagation Delay ∆VIN = 100mV, VOD = 20mV ● V V 450 800 1000 µA µA 75 200 250 µA µA 2 V 0.8 – 1000 – 250 Propagation Delay (Note 7) ∆VIN = 100mV, VOD = 5mV nA 80 110 ns ns 85 100 130 ns ns 15 30 ns ● ∆VIN = 100mV, VOD = 5mV V 60 ● t PD2 V V 0.5 ● VIH UNITS 0.3 0.4 ● I– MAX ∆t PD Differential Propagation Delay (Note 7) t LPD Latch Propagation Delay (Note 8) 60 t SU Latch Setup Time (Note 8) – 15 ns tH Latch Hold Time (Note 8) 35 ns t PW(D) Minimum Disable Pulse Width 30 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This parameter is guaranteed to meet specified performance through design and characterization. It has not been tested. Note 3: The LT1671CS8 and LT1671CMS8 are guaranteed to meet specified performance from 0°C to 70°C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at – 40°C and 85°C. The LT1671IS8 is guaranteed to meet the extended temperature limits. Note 4: Input offset voltage (VOS) is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4V. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. ns Note 7: tPD and ∆tPD cannot be measured in automatic handling equipment with low values of overdrive. The LT1671 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that tPD and ∆tPD limits can be guaranteed with this test, if additional DC tests are performed to guarantee that all internal bias conditions are correct. Propagation delay (t PD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: ∆t PD = t PDLH – t PDHL Note 8: Latch propagation delay (t LPD) is the delay time for the output to respond when the LATCH pin is deasserted. Latch setup time (t SU) is the interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. 3 LT1671 U W TYPICAL PERFORMANCE CHARACTERISTICS Propagation Delay vs Load Capacitance Gain Characteristics VS = ±5V RL = 1M TA = 25°C 3.5 TA = – 55°C TIME (ns) 3.0 2.5 2.0 80 80 RISING EDGE (tPDLH) 70 VS = ±5V VSTEP = 100mV VOD = 5mV TA = 25°C RL = 1M 1.5 60 1.0 0.5 0 –3 50 –2 –1 1 2 0 DIFFERENTIAL INPUT VOLTAGE (mV) 0 3 50 10 20 30 40 OUTPUT LOAD CAPACITANCE (pF) 50 4.4 VS = ±5V RL = 1M VOD = 20mV TA = 25°C 180 160 TIME (ns) 80 FALLING EDGE (tPDHL) Propagation Delay vs Temperature 100 200 VS = ±5V VSTEP = 100mV TA = 25°C RL = 1M 80 400mV 70 140 200mV 120 40 RISING EDGE (tPDLH) 50 40 10 20 30 OVERDRIVE (mV) 20 60 40 0 STEP SIZE = 100mV 50 40 10 0 5 10 SOURCE RESISTANCE (kΩ) t PDLH 60 30 80 t PDHL 90 STEP SIZE = 800mV 100 60 5.6 4.6 4.8 5.0 5.2 5.4 POSITIVE SUPPLY VOLTAGE (V) 1671 G03 Propagation Delay vs Source Resistance 100 TIME (ns) V – = –5V VSTEP = 100mV VOD = 5mV TA = 25°C RL = 1M 1671 G02 Propagation Delay vs Input Overdrive 120 RISING EDGE (tPDLH) 70 60 1671 G01 140 FALLING EDGE (tPDHL) FALLING EDGE (tPDHL) 90 TIME (ns) 4.0 TIME (ns) TA = 125°C 4.5 OUTPUT VOLTAGE (V) 90 100 5.0 20 Propagation Delay vs Positive Supply Voltage VS = ±5V VSTEP = 100mV VOD = 5mV RL = 1M 0 –50 –25 15 50 0 75 25 TEMPERATURE (°C) 100 125 1671 TA02 1671 G05 Input Offset Voltage vs Temperature Input Bias Current vs Temperature 500 INPUT BIAS CURRENT (nA) VS = ±5V RL = 1M VOLTAGE (mV) 2 1 0 –1 Positive Common Mode Limit vs Temperature 6 VS = ±5V RL = 1M 5 400 VOLTAGE (V) 4 3 1671 G06 300 200 VCM = –5V VS = ±5V RL = 1M 4 3 2 100 VCM = 0V 1 –2 VCM = 3.5V –3 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 1671 G07 4 0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 1671 G08 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1671 G09 LT1671 U W TYPICAL PERFORMANCE CHARACTERISTICS Negative Common Mode Limit vs Temperature Output Low Voltage (VOL) vs Output Sink Current 1 0.8 RL = 1M 5.0 VS = ±5V VIN = 30mV 0.7 0 VS = SINGLE 5V SUPPLY –3 –4 OUTPUT VOLTAGE (V) –2 TA = –55°C 0.5 TA = 125°C 0.4 TA = 25°C 0.3 0.2 VS = ±5V –5 0.1 50 0 75 25 TEMPERATURE (°C) 100 4 6 10 8 12 2.5 2.0 14 4 8 6 10 12 OUTPUT SOURCE CURRENT (mA) 2 0 1671 G11 Positive Supply Current vs V + Supply Voltage 14 1671 G12 Positive Supply Current vs Switching Frequency Negative Supply Current vs V – Supply Voltage 3.5 V – = 0V VIN = –60mV IOUT = 0 0.5 TA = 25°C TA = –55°C 3.0 OUTPUT SINK CURRENT (mA) 1671 G10 0.6 TA = 125°C 3.5 1.0 2 0 125 4.0 1.5 0 –6 –50 –25 VS = ±5V VIN = –30mV 4.5 0.6 –1 VOLTAGE (V) INPUT VOLTAGE (V) Output High Voltage (VOH) vs Output Source Current 100 VS = ±5V VSTEP = ±50mV IOUT = 0 3.0 V+ = 5V VIN = –60mV IOUT = 0 90 TA = 25°C 0.3 TA = 125°C TA = –55°C 0.2 CURRENT (µA) CURRENT (mA) 0.4 2.0 TA = 125°C 1.5 TA = 125°C 70 TA = 25°C TA = 25°C 0.1 0 80 1.0 0.5 60 TA = –55°C TA = –55°C 0 0 1 2 6 4 3 5 SUPPLY VOLTAGE (V) 7 8 1 SWITCHING FREQUENCY (MHz) 0.1 50 –8 –7 –6 –5 –4 –3 –2 –1 NEGATIVE SUPPLY VOLTAGE (V) 0 1671 G15 Response to 15MHz ±10mV Sine Wave Latch Pin Current vs Temperature 1.0 10 1671 G14 1671 G13 CURRENT (µA) CURRENT (mA) 2.5 VS = ±5V 0.8 +IN 20mVP-P 10mV/DIV 0.6 3V Q OUT 1V/DIV 0.4 0V 0.2 0 –50 –25 50ns/DIV 50 0 75 25 TEMPERATURE (°C) 100 1671 G17 125 1671 G16 5 LT1671 U W TYPICAL PERFORMANCE CHARACTERISTICS tPD+ Response Time to 5mV Overdrive tPD– Response Time to 5mV Overdrive 1.4V 1.4V 5mV 5mV +IN +IN Q OUT – 95mV 0V VS = ±5V VOD = 5mV Q OUT – 95mV VS = ±5V VOD = 5mV 20ns/DIV 1671 G18 0V 20ns/DIV 1671 G19 U U U PIN FUNCTIONS V + (Pin 1): Positive Supply Voltage. Normally 5V. GND (Pin 6): Ground. +IN (Pin 2): Noninverting Input. –IN (Pin 3): Inverting Input. Q OUT (Pin 7): Noninverting Logic Output. This pin is high when +IN is above – IN and LATCH ENABLE is low. V – (Pin 4): Negative Supply Voltage. Normally either 0V or – 5V. Q OUT (Pin 8): Inverting Logic Output. This pin is low when +IN is above – IN and LATCH ENABLE is low. LATCH ENABLE (Pin 5): Latch Control Pin. When high, the outputs remain in a latched condition, independent of the current state of the inputs. WU W TI I G DIAGRA S VOD VIN LATCH ENABLE ∆VIN tH tSU tPD VIN VOUT tPD 1671 TD01 VOUT 1671 TD02 6 LT1671 U U W U APPLICATIONS INFORMATION Common Mode Considerations Input Bias Current The LT1671 is specified for a common mode range of – 5V to 3.5V on a ±5V supply or a common mode range of 0V to 3.5V on a single 5V supply. A more general consideration is that the common mode range is 0V below the negative supply and 1.5V below the positive supply, independent of the actual supply voltage. The criterion for common mode limit is that the output still responds correctly to a small differential input signal. Input bias current is measured with the output held at 1.4V. As with any PNP differential input stage, the LT1671 bias current flows out of the device. It will go to zero on an input which is high and double on an input which is low. When either input signal falls below the negative common mode limit, the internal PN diode formed with the substrate can turn on, resulting in significant current flow through the die. An external Schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the substrate diode from turning on. The zero crossing detector in Figure 1 demonstrates the use of a fast clamp diode. The zero crossing detector terminates the transmission line at its 50Ω characteristic impedance. Negative inputs should not fall below –2V to keep the signal current within the clamp diode’s maximum forward rating. Positive inputs should not exceed the devices absolute maximum ratings nor the power rating on the terminating resistor. RS 50Ω 5V CABLE + VIN 1N5712 RT 50Ω Q LT1671 – Q 1671 F01 Figure 1. Fast Zero Crossing Detector Either input may go above the positive common mode limit without damaging the comparator. The upper voltage limit is determined by an internal diode from each input to the positive supply. The input may go above the positive supply as long as it does not go far enough above it to conduct more than 10mA. Functionality will continue if the remaining input stays within the allowed common mode range. There will, however, be an increase in propagation delay as the input signal switches back into the common mode range. LATCH Pin Dynamics The LATCH pin is intended to retain input data (output latched) when the LATCH pin goes high. The pin will float to a high state when disconnected, so a flow-through condition requires that the LATCH pin be grounded. The LATCH pin is designed to be driven with either a TTL or CMOS output. It has no built-in hysteresis. To guarantee data retention, the input signal must remain valid at least 35ns after the latch goes high (hold time), and must be valid at least – 15ns before the latch goes high (setup time). The negative setup time simply means that the data arriving 15ns after (rather than before) the latch signal is valid. When the latch signal goes low, new data will appear at the output in approximately 60ns (latch propagation delay). Measuring Response Time To properly measure the response of the LT1671 requires an input signal source with very fast rise times and exceptionally clean settling characteristics. The last requirement comes about because the standard comparator test calls for an input step size that is large compared to the overdrive amplitude. Typical test conditions are 100mV step size with 5mV overdrive. This requires an input signal that settles to within 1% (1mV) of final value in only a few nanoseconds with no ringing or settling tail. Ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to check its fidelity. Some means must be used to inherently generate a fast, clean edge with known final value. The circuit shown in Figure 2 is the best electronic means of generating a fast, clean step to test comparators. It uses a very fast transistor in a common base configuration. The transistor is switched off with a fast edge from the generator and the collector voltage settles to exactly 0V in just a few nanoseconds. The most important feature of this 7 LT1671 U U W U APPLICATIONS INFORMATION 5V 0.01µF* 0V 25Ω –100mV 25Ω 0.1µF + 2N3866 10k V1** – FET PROBE Q 0.01µF 50Ω 0V –3V FET PROBE LT1671 130Ω PULSE IN Q * TOTAL LEAD LENGTH INCLUDING DEVICE PIN. SOCKET AND CAPACITOR LEADS SHOULD BE LESS THAN 0.5 IN. USE GROUND PLANE ** (VOS + OVERDRIVE)/200 50Ω 400Ω 750Ω –5V 1671 F02 –5V Figure 2. Response Time Test Circuit circuit is the lack of feedthrough from the generator to the comparator input. This prevents overshoot on the comparator input, which would give a false fast reading on comparator response time. Bypass capacitors should be as close as possible to the LT1671. A good high frequency capacitor such as a 0.1µF ceramic is recommended, in parallel with a larger capacitor such as a 4.7µF tantalum. To adjust the circuit for exactly 5mV overdrive, V1 is adjusted so that the LT1671 output under test settles to 1.4V (in the linear region). Then V1 is changed by – 1V to set overdrive to 5mV. Poor trace routes and high source impedances are also common sources of problems. Be sure to keep trace lengths as short as possible, and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, be sure to terminate them with a resistor to eliminate any reflections that may occur. Resistor values are typically 250Ω to 400Ω. Also, be sure to keep source impedances as low as possible, preferably 1kΩ or less. High Speed Design Techniques A substantial amount of design effort has made the LT1671 relatively easy to use. It is much less prone to oscillation than some slower comparators, even with slow input signals. However, as with any high speed comparator, there are a number of problems which may arise because of PC board layout and design. The most common problem involves power supply bypassing. Bypassing is necessary to maintain low supply impedance. DC resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels. This allows the supply line to move with changing internal current levels of the connected devices. This will almost always result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, keeping supply impedances low. 8 About Level Shifts The LT1671’s logic output will interface with many circuits directly. Many applications, however, require some form of level shifting of the output swing. With LT1671based circuits this is not trivial because it is desirable to maintain very low delay in the level shifting stage. When designing level shifters, keep in mind that the TTL output of the LT1671 is a sink-source pair (Figure 3) with good ability to drive capacitance (such as feedforward capacitors). Figure 4 shows a noninverting voltage gain stage with a 15V output. When the LT1671 switches, the baseemitter voltages at the 2N2369 reverse, causing it to switch very quickly. The 2N3866 emitter-follower gives a low impedance output and the Schottky diode aids current sink capability. LT1671 U U W U APPLICATIONS INFORMATION LT1671 is the key to low delay, providing Q2’s base with nearly ideal drive. This capacitor loads the LT1671’s output transition, but Q2’s switching is clean with 3ns delay on the rise and fall of the pulse. Figure 6 is similar to Figure 4 except that a sink transistor has replaced the Schottky diode. The two emitter-followers drive a power MOSFET that switches 1A at 15V. Most of the 7ns to 9ns delay in this stage occurs in the MOSFET and the 2N2369. +V OUTPUT = 0 → +V (TYPICALLY 3V TO 4V) 1671 F03 Figure 3. Simplified LT1671 Output Stage When designing level shifters, remember to use transistors with fast switching times and high fT. To get the kind of results shown, switching times in the nanosecond range and an fT approaching 1GHz are required. 15V 1k 2N2369 + 2N3866 HP5082-2810 LT1671 15V OUT – 1k 12pF 1k 1k RISE TIME = 4ns FALL TIME = 5ns RL 2N2369 + 1671 F04 2N3866 POWER FET LT1671 – Figure 4. Level Shift Has Noninverting Voltage Gain 2N5160 1k 1k 12pF 1671 F06 Figure 5 is a very versatile stage. It features a bipolar swing that is set by the output transistor’s supplies. This 3ns delay stage is ideal for driving FET switch gates. Q1, a gated current source, switches the Baker-clamped output transistor, Q2. The heavy feedforward capacitor from the RISE TIME = 7ns FALL TIME = 9ns Figure 6. Noninverting Voltage Gain Level Shift 5V + INPUT LT1671 – 1N4148 4.7k 430Ω Q1 2N2907 1000pF 0.1µF 820Ω 5V (TYP) HP5082-2810 330Ω Q2 2N2369 RISE TIME = 3ns FALL TIME = 3ns 5V OUTPUT –10V OUTPUT TRANSISTOR SUPPLIES (SHOWN IN HEAVY LINES) CAN BE REFERENCED ANYWHERE BETWEEN 15V AND –15V 1671 F05 820Ω –10V (TYP) Figure 5. Level Shift with Inverting Voltage Gain—Bipolar Swing 9 LT1671 U U W U APPLICATIONS INFORMATION Crystal Oscillators Switchable Output Crystal Oscillator Figure 7 shows a crystal oscillator circuit. In the circuit, the resistors at the LT1671’s positive input set a DC bias point. The 2k-0.068µF path sets up phase shifted feedback and the circuit looks like a wideband unity-gain follower at DC. The crystal’s path provides resonant positive feedback and stable oscillation occurs. Figure 8 permits crystals to be electronically switched by logic commands. This circuit is similar to the previous examples, except that oscillation is only possible when one of the logic inputs is biased high. XTAL X RX DX XTAL B 5V LOGIC INPUTS AS MANY STAGES AS DESIRED 1k B 2k 1MHz TO 10MHz CRYSTAL (AT-CUT) 5V XTAL A 1k A 1k LT1671 2k D1 + + OUTPUT – – OUTPUT LT1671 1k D2 2k 2k 1671 F08 1671 F07 0.068µF 75pF = 1N4148 GROUND XTAL CASES Figure 7. 1MHz to 10MHz Crystal Oscillator 10 Figure 8. Switchable Output Crystal Oscillator. Biasing A or B High Places Associated Crystal in Feedback Path. Additional Crystal Branches Are Permissible LT1671 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 7 6 5 0.118 ± 0.004** (3.00 ± 0.102) 0.192 ± 0.004 (4.88 ± 0.10) 1 2 3 4 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 0.034 ± 0.004 (0.86 ± 0.102) 0° – 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 0.021 ± 0.006 (0.53 ± 0.015) 0.006 ± 0.004 (0.15 ± 0.102) MSOP (MS8) 1197 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0996 11 LT1671 U TYPICAL APPLICATION LT1671’s positive input. The LT1671’s negative input is biased directly from A1’s output. The LT1671’s output, the circuit’s output, is unaffected by > 85:1 signal amplitude variations. Bandwidth limiting in A1 does not affect triggering because the adaptive trigger threshold varies ratiometrically to maintain circuit output. 4MHz Adaptive Trigger Circuit Line and fiber-optic receivers often require an adaptive trigger to compensate for variations in signal amplitude and DC offsets. The circuit in Figure 9 triggers on 2mV to 175mV signal from 100Hz to 4MHz while operating from a single 5V rail. A1, operating at a gain of 15, provides wideband AC gain. The output of this stage biases a 2-way peak detector (Q1 through Q4). The maximum peak is stored in Q2’s emitter capacitor, while the minimum excursion is retained in Q4’s emitter capacitor. The DC value of the midpoint of A1’s output signal appears at the junction of the 500pF capacitor and the 3MΩ units. This point always sits midway between the signal’s excursions, regardless of absolute amplitude. This signal-adaptive voltage is buffered by A2 to set the trigger voltage at the Figure 10 shows operating waveforms at 4MHz. Trace A’s input produces Trace B’s amplified output at A1. The comparator’s output is Trace C. A = 10mV/DIV B = 50mV/DIV C = 1mV/DIV 5V 2k 50ns/DIV 3 Q1 1 5 2 5V 1671F10 6 Q2 4 3M + 0.005µF A1 LT1227 750ΩΩ 5V + – 13 2k 500pF 0.005µF – 510ΩΩ 36ΩΩ 12 15 A2 LT1006 3M 10 14 Q3 5V Figure 10. Adaptive Trigger Responding to a 4MHz, 5mV Input. Input Amplitude Variations from 2mV to 175mV Are Accommodated Q4 11 470ΩΩ + 10µF + 0.1µF 100µF 0.1µF + 2k 0.1µF 470Ω – LT1671 TRIGGER OUT INPUT 1671 F09 Q1, Q2, Q3, Q4 = CA3096 ARRAY: TIE SUBSTRATE (PIN 16) TO GROUND = 1N4148 Figure 9. 4MHz Single Supply Adaptive Trigger. Output Comparator’s Threshold Varies Ratiometrically with Input Amplitude, Maintaining Data Integrity over >85:1 Input Amplitude Range RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1016 UltraFastTM Precision Comparator Industry Standard 10ns Comparator LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016 LT1394 UltraFast Single Supply Comparator 7ns, 6mA Single Supply Comparator LT1720 UltraFast Dual Single Supply Comparator Dual 4.5ns, 4mA Single Supply Comparator UltraFast is a trademark of Linear Technology Corporation. 12 Linear Technology Corporation 1671fs, sn1671 LT/TP 0499 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998