X40030, X40031, X40034, X40035 ® Data Sheet PRELIMINARY April 28, 2005 Triple Voltage Monitor with Integrated CPU Supervisor FN8114.0 • Industrial Systems —Process Control —Intelligent Instrumentation • Computer Systems —Computers —Network Servers FEATURES • Triple voltage detection and reset assertion —Standard reset threshold settings See selection table on page 2. —Adjust low voltage reset threshold voltages using special programming sequence —Reset signal valid to VCC = 1V —Monitor three seperate voltages • Fault detection register • Selectable power on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) • Selectable watchdog timer interval (25ms, 200ms, 1.4s or off) • Debounced manual reset input • Low power CMOS —25µA typical standby current, watchdog on —6µA typical standby current, watchdog off • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages —14-lead SOIC, TSSOP • Monitor Voltages: 5V to 0.9V • Independent Core Voltage Monitor DESCRIPTION The X40030, X40031, X40034, X40035 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, and manual reset, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/RESET is active until VCC returns to proper operating level and stabilizes. A second and third voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available, however, Intersil’s unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet specific system level requirements or to fine-tune the threshold for applica- APPLICATIONS • Communication Equipment —Routers, Hubs, Switches —Disk arrays, Network Storage BLOCK DIAGRAM + V3MON V3 Monitor Logic - VTRIP3 V2 Monitor Logic WP SCL VCC or V2MON* + V2MON SDA V3FAIL Fault Detection Register Data Register WDO MR + VCC VCC Monitor Logic 1 Watchdog and Reset Logic Status Register Command Decode Test & Control Logic (V1MON) V2FAIL VTRIP2 - VTRIP1 - Power on, Manual Reset Low Voltage Reset Generation RESET X40030/34 RESET X40031/35 LOWLINE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X40030, X40031, X40034, X40035 A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. Device Expected System Voltages Vtrip1 (V) Vtrip2 (V) Vtrip3 (V) POR (system) X40030, X40031 -A -B -C 5V; 3V or3.3V; 1.8V 5V; 3V; 1.8V 3.3V; 2.5V; 1.8V 2.0-4.75* 4.55-4.65* 4.35-4.45* 2.95-3.05* 1.70-4.75 2.85-2.95 2.55-2.65 2.15-2.25 1.70-4.75 1.65-1.75 1.65-1.75 1.65-1.75 RESET = X40030 RESET = X40031 X40034, X40035 -A -B -C 5V; 3.3V; 1.5V 5V; 3V or 3.3V; 1.5V 5V; 3V or 3.3V; 1.2V 2.0-4.75* 4.55-4.65* 4.55-4.65* 4.55-4.65* 0.90-3.50 1.25-1.35 1.25-1.35 0.95-1.05 1.70-4.75 3.05-3.15 2.85-2.95 2.85-2.95 RESET = X40030 RESET = X40031 *Voltage monitor requires VCC to operate. Others are independent of VCC PIN CONFIGURATION X40031, X40035 14-Pin SOIC, TSSOP X40030, X40034 14-Pin SOIC, TSSOP V2FAIL V2MON LOWLINE NC MR RESET VSS 1 2 3 4 14 13 12 11 5 6 7 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA V2FAIL V2MON LOWLINE NC MR RESET VSS 1 2 3 4 14 13 12 11 5 6 7 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA PIN DESCRIPTION Pin Name Function 1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin. 2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input (X40034, X40035). 3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4 NC No connect. 5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. 6 RESET/ RESET RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power up. It will also stay active until manual reset is released and for tPURST thereafter. 2 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 PIN DESCRIPTION (Continued) Pin Name Function 7 VSS Ground 8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers). It has an internal pull down resistor. (>10MΩ typical) 11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. Connect V3MON to VSS or VCC when not used. The V3MON comparator is supplied by the V3MON input. 12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin. 13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog timer goes active. 14 VCC Supply Voltage. PRINCIPLES OF OPERATION Manual Reset Power On Reset By connecting a push-button directly from MR to ground, the designer adds manual system reset capability. The MR pin is LOW while the push-button is closed and RESET/RESET pin remains HIGH/LOW until the push-button is released and for tPURST thereafter. Applying power to the X40030, X40031, X40034, X40035 activates a Power On Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – It allows time for an FPGA to download its configuration prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40031, X40035) and RESET (X40030, X40034) pin allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button X40030/34 System Reset VCC RESET MR Manual Reset 3 Low Voltage VCC (V1 Monitoring) During operation, the X40030, X40031, X40034, X40035 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP1. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP1 for tPURST. Low Voltage V2 Monitoring The X40030 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. For the X40030 and X40031 the V2FAIL signal remains active until the V2MON drops below 1V (V2MON falling). It also remains active until V2MON FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Figure 2. Two Uses of Multiple Voltage Monitoring returns and exceeds VTRIP2.This voltage sense circuitry monitors the power supply connected to V2MON pin. If VCC = 0, V2MON can still be monitored. VCC For the X40034 and X40035, the V2FAIL signal remains active until VCC drops below 1V and remains active until V2MON returns and exceeds VTRIP2.This sense circuitry is powered by VCC. If VCC = 0, V2MON cannot be monitored. X40031-A 6-10V 5V V3MON (1.7V) V3FAIL 390K The X40030, X40031, X40034, X40035 also monitors a third voltage level and asserts V3FAIL if the voltage falls below a preset minimum VTRIP3. The V3FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. The V3FAIL signal remains active until the V3MON drops below 1V (V3MON falling). It also remains active until V3MON returns and exceeds VTRIP3. RESET V2MON V2FAIL 3.3V 1M Low Voltage V3 Monitoring VCC System Reset Power Fail Interrupt VCC X40031-B Unreg. Supply 5V Reg VCC 3.0V Reg RESET V2MON System Reset V2FAIL This voltage sense circuitry monitors the power supply connected to V3MON pin. If VCC = 0, V3MON can still be monitored. 1.8V Reg V3MON V3FAIL Notice: No external components required to monitor three voltages. Early Low VCC Detection (LOWLINE) This CMOS output goes LOW earlier than RESET/RESET whenever VCC falls below the VTRIP1 voltage and returns high when VCC exceeds the VTRIP1 voltage. There is no power up delay circuitry (tPURST) on this pin. Figure 3. VTRIPX Set/Reset Conditions VTRIPX (X = 1, 2, 3) VCC/V2MON/V3MON VP WDO SCL 7 0 0 7 0 7 SDA 00h A0h 4 tWC FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the WDO signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40030, X40031, X40034, X40035 control register (also refer to page 21). CASE A Now if the desired VTRIPX is greater than the VTRIPX (actual), then add the difference between VTRIPX (desired) – VTRIPX (actual) to the original VTRIPX desired. This is your new VTRIPX that should be applied to VXMON and the whole sequence should be repeated again (see Figure 5). Figure 4. Watchdog Restart .6µs A0h, followed by the Byte Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. To check if the VTRIPX has been set, set VXMON to a value slightly greater than VTRIPX (that was previously set). Slowly ramp down VXMON and observe when the corresponding outputs (LOWLINE, V2FAIL and V3FAIL) switch. The voltage at which this occurs is the VTRIPX (actual). 1.3µs SCL SDA CASE B Start WDT Reset Stop V1, V2 AND V3 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40030 is shipped with standard V1, V2 and V3 threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40030, X40031, X40034, X40035 trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting a VTRIPx Voltage (x=1, 2, 3) There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to “reset” the VTRIPx voltage before setting the new value. Setting a Higher VTRIPx Voltage (x=1, 2, 3) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin (Vcc(V1MON), V2MON or V3MON). Then, a programming voltage (Vp) must be applied to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address 5 Now if the VTRIPX (actual), is higher than the VTRIPX (desired), perform the reset sequence as described in the next section. The new VTRIPX voltage to be applied to VXMON will now be: VTRIPX (desired) – (VTRIPX (actual) – VTRIPX (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIPx Voltage (x=1, 2, 3) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be “reset” according to the procedure described below. Once VTRIPx has been “reset”, then VTRIPx can be set to the desired voltage using the procedure described in “Setting a Higher VTRIPx Voltage”. Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser. Notes: 1.This operation does not corrupt the memory array. 2. Set VCC ≅ 1.5(V2MON or V3MON), when setting VTRIP2 or VTRIP3 respectively FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0 and BP. The X40030, X40031, X40034, X40035 will not acknowledge any data bytes written after the first byte is entered. CONTROL REGISTER The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The state of the Control Register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 7. 7 6 5 PUP1 WD1 WD0 4 3 BP 0 2 1 0 RWEL WEL PUP0 RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. Figure 5. Sample VTRIP Reset Circuit VP Adjust V2FAIL RESET VTRIP1 Adj. 1 6 13 X40030 2 9 7 VTRIP2 Adj. 6 µC 14 8 Run SCL SDA FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3) Vx = VCC, VxMON Note: X = 1, 2, 3 Let: MDE = Maximum Desired Error VTRIPX Programming No Desired VTRIPX< Present Value MDE+ Acceptable Desired Value YES Error Range Execute VTRIPX Reset Sequence MDE– Error = Actual - Desired Set VX = desired VTRIPX New VX applied = Old VX applied + | Error | Execute Set Higher VX Sequence New VX applied = Old VX applied - | Error | Apply VCC and Voltage > Desired VTRIPX to VX Execute Reset VTRIPX Sequence NO Decrease VX Output Switches? YES Error < MDE– Error > MDE+ Actual VTRIPX Desired VTRIPX | Error | < | MDE | DONE WEL: Write Enable Latch (Volatile) PUP1, PUP0: Power Up Bits (Nonvolatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. The Power Up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power up times are shown in the following table. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. 7 PUP1 PUP0 Power on Reset Delay (tPURST) 0 0 50ms 0 1 200ms (factory setting) 1 0 400ms 1 1 800ms FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 200 milliseconds 1 0 25 milliseconds 1 1 disabled (factory setting) – A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, or power cycling the device or attempting a write to a write protected block. Writing to the Control Registers To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: Notes: 1. tPURST is set to 200ms as factory default. – Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). – Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). – Write one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s is the BP bit and qr are the power up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. 8 2. Watch Dog Timer bits are shipped disabled. FAULT DETECTION REGISTER (FDR) The Fault Detection Register provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile 7 LV1F 6 5 4 LV2F LV3F WDF 3 2 1 0 MRF 0 0 0 The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR. FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Figure 7. Valid Data Changes on the SDA Bus SCL SDA Data Stable Data Change At power-up, the FDR is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring can take place. In the event of any one of the monitored sources fail. The corresponding bit in the register will change from a “1” to a “0” to indicate the failure. At this moment, the system should perform a read to the register and note the cause of the reset. After reading the register the system should reset the register back to all “1” again. The state of the FDR can be read at any time by performing a random read at address 0FFh, using the special preamble. The FDR can be read by performing a random read at 0FFh address of the register at any time. Only one byte of data is read by the register read operation. Data Stable SERIAL INTERFACE Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data The MRF bit will be set to “0” when Manual Reset input goes active. Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 7. WDF, Watchdog Timer Fail Bit (Volatile) Serial Start Condition The WDF bit will be set to “0” when the WDO goes active. All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 8. MRF, Manual Reset Fail Bit (Volatile) LV1F, Low VCC Reset Fail Bit (Volatile) The LV1F bit will be set to “0” when VCC (V1MON) falls below VTRIP1. LV2F, Low V2MON Reset Fail Bit (Volatile) The LV2F bit will be set to “0” when V2MON falls below VTRIP2. LV3F, Low V3MON Reset Fail Bit (Volatile) The LV3F bit will be set to “0” when the V3MON falls below VTRIP3. 9 Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 8. FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Figure 8. Valid Start and Stop Conditions SCL SDA Start Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 9. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not Stop detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 10. A write to a protected block of memory will supress the acknowledge bit. Figure 9. Acknowledge Response From Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Start 10 Acknowledge FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. dition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 11 for the address, acknowledge, and data transfer sequence. Figure 10. Acknowledge Polling Sequence Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 10. Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK Returned? Serial Read Operations Issue STOP YES Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO YES Read Operation Continue Normal Read or Write Command Sequence Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start con- PROCEED Figure 11. Random Address Read Sequence Signals from the Master SDA Bus Signals from the Slave 11 S t a r t 10 1 10 0 S t a r t Byte Address Slave Address 0 1 1 1 11 11 1 1 A C K S t o p Slave Address A C K A C K Data FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 SERIAL DEVICE ADDRESSING Word Address Slave Address Byte The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power up condition. Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: Operational Notes – a device type identifier that is always ‘1011’. – one bit (AS) that provides the device select bit. AS bit is set-to “0” as factory default. The device powers-up in the following state: – The device is in the low power standby state. – next bit is ‘0’. – The WEL bit is set to ‘0’. In this state it is not possible to write to the device. Figure 12. X40030, X40031, X40034, X40035 Addressing – SDA pin is the input mode. – RESET/RESET Signal is active for tPURST. Slave Byte Control Register 1 0 1 1 0 0 1 R/W Data Protection Fault Detection Register 1 0 1 1 0 0 0 R/W The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow write operations. Word Address Control Register 1 1 1 1 1 1 1 1 Fault Detection Register 1 1 1 1 1 1 1 1 – last bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. 12 – The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. – A three step sequence is required before writing into the Control Register to change Watchdog Timer or Block Lock settings. – The WP pin, when held HIGH, prevents all writes to the array and all the Register. FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Chip Supply Voltage Moitored* Voltages Commercial 0°C 70°C Version Industrial -40°C +85°C X40030, X40031 2.7V to 5.5V 1.7V to 5.5V X40034, X40035 2.7V to 5.5V 1.0V to 5.5V *See Ordering Info D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter Min. Typ.(4) Max. Unit Active Supply Current (VCC) Read 1.5 mA Active Supply Current (VCC) Write 3.0 mA 6 10 µA VIL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz 25 30 µA VSDA = VSCL = VCC Others = GND or VCC ICC1(1) ICC2(1) ISB1(1) Standby Current (VCC) AC (WDT off) ISB2(2) Standby Current (VCC) DC (WDT on) Test Conditions VIL = VCC x 0.1 VIH = VCC x 0.9, fSCL = 400kHz ILI Input Leakage Current (SCL, MR, WP) 10 µA VIL = GND to VCC ILO Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, RESET) 10 µA VSDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage (SDA, SCL, MR, WP) -0.5 VCC x 0.3 V (3) Input HIGH Voltage (SDA, SCL, MR, WP) VCC x 0.7 VCC + 0.5 V Schmitt Trigger Input Hysteresis • Fixed input level • VCC related level 0.2 .05 x VCC VIH VHYS (6) VOL Output LOW Voltage (SDA, RESET/RESET, LOWLINE, V2FAIL, V3FAIL, WDO) VOH Output (RESET, LOWLINE) HIGH Voltage V V 0.4 VCC – 0.8 VCC – 0.4 V IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.7-3.6V) V IOH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.7-3.6V) VCC Supply VTRIP1(5) VCC Trip Point Voltage Range 2.0 4.75 V 4.55 4.6 4.65 V X40030, X40031-A, X40034, X40035 4.35 4.4 4.45 V X40030, X40031-B 2.85 2.9 2.95 V X40030, X40031-C 15 µA Second Supply Monitor IV2 V2MON Current 13 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol VTRIP2 (5) tRPD2(6) Parameter Min. V2MON Trip Point Voltage Range Typ.(4) 1.7 0.9 Max. Unit Test Conditions 4.75 3.5 V V X40030, X40031 X40034, X40035 2.85 2.9 2.95 V X40030, X40031-A 2.55 2.6 2.65 V X40030, X40031-B 2.15 2.2 2.25 V X40030, X40031-C 1.25 1.3 1.35 V X40034, X40035-A&B 0.95 1.0 1.05 V X40034, X40035-C 5 µs 15 µA 4.75 V VTRIP2 to V2FAIL Third Supply Monitor IV3 VTRIP3(5) tRPD3(6) V3MON Current V3MON Trip Point Voltage Range 1.7 1.65 1.7 1.75 V X40030, X40031 3.05 3.1 3.15 V X40034, X40035-A 2.85 2.9 2.95 V X40034, X40035-B&C 5 µs VTRIP3 to V3FAIL Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) VIL Min. and VIH Max. are for reference only and are not tested. (4) At 25°C, VCC = 3V (5) See ordering information for standard programming levels. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3) R ∆V Vref VxMON + C VREF ∆V = 100mV Output Pin – tRPDX = 5µs worst case CAPACITANCE Symbol COUT(1) CIN(1) Note: Parameter Max. Unit Test Conditions Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO) 8 pF VOUT = 0V Input Capacitance (SCL, WP, MR) 6 pF VIN = 0V (1) This parameter is not 100% tested. 14 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V VCC 5V V2MON, V3MON RESET WDO SDA 4.6kΩ 4.6kΩ 2.06kΩ 30pF SYMBOL TABLE V2FAIL, V3FAIL 30pF 30pF A.C. TEST CONDITIONS Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC x 0.5 Output load Standard output load WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance A.C. CHARACTERISTICS Symbol fSCL Parameter Min. SCL Clock Frequency Max. Unit 400 kHz tIN Pulse width Suppression Time at inputs 50 tAA SCL LOW to SDA Data Out Valid 0.1 tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs Data Output Hold Time 50 ns tDH tR tF SDA and SCL Rise Time SDA and SCL Fall Time 300 ns 20 +.1Cb(1) 300 ns 0.6 tHD:WP WP Hold Time 0 Note: µs 20 WP Setup Time Capacitive load for each bus line 0.9 +.1Cb(1) tSU:WP Cb ns µs µs 400 pF (1) Cb = total capacitance of one bus line in pF 15 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 TIMING DIAGRAMS Bus Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA IN tSU:STO tAA tDH tBUF SDA OUT WP Pin Timing START SCL Clk 1 Clk 9 Slave Address Byte SDA IN tSU:WP tHD:WP WP Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition Nonvolatile Write Cycle Timing Symbol tWC Note: Parameter (1) Write Cycle Time Min. Typ. Max. Unit 5 10 ms (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 16 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 Power Fail Timings VTRIPX [ [ tRPDL VCC tRPDX V2MON or [ [ V3MON LOWLINE or tRPDL tRPDX tRPDL tRPDX tF tR V2FAIL or VRVALID V3FAIL X = 2, 3 RESET/RESET/MR Timings VTRIP1 VCC tPURST tPURST tRPD1 tF tR RESET VRVALID RESET MR tMD tIN1 17 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol (2) tRPD1 tRPDL t LR tRPDX (2) tPURST Parameters Min. Typ.(1) VTRIP1 to RESET/RESET (Power down only) VTRIP1 to LOWLINE LOWLINE to RESET/RESET delay (Power down only) [= tRPD1-tRPDL] Max. Unit 5 µs 500 VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) ns 5 Power On Reset delay: PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) PUP1=1, PUP0=0 PUP1=1, PUP0=1 µs 50(2) 200 400(2) 800(2) ms ms ms ms tF VCC, V2MON, V3MON, Fall Time 20 mV/µs tR VCC, V2MON, V3MON, Rise Time 20 mV/µs Reset Valid VCC 1 V 500 ns 5 µs VRVALID tMD MR to RESET/ RESET delay (activation only) tin1 Pulse width for MR tWDO Watchdog Timer Period: WD1=0, WD0=0 WD1=0, WD0=1 WD1=1, WD0=0 WD1 = 1, WD0 = 1 (factory setting) 1.4(2) 200(2) 25 OFF s ms ms tRST1 Watchdog Reset Time Out Delay WD1=0, WD0=0 WD1=0, WD0=1 100 200 300 ms tRST2 Watchdog Reset Time Out Delay WD1=1, WD0=0 12.5 25 37.5 ms tRSP Watchdog timer restart pulse width 1 Notes: (1) VCC = 5V at 25°C. µs (2) Values based on characterization data only. Watchdog Time Out For 2-Wire Interface Start Clockin (0 or 1) tRSP Start < tWDO SCL SDA tRST tWDO tRST WDO Start WDT Restart Minimum Sequence to Reset WDT SCL SDA 18 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 VTRIPX Set/Reset Conditions VCC/V2MON/V3MON (VTRIPX) tTHD VP tTSU WDO tVPS tVPH SCL 7 0 0 7 0 tVPO 7 * SDA 00h A0h tWC Start 01h* sets VTRIP1 09h* sets VTRIP2 0Dh* sets VTRIP3 03h* 0Bh* 0Fh* resets VTRIP1 resets VTRIP2 resets VTRIP3 * all others reserved VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0–5.5V; Temperature = 25°C Parameter Description Min. Max. Unit tVPS WDO Program Voltage Setup time 10 µs tVPH WDO Program Voltage Hold time 10 µs tTSU VTRIPX Level Setup time 10 µs tTHD VTRIPX Level Hold (stable) time 10 µs tWC VTRIPX Program Cycle 10 ms tVPO Program Voltage Off time before next cycle 1 ms Programming Voltage 15 18 V VTRAN1 VTRIP1 Set Voltage Range 2.0 4.75 V VTRAN2 VTRIP2 Set Voltage Range - X40030, X40031 1.7 4.75 V VTRAN2A VTRIP2 Set Voltage Range - X40034, X40035 0.9 3.5 V VTRAN3 VTRIP3 Set Voltage Range 1.7 4.75 V Vtv VTRIPX Set Voltage variation after programming (-40 to +85°C). -25 +25 mV tVPS WDO Program Voltage Setup time 10 VP 19 µs FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 FN8114.0 April 28, 2005 X40030, X40031, X40034, X40035 ORDERING INFORMATION Monitored VCC Range 1.7-5.5 VTRIP1 Range VTRIP2 Range VTRIP3 Range 4.6V±50mV 2.9V±50mV 1.7V±50mV Package Operating Temperature Range Part Number with RESET Part Number with RESET 14L SOIC 0oC–70oC X40030S14-A X40031S14-A -40oC–85oC X40030S14I-A X40031S14I-A 0oC–70oC X40030V14-A X40031V14-A -40oC–85oC X40030V14I-A X40031V14I-A 14L TSSOP 1.7-5.5 4.4V±50mV 2.6V±50mV 1.7V±50mV 14L SOIC 14L TSSOP 1.7-3.6 2.9V±50mV 2.2V±50mV 1.7V±50mV 14L SOIC 14L TSSOP 1.3-5.5 4.6V±50mV 1.3V±50mV 3.1V±50mV 14L SOIC 14L TSSOP 1.3-5.5 4.6V±50mV 1.3V±50mV 2.9V±50mV 14L SOIC 14L TSSOP 1.0-3.6 4.6V±50mV 1.0V±50mV 2.9V±50mV 14L SOIC 14L TSSOP 0oC–70oC X40030S14-B X40031S14-B -40oC–85oC X40030S14I-B X40031S14I-B 0oC–70oC X40030V14-B X40031V14-B -40oC–85oC X40030V14I-B X40031V14I-B 0oC–70oC X40030S14-C X40031S14-C -40oC–85oC X40030S14I-C X40031S14I-C 0oC–70oC X40030V14-C X40031V14-C -40oC–85oC X40030V14I-C X40031V14I-C 0oC–70oC X40030S14-A X40031S14-A -40oC–85oC X40030S14I-A X40031S14I-A 0oC–70oC X40030V14-A X40031V14-A -40oC–85oC X40030V14I-A X40031V14I-A 0oC–70oC X40030S14-B X40031S14-B -40oC–85oC X40030S14I-B X40031S14I-B 0oC–70oC X40030V14-B X40031V14-B -40oC–85oC X40030V14I-B X40031V14I-B 0oC–70oC X40030S14-C X40031S14-C -40oC–85oC X40030S14I-C X40031S14I-C 0oC–70oC X40030V14-C X40031V14-C -40oC–85oC X40030V14I-C X40031V14I-C PART MARK INFORMATION 14-Lead Package 0/1/4/5 X4043XX YYWWXX Package - S/V A, B, or C I – Industrial Blank – Commercial WW – Workweek YY – Year All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8114.0 April 28, 2005