Factsheet

EEPROM 1x8
C35 – Memory IP – NVM
Key Parameter
Functional Block Diagram
1x8 = 8bit
• Number of Pages
1
• In/Out Bus Width
8bit
• Supply Voltage Write
2.7V to 5.5V
• Supply Voltage Read
2.7V to 5.5V
• Typ. Read Current
200µA @ 1MHz
• Typ. Write Current
125µA
• Write Time
6ms
• Read Access Time
200ns
• Block Area
0.24mm
Address Decoder
Control
Logic
• Bits Organization
Charge Pump
Memory Array
8bit
DataIO / Sense Amplifier
2
Process Characteristics
Block Features
• Fabrication Process
0.35µm (C35EE)
• Fixed memory building block
• Process Option
EEPROM midox
• Fully static RAM operation
• Storage Element
SimpleEE
• Fully differential sense amplifier
• Temperature Range
-40˚C to 125˚C
• Synchronous I/O interface
• Data Retention
20years at 125˚C
• Write Cycles
100k cycles at 125˚C
General Description
The IP-block represents a non-volatile memory (NVM) device using a SimpleEE floating gate bit
cell, intended for use in embedded micro controller systems. The movement of the charge in and
out of the floating gate is done by the Fowler-Nordheim tunneling mechanism.
Access to the IP-block is similar to a static RAM, except the write access, which is more time
consuming. To speed up write operations, the memory core is organized in 1 page with 1 column of
8bit each, where each write operation addresses one page.
The voltage required to program and to erase the memory cell is in the range of 14V, which is
internally generated by an integrated Charge Pump.
A DataIO block with integrated Sense Amplifier together with the Address Decoder, Charge Pump
and the Memory Array is managed by the Control Logic block. Special test modes for NVM bit cell
screening are implemented and executed in the production test flow in order to ensure reliability of
the NVM.
The device is optimized for low power operation by shutting down the sense amplifier after sensing
the state of the bit cells.
For further information and requests, e-mail us at: [email protected]
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Disclaimer: This information is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited
to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
Memory IP Factsheet
www.ams.com
[v1-00] 2014-May