L DESIGN FEATURES Improve Hot Swap Performance and Save Design Time with Hot Swap Controller that Integrates 2A MOSFET and Sense Resistor by David Soo Introduction components or easily adjusted using resistors and capacitors to better suit a large range of applications. The part is able to cover a wide 2.9V to 26.5V voltage range and includes a temperature and current monitor. The MOSFET is kept in the safe-operating–area (SOA) by using a time-limited foldback current limit and overtemperature protection. The LTC4217 can be easily applied in its basic configuration, or, with a few additional external components, set up for applications with special requirements. Monitoring the MOSFET The LTC4217 features MOSFET current and temperature monitoring. The current monitor outputs a current proportional to the MOSFET current, while a voltage proportional to the MOSFET temperature is available. This allows external circuits to predict possible failure and shutdown the system. The current in the MOSFET passes through a sense resistor, and the voltage on the sense resistor is converted to a current that is sourced out the IMON pin. The gain is 50µA from IMON for 1A of MOSFET current. The output current can be converted to a voltage using an external resistor to drive a VDD 12V OUT 12V UV AUTO RETRY LTC4217DHC-12 FLT + VOUT 12V 330µF 1.5A 10k PG TIMER INTVCC 0.1µF GND IMON ADC 20k Figure 2. 12V, 1.5A card resident application 16 0.9 0.8 0.7 VISET (V) The LTC4217 Hot Swap controller turns a board’s supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. No surprise there, this is generally what Hot Swap controllers do, but the LTC4217 has a feature that gives it an advantage over other Hot Swap controllers. It simplifies the design of Hot Swap systems by integrating the controller, MOSFET and sense resistor in a single IC. This saves significant design time that would otherwise be spent choosing an optimum controller/MOSFET combination, setting current limits, and carefully designing a layout that protects the MOSFET from excessive power dissipation. One significant advantage of an integrated solution over discrete solutions is that the current limit accuracy is well known. In discrete solutions, the overall precision of the current limit is a function of adding the tolerances of contributing components, while in the LTC4217, it appears as a single 2A specification. The integrated solution also simplifies layout issues by optimizing MOSFET and sense resistor connections. The inrush current, current limit threshold and timeout can be set to default values with no external 0.6 0.5 0.4 0.3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 1. VISET vs temperature comparator or ADC. The voltage compliance for the IMON pin is from 0V to (INTVCC – 0.7V). The MOSFET temperature corresponds linearly to the voltage on the ISET pin, with the temperature profile shown in Figure 1. The open circuit voltage on this pin at room temperature is 0.63V. In addition, the overtemperature shutdown circuit turns off the MOSFET when the controller die temperature exceeds 145°C, and turns it on again when the temperature drops to 125°C. 12V Application Figure 2 shows the LTC4217-12 in a 12V Hot Swap application with default settings. The only external component required is the capacitor on the INTVCC pin. The current limit, inrush current control, and protection timer are internally set at levels that protect the integrated MOSFET. The input voltage monitors are preset for a 12V supply using internal resistive dividers from the VDD supply to drive the UV and OV pins. The UV condition occurs when VDD falls below 9.23V; OV when VDD exceeds 15.05V. The LTC4217 turns a board’s supply voltage on and off in a controlled Linear Technology Magazine • June 2009 DESIGN FEATURES L VDD + 6.15 CURRENT LIMIT VALUE (A) 2.5 GATE SLOPE = 0.3V/ms OUT VDD 2.0 1.5 1.0 0.5 0 t1 t2 Figure 3. Supply turn-on manner, allowing the board to be safely inserted and removed from a live backplane. Several conditions must be present before the internal MOSFET can be turned on. First the VDD supply exceeds its 2.73V undervoltage lockout level and the internally generated INTVCC crosses 2.65V. Next the UV and OV pins must indicate that the input power is within the acceptable range. These conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during the insertion has ended. The MOSFET is then turned on by a controlled 0.3V/ms gate ramp as shown in Figure 3. The voltage ramp of the output capacitor follows the slope of the gate ramp thereby setting the supply inrush current at: To reduce inrush current further, use a shallower voltage ramp than the default 0.3V/ms by adding a ramp VDD 12V 150k LTC4217FE GATE FLT 330µF 20k 1k OV 20k + FB UV 224k VOUT 12V 0.8A OUT 140k 0.1µF 20k 12V 10k PG ISET 20k TIMER 0.47µF INTVCC 0.1µF GND IMON ADC 20k Figure 5. 0.8A, 12V card resident applicaiton Linear Technology Magazine • June 2009 0.2 0.4 0.6 0.8 FB VOLTAGE (V) 1.0 1.2 Figure 4. Current limit threshold foldback capacitor (with a 1k series resistor) from gate to ground. As OUT approaches the VDD supply, the powergood indicator (PG) becomes active. The definition of power good is the voltage on the FB pin exceeds 1.235V while the GATE pin is high. The FB pin monitors the output voltage via an internal resistive divider from the OUT pin. Once the OUT voltage crosses the 10.5V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin ceases to pull low and indicates that the power is good. Once OUT reaches the VDD supply, the GATE ramps until clamped at 6.15V above OUT. The LTC4217 features an adjustable current limit with foldback that protects against short circuits or excessive load current. The default current limit is 2A and can be adjusted lower by placing a resistor between the ISET pin and ground. To prevent excessive power dissipation in the switch during active current limit, the available current is reduced as a function IINRUSH = CL • (0.3V/ms) 0 of the output voltage sensed by the FB pin as shown in Figure 4. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the delay set by the timer. Tying the TIMER pin to INTVCC configures the part to use a preset 2ms overcurrent time-out and a 100ms cool-down time. After the 100ms cool-down, the switch is allowed to turn on again if the overcurrent fault has been cleared. Bringing the UV pin below 0.6V and then high clears the fault. Tying the FLT pin to the UV pin allows the part to self-clear the fault and turn on again after the 100ms cool-down. Programmable Features The LTC4217 application shown in Figure 5 demonstrates the adjustable features. The UV and OV resistive dividers set undervoltage and overvoltage turnoff thresholds while the FB divider determines the power good trip point. The R-C network on the GATE pin decreases the gate ramp to 0.24V/ms from the default 0.3V/ms to reduce the inrush current. The 20k ISET resistor forms a resistive divider with an internal 20k resistor to reduce the current limit threshold (before foldback) to onehalf of the original threshold for a 1A current limit. The graph in Figure 6 shows the current limit threshold as the ISET resistor varies. As in the previous application, the UV and FLT signals are tied together so that the part auto-retries turn-on following shutdown for an overcurrent fault. continued on page 25 17 DESIGN FEATURES L for the LT3582-5 or LT3582-12, it does permit reading of the chip’s configuration and the ability to disable the power switches through the interface. Additional I 2C functionality is available with the LT3582 including re-programmability of the output voltages, and setting the power up sequencing and power down discharge. L1 1.5µH D1 INPUT 2.7V TO 4.2V VIN SWN SWP CAPP VOUTN I2C INTERFACE CAPP SDA VOUTP SCL VPP CA REG0/OTP0 = 1Ch REG1/OTP1 = 4Ch REG2/OTP2 = 07h C4 10µF RAMPP RAMPN C5 10nF C6 10nF VPOS 4.6V 100mA C3 10µF 300 250 70 200 60 150 50 100 40 30 POWER LOSS (mW) LT3582 VNEG –5V 90mA C1 10µF D2 350 VIN = 3.3V 80 L2 1.5µH GND C2 10µF The LT3582 is an easy-to-use compact solution for DC/DC converter applications where positive and negative outputs are required. It is accurate, efficient and includes an outsized number of features for its diminutive 3mm × 3mm 16-pin QFN package. It is offered in ±5V (LT3582-5), ±12V (LT3582-12) and I2C-programmable (LT3582) output versions. L 90 SHDN EFFICIENCY (%) SWN Conclusion A default power-up configuration can be made permanent in the LT3582 through the One-Time-Programmable memory. The chip will always use the default configuration from OTP memory upon power-up. Unless locked by programming a specific OTP memory bit, the chip configuration can be changed after power-up by writing new settings through the I2C interface. 50 0.1 D1-D2: PANASONIC M21D3800L LOW VF SCHOTTKY L1-L2: TDK MLP3216S1R5L C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805 C5-C6: 0402 X5R 1 10 LOAD CURRENT (mA) 0 100 Figure 11. Tiny AMOLED power supply is 0.8mm (max) thin LTC4217, continued from page 17 This example places a 20k resistor on the IMON pin to set the gain of the current monitor output to 1V per amp of MOSFET current. Instead of tying the TIMER pin to the INTVCC pin for a default 2ms overcurrent timeout, an external 0.47µF capacitor is used to set a 5.7ms timeout. During an overcurrent event the external timing capacitor is charged with a100µA pull-up current. If the voltage on the capacitor reaches the 1.2V threshold, the MOSFET turns off. The equation for setting timing capacitor’s value is as follows: CT = TCB • 0.083(µF/ms) While the MOSFET is cooling off, the LTC4217 discharges the timing capacitor. When the capacitor voltage reaches 0.2V an internal 100ms timer is started. Following this cool down period the fault is cleared (when using auto-retry) and the MOSFET is allowed to turn on again. It is important to consider the safe operating area of the MOSFET when 10 2.0 1 1ms 1.5 ID (A) CURRENT LIMIT THRESHOLD VALUE (A) 2.5 1.0 10ms 0.5 0 100ms 0.1 1k 10k 100k RSET (Ω) 1M 10M Figure 6. Current limit adjustment Linear Technology Magazine • June 2009 0.01 1s 10s DC TA = 25°C MULTIPLE PULSE DUTY CYCLE = 0.2 0.1 1 10 VDS (V) Figure 7. MOSFET SOA curve 100 extending the circuit breaker timeout beyond 2ms. The SOA graph for the MOSFET used in LTC4217 is shown in Figure 7. The worse case power dissipation occurs when the voltage versus current profile of the foldback current limit is at maximum. This occurs when the current is 1A and the voltage is one half of the 12V or 6V (see Figure 4, FB pin at 0.7V). In this case the power is 6W, which dictates a maximum time of 100ms (Figure 7, at 6V and 1A). Conclusion The primary role of the LTC4217 is to control hot insertion and provide the electronic circuit breaker function. Additionally the part includes protection of the MOSFET with focus on SOA compliance, thermal protection and precise 2A current limit. It is also adaptable over a large range of applications due to adjustable inrush current, overcurrent fault timer and current limit threshold. A high level of integration makes the LTC4217 easy to use yet versatile. L 25