LTC4217 2A Integrated Hot Swap Controller FEATURES DESCRIPTION n The LTC®4217 is an integrated solution for Hot Swap™ applications that allows a board to be safely inserted and removed from a live backplane. The part integrates a Hot Swap controller, power MOSFET and current sense resistor in a single package for small form factor applications. A dedicated 12V version (LTC4217-12) contains preset 12V specific thresholds, while the standard LTC4217 allows adjustable thresholds. n n n n n n n n n n Small Footprint 33mΩ MOSFET with RSENSE Wide Operating Voltage Range: 2.9V to 26.5V Adjustable, 5% Accurate Current Limit Current and Temperature Monitor Outputs Overtemperature Protection Adjustable Current Limit Timer Before Fault Power Good and Fault Outputs Adjustable Inrush Current Control 2% Accurate Undervoltage and Overvoltage Protection Available in 20-Lead TSSOP and 16-Lead 5mm × 3mm DFN Packages The LTC4217 provides separate inrush current control and a 5% accurate 2A current limit with foldback current limiting. The current limit threshold can be adjusted dynamically using an external pin. Additional features include a current monitor output that amplifies the sense resistor voltage for ground referenced current sensing and a MOSFET temperature monitor output. Thermal limit, overvoltage, undervoltage and power good monitoring are also provided. APPLICATIONS n n n RAID Systems Server I/O Cards Industrial L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Power-Up Waveforms 12V, 1.5A Card Resident Application OUT VDD 12V 12V UV AUTO RETRY LTC4217DHC-12 FLT 0.1μF + VOUT 12V 330μF 1.5A 10k IIN 0.1A/DIV PG TIMER ISET INTVCC IMON GND VIN 10V/DIV VOUT 10V/DIV ADC 20k 4217 TA01a PG 10V/DIV 25ms/DIV 4217 TA01b 4217fc 1 LTC4217 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ................................. –0.3V to 28V Input Voltages FB, OV, UV .............................................. –0.3V to 12V TIMER................................................... –0.3V to 3.5V SENSE .............................VDD – 10V or – 0.3V to VDD Output Voltages ISET, IMON ................................................. –0.3V to 3V PG, FLT .................................................. –0.3V to 35V OUT ............................................ –0.3V to VDD + 0.3V INTVCC .................................................. –0.3V to 3.5V GATE (Note 3) ........................................ –0.3V to 33V Operating Temperature Range LTC4217C ................................................ 0°C to 70°C LTC4217I.............................................. –40°C to 85°C Junction Temperature (Notes 4, 5)........................ 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) FE Package Only ............................................... 300°C PIN CONFIGURATION LTC4217 LTC4217-12 LTC4217 TOP VIEW TOP VIEW SENSE 1 20 SENSE 2 19 VDD VDD 1 16 VDD VDD UV 2 15 ISET UV 3 18 ISET OV 3 14 IMON OV 4 17 IMON TIMER 4 13 FB TIMER 5 12 FLT INTVCC 6 17 SENSE 21 SENSE 16 FB 15 FLT INTVCC 5 GND 6 11 PG GND 7 14 PG OUT 7 10 GATE OUT 8 13 GATE OUT 8 9 OUT 9 12 OUT OUT SENSE 10 DHC PACKAGE 16-LEAD (5mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 17) IS SENSE, θJA = 43°C/W SOLDERED, OTHERWISE θJA = 140°C/W 11 SENSE FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 38°C/W EXPOSED PAD (PIN 21) IS SENSE, θJA = 38°C/W SOLDERED, OTHERWISE θJA = 130°C/W 4217fc 2 LTC4217 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL LTC4217CDHC-12#PBF PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4217CDHC-12#TRPBF 421712 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC4217IDHC-12#PBF LTC4217IDHC-12#TRPBF 421712 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC4217CDHC#PBF LTC4217CDHC#TRPBF 4217 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC4217IDHC#PBF LTC4217IDHC#TRPBF 4217 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC4217CFE#PBF LTC4217CFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP 0°C to 70°C LTC4217IFE#PBF LTC4217IFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4217CDHC-12 LTC4217CDHC-12#TR 421712 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC4217IDHC-12 LTC4217IDHC-12#TR 421712 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC4217CDHC LTC4217CDHC#TR 4217 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C LTC4217IDHC LTC4217IDHC#TR 4217 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C LTC4217CFE LTC4217CFE#TR LTC4217FE 20-Lead Plastic TSSOP 0°C to 70°C LTC4217IFE LTC4217IFE#TR LTC4217FE 20-Lead Plastic TSSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics l VDD Input Supply Range IDD Input Supply Current MOSFET On, No Load l VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l 2.9 26.5 1.6 3 2.65 2.73 2.85 V mA V VDD(UVTH) Input Supply Undervoltage Threshold LTC4217-12, VDD Rising l 9.6 9.88 10.2 V ΔVDD(UVHYST) Input Supply Undervoltage Hysteresis LTC4217-12 l 520 640 760 mV VDD(OVTH) Input Supply Overvoltage Threshold LTC4217-12, VDD Rising l 14.7 15.05 15.4 V ΔVDD(OVHYST) Input Supply Overvoltage Hysteresis LTC4217-12 l 183 244 305 mV VOUT(PGTH) Output Power Good Threshold LTC4217-12, VOUT Rising l 10.2 10.5 10.8 V ΔVOUT(PGHYST) Output Power Good Hysteresis LTC4217-12 l 127 170 213 mV VOUT = VGATE = 0V, VDD = 26.5V VOUT = VGATE = 12V, LTC4217 VOUT = VGATE = 12V, LTC4217-12 l l l 1 50 0 2 70 ±150 4 90 μA μA μA l 0.15 0.3 0.55 V/ms l 15 33 50 mΩ 1.9 2 2.1 A VFB = 1.23V l 1.85 2 2.15 A VFB = 0V l 0.35 0.5 0.7 A VFB = 1.23V, RSET = 20kΩ l 0.85 1 1.17 A IOUT OUT Pin Leakage Current ΔVGATE/Δt GATE Pin Turn-On Ramp Rate RON MOSFET + Sense Resistor On Resistance ILIM(TH) Current Limit Threshold Note 6 VFB = 1.23V 4217fc 3 LTC4217 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN IIN OV, UV, FB Pin Input Current VIN = 1.2V, LTC4217 l RIN OV, UV, FB Pin Input Resistance LTC4217-12 l VIN Rising l TYP MAX UNITS 0 ±1 μA 13 18 23 kΩ Inputs VTH OV, UV, FB Pin Threshold Voltage 1.21 1.235 1.26 ΔVOV(HYST) OV Pin Hysteresis l 10 20 30 mV ΔVUV(HYST) UV Pin Hysteresis l 50 80 110 mV VUV(RTH) UV Pin Reset Threshold Voltage l 0.55 0.62 0.7 V ΔVFB(HYST) FB Pin Power Good Hysteresis l 10 20 30 mV RISET ISET Pin Output Resistor l 19.5 20 20.5 kΩ VUV Falling V Outputs VOL PG, FLT Pin Output Low Voltage IOUT = 2mA l 0.4 0.8 V IOH PG, FLT Pin Input Leakage Current VOUT = 30V l 0 ±10 μA VTIMER(H) TIMER Pin High Threshold VTIMER Rising l 1.2 1.235 1.28 V VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l 0.1 0.21 0.3 V ITIMER(UP) TIMER Pin Pull-Up Current VTIMER = 0V l –80 –100 –120 μA ITIMER(DN) TIMER Pin Pull-Down Current VTIMER = 1.2V l 1.4 2 2.6 μA ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) l 1.6 2 2.7 % 47.5 50 52.5 μA/A 0 ±7.5 μA μA AIMON IMON Pin Current Gain IOUT = 2A l IOFF(IMON) IMON Pin Offset Current IOUT = 132mA l IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l –19 –24 –29 l 190 250 340 IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 μA mA AC Characteristics tPHL(GATE) Input High (OV), Input Low (UV) to Gate Low Propagation Delay VGATE < 16.5V Falling l 8 10 μs tPHL(ILIM) Short-Circuit to Gate Low VFB = 0, Step ISENSE to 1.2A, VGATE < 16.5V Falling l 1 5 μs tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l 50 100 150 ms tD(CB) Circuit Breaker Filter Delay Time (Internal) VFB = 0V, Step ISENSE to 1.2A l 1.5 2 2.7 ms tD(AUTO-RETRY) Auto-Retry Turn-On Delay (Internal) l 50 100 150 ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above OUT. Driving this pin to voltages beyond the clamp may damage the device. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: LTC4217DHC, LTC4217DHC-12: TJ = TA + (PD • 43°C/W) LTC4217FE: TJ = TA + (PD • 38°C/W) Note 6: For the DHC package, switch on-resistance is guaranteed by design and test correlation. 4217fc 4 LTC4217 TYPICAL PERFORMANCE CHARACTERISTICS IDD vs VDD TA = 25°C, VDD = 12V unless otherwise noted. UV Low-High Threshold vs Temperature INTVCC Load Regulation 3.5 1.234 VDD = 5V 3.0 UV LOW-HIGH HRESHOLD (V) 2.0 1.8 2.5 INTVCC (V) 1.6 25°C 1.4 –40°C 2.0 1.5 1.0 1.2 0 0 5 10 15 VDD (V) 20 25 30 0 –2 –4 4217 G01 1.230 1.228 –6 –8 ILOAD (mA) –10 –12 –14 0.08 0.06 –25 50 0 25 TEMPERATURE (°C) 75 –100 –95 –90 –50 –25 50 0 25 TEMPERATURE (°C) 75 4217 G04 1000 100 0 0.2 0.4 0.6 0.8 FB VOLTAGE (V) 1.0 1.2 4217 G07 0.1 2 4 6 8 OUTPUT CURRENT (A) 10 4217 G06 ISET Resistor vs Temperature 22 2.0 1.5 1.0 21 20 19 0.5 0 0 1 0 ISET RESISTOR (kΩ) CURRENT LIMIT THRESHOLD VALUE (A) 0.5 10 100 2.5 1.0 100 4217 G03 Current Limit Adjustment (IOUT vs RSET) 2.5 1.5 75 4217 G05 Current Limit Threshold Foldback 2.0 50 0 25 TEMPERATURE (°C) Current Limit Delay (tPHL(ILIM) vs Overdrive) –105 100 –25 4217 G02 –110 TIMER PULL-UP CURRENT (μA) 0.10 0.04 –50 1.226 –50 Timer Pull-Up Current vs Temperature UV Hysteresis vs Temperature CURRENT LIMIT VALUE (A) 1.232 0.5 1.0 UV HYSTERESIS (V) VDD = 3.3V CURRENT LIMIT PROPAGATION DELAY (μs) IDD (mA) 85°C 1k 10k 100k RSET (Ω) 1M 10M 4217 G08 18 –50 –25 50 0 25 TEMPERATURE (°C) 75 100 4217 G09 4217fc 5 LTC4217 TYPICAL PERFORMANCE CHARACTERISTICS RON vs VDD and Temperature TA = 25°C, VDD = 12V unless otherwise noted. PG, FLT VOUT Low vs ILOAD MOSFET SOA Curve 60 14 10 12 VDD = 3.3V, 12V, 24V 1 1ms ID (A) RON (mΩ) 40 30 20 10ms 100ms 0.1 10 0 –50 –25 50 0 25 TEMPERATURE (°C) 75 TA = 25°C MULTIPLE PULSE DUTY CYCLE = 0.2 0.01 100 50 0 25 TEMPERATURE (°C) –25.0 75 –24.0 –50 100 10 12 4217 G12 6 5 4 3 VDD = 3.3V 2 1 0 –25 50 0 25 TEMPERATURE (°C) 75 0 100 Gate Drive vs Temperature Gate Drive vs VDD 5.6 5.4 5.2 20 25 30 4217 G16 –15 –20 IGATE (μA) –25 –30 4217 G15 0.9 0.8 6.14 0.7 6.13 VISET (V) 5.8 –10 VISET vs Temperature 6.15 GATE DRIVE (VGATE – VSOURCE) (V) 6.2 6.0 –5 4217 G14 4217 G13 15 VDD (V) 6 8 ILOAD (mA) 7 –24.5 10 4 Gate Pull-Up Current vs Gate Drive GATE DRIVE (VGATE – VSOURCE) (V) IGATE PULL-UP (μA) 90 5 2 4217 G11 85 GATE DRIVE (VGATE – VSOURCE) (V) 0 VDD = 12V 95 0 4 100 –25.5 –25 6 2 –26.0 VDD = 3.3V, 12V, 24V ILOAD = 2A FLT 8 GATE Pull-Up Current vs Temperature 100 IMON (μA) 10 VDS (V) IMON vs Temperature and VDD 80 –50 PG 10 0 1 0.1 4217 G10 105 1s 10s DC PG, FLT VOUT LOW (V) 50 6.12 0.6 0.5 6.11 6.10 –50 0.4 –25 50 0 25 TEMPERATURE (°C) 75 100 4217 G17 0.3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4217 G18 4217fc 6 LTC4217 PIN FUNCTIONS FB: Foldback and Power Good Input. Connect this pin to an external resistive divider from OUT for the LTC4217 (adjustable) version. The LTC4217-12 version uses a fixed internal divider with optional external adjustment. Open the pin if the LTC4217-12 thresholds for 12V operation are desired. If the voltage falls below 0.6V, the current limit is reduced using a foldback profile (see the Typical Performance Characteristics section). If the voltage falls below 1.21V, the PG pin will pull low to indicate the power is bad. FLT: Overcurrent Fault Indicator. Open-drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. For overcurrent auto-retry tie to UV pin (see the Applications Information section for details). GATE: Gate Drive for Internal N-channel MOSFET. An internal 24μA current source charges the gate of the N-channel MOSFET. At start-up the GATE pin ramps up at a 0.3V/ms rate determined by internal circuitry. During an undervoltage or overvoltage condition a 250μA pull-down current turns the MOSFET off. During a short-circuit or undervoltage lockout condition, a 140mA pull-down current source between GATE and OUT is activated. GND: Device Ground. IMON: Current Monitor Output. The current in the internal MOSFET switch is divided by 20,000 and sourced from this pin. Placing a 20k resistor from this pin to GND creates a 0V to 2V voltage swing when current ranges from 0A to 2A. INTVCC: Internal 3V Supply Decoupling Output. This pin must have a 0.1μF or larger bypass capacitor. ISET: Current Limit Adjustment Pin. For a 2A current limit value open this pin. This pin is driven by a 20k resistor in series with a voltage source. The pin voltage is used to generate the current limit threshold. The internal 20k resistor and an external resistor between ISET and ground create an attenuator that lowers the current limit value. In order to match the temperature variation of the sense resistor, the voltage on this pin increases at the same rate as the sense resistance increases. Therefore the voltage at ISET pin is proportional to temperature of the MOSFET switch. OUT: Output of Internal MOSFET Switch. Connect this pin directly to the load. In the LTC4217-12 version, the PG comparator monitors an internal resistive divider between the OUT pin and GND. OV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD for the LTC4217 (adjustable) version. The LTC4217-12 version uses a fixed internal divider with optional external adjustment for 12V operation. Open the pin if the LTC4217-12 thresholds are desired. If the voltage at this pin rises above 1.235V, an overvoltage is detected and the switch turns off. Tie to GND if unused. PG: Power Good Indicator. Open-drain output pulls low when the FB pin drops below 1.21V indicating the power is bad. If the FB pin rises above 1.23V and the GATE to OUT voltage exceeds 4.2V, the open-drain pull-down releases the PG pin to go high. SENSE: Current Sense Node and MOSFET Drain. The current limit circuit controls the GATE pin to limit the sense voltage between the VDD and SENSE pins to 15mV (2A) or less depending on the voltage at the FB pin. The exposed pad on DHC and FE packages are connected to SENSE and must be soldered to an electrically isolated printed circuit board trace to properly transfer the heat out of the package. TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/μF duration for current limit before the switch is turned off. If the UV pin is toggled low while the MOSFET switch is off, the switch will turn on again following a cooldown time of 518ms/μF duration. Tie this pin to INTVCC for a fixed 2ms overcurrent delay and 100ms auto-retry time. UV: Undervoltage Comparator Input. Tie high if unused. Connect this pin to an external resistive divider from VDD for the LTC4217 (adjustable) version. The LTC4217-12 version drives the UV pin with an internal resistive divider from VDD. Open the pin if the preset LTC4217-12 thresholds for 12V operation are desired. If the UV pin voltage falls below 1.15V, an undervoltage is detected and the switch turns off. Pulling this pin below 0.62V resets the overcurrent fault and allows the switch to turn back on (see the Applications Information section for details). If overcurrent auto-retry is desired then tie this pin to the FLT pin. VDD: Supply Voltage and Current Sense Input. This pin has an undervoltage lockout threshold of 2.73V. 4217fc 7 LTC4217 FUNCTIONAL DIAGRAM SENSE (EXPOSED PAD) INTERNAL 7.5mΩ SENSE RESISTOR GATE INTERNAL 25mΩ MOSFET OUT VDD IMON CLAMP – +– ISET CHARGE PUMP AND GATE DRIVER CS + INRUSH 0.6V POSITIVE TEMPERATURE COEFFICIENT REFERENCE 0.3V/ms 20k X1 OUT FB CM FOLDBACK 0.6V + UV * – UV 20k * 20k * PG – 140k 1.235V 150k + VDD OUT LOGIC 1.235V PG * 0.62V + RST – VDD 224k 0.2V FLT TM1 * INTVCC – + OV 20k + 100μA OV * 1.235V – 2μA + VDD TM2 VDD – 1.235V – 3.1V GEN UVLO1 + – 2.73V INTVCC UVLO2 TIMER 2.65V + 4217 BD *LTC4217-12 (DFN) ONLY GND 4217fc 8 LTC4217 OPERATION The Functional Diagram displays the main circuits of the device. The LTC4217 is designed to turn a board’s supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. The LTC4217 includes a 25mΩ MOSFET and a 7.5mΩ current sense resistor. During normal operation, the charge pump and gate driver turn on the pass MOSFET’s gate to provide power to the load. The inrush current control is accomplished by the INRUSH circuit. This circuit limits the GATE ramp rate to 0.3V/ms and hence controls the voltage ramp rate of the output capacitor. The current sense (CS) amplifier monitors the load current using the voltage sensed across the current sense resistor. The CS amplifier limits the current in the load by reducing the GATE-to-OUT voltage in an active control loop. It is simple to adjust the current limit threshold using the current setting (ISET) pin. This allows a different threshold during other times such as start-up. has cooled and it is safe to turn it on again. It is suitable for many applications to use an internal 2ms overcurrent timer with a 100ms cooldown period. Tying the TIMER pin to INTVCC sets this default timing. The fixed 12V version, LTC4217-12, uses two separate internal dividers from VDD to drive the UV and OV pins. This version also features a divider from OUT to drive the FB pin. The LTC4217-12 is available in the DFN package while the LTC4217 (adjustable version) is in the DFN and TSSOP packages. The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signaled by the PG pin using an open-drain pull-down transistor. A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power, the foldback amplifier reduces the current limit value from 2A to 0.5A in a linear manner as the FB pin drops below 0.6V (see the Typical Performance Characteristics section). The Functional Diagram also shows the monitoring blocks of the LTC4217. The two comparators on the left side include the UV and OV comparators. These comparators determine if the external conditions are valid prior to turning on the MOSFET. But first the undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 3.1V supply (INTVCC) and generate the power up initialization to the logic circuits. If the external conditions remain valid for 100ms the MOSFET is allowed to turn on. If an overcurrent condition persists, the TIMER pin ramps up with a 100μA current source until the pin voltage exceeds 1.2V (comparator TM2). This indicates to the logic that it is time to turn off the pass MOSFET to prevent overheating. At this point the TIMER pin ramps down using the 2μA current source until the voltage drops below 0.2V (Comparator TM1) which tells the logic to start an internal 100ms timer. At this point, the pass transistor Other features include MOSFET current and temperature monitoring. The current monitor (CM) outputs a current proportional to the sense resistor current. This current can drive an external resistor or other circuits for monitoring purposes. A voltage proportional to the MOSFET temperature is output to the ISET pin. The MOSFET temperature allows external circuits to predict failure and shutdown the system. APPLICATIONS INFORMATION The typical LTC4217 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. A complete application circuit is shown in Figure 1. External component selection is discussed in detail in the following sections. Turn-On Sequence Several conditions must be present before the internal pass MOSFET can be turned on. First the supply VDD must exceed its undervoltage lockout level. Next the internally generated supply INTVCC must cross its 2.65V undervoltage threshold. This generates a 25μs power-on-reset pulse which clears the fault register and initializes internal latches. 4217fc 9 LTC4217 APPLICATIONS INFORMATION VDD 12V GATE RGATE 1k FLT OV CL 330μF R6 20k CGATE 0.1μF R4 20k R2 20k + FB UV R1 224k R5 150k LTC4217FE R3 140k VOUT 12V 0.8A OUT 12V R7 10k PG ISET RSET 20k TIMER CT 0.1μF IMON INTVCC C1 0.1μF Adding a capacitor and a 1k series resistor from GATE to ground will lower the inrush current below the default value set by the INRUSH circuit. The GATE is charged with an 24μA current source (when INRUSH circuit is not driving the GATE). The voltage at the GATE pin rises with a slope equal to 24μA/CGATE and the supply inrush current is set at: ADC RMON 20k GND evident from this graph that the power dissipation at 12V, 300mA for 40ms is in the safe region. 4217 F01 IINRUSH = CL CGATE • 24µA Figure 1. 0.8A, 12V Card Resident Application After the power-on-reset pulse, the LTC4217 will go through the following sequence. First, the UV and OV pins must indicate that the input voltage is within the acceptable range. All of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during the insertion has ended. The MOSFET is turned on by charging up the GATE with a charge pump generated current source whose value is adjusted by shunting a portion of the pull-up current to ground. The charging current is controlled by the INRUSH circuit that maintains a constant slope of GATE voltage versus time (Figure 2). The voltage at the GATE pin rises with a slope of 0.3V/ms and the supply inrush current is set at: IINRUSH = CL • (0.3V/ms) This gate slope is designed to charge up a 1000μF capacitor to 12V in 40ms, with an inrush current of 300mA. This allows the inrush current to stay under the current limit threshold (500mA) for capacitors less than 1000μF. Included in the Typical Performance Characteristics section is a graph of the Safe Operating Area for the MOSFET. It is VDD + 6.15 GATE SLOPE = 0.3V/ms When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the OUT voltage follows the GATE voltage as it increases. Once OUT reaches VDD, the GATE will ramp up until clamped by the 6.15V Zener between GATE and OUT. As the OUT voltage rises, so will the FB pin which is monitoring it. Once the FB pin crosses its 1.235V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin will cease to pull low and indicate that the power is good. Parasitic MOSFET Oscillation When the N-channel MOSFET ramps up the output during power-up it operates as a source follower. The source follower configuration may self-oscillate in the range of 25kHz to 300kHz when the load capacitance is less than 10μF, especially if the wiring inductance from the supply to the VDD pin is greater than 3μH. The possibility of oscillation will increase as the load current (during power-up) increases. There are two ways to prevent this type of oscillation. The simplest way is to avoid load capacitances below 10μF. For wiring inductance larger than 20μH, the minimum load capacitance may extend to 100μF. A second choice is to connect an external gate capacitor CP >1.5nF as shown in Figure 3. OUT VDD Turn-Off Sequence t1 t2 Figure 2. Supply Turn-On 4217 F02 The switch can be turned off by a variety of conditions. A normal turn-off is initiated by the UV pin going below its 1.235V threshold. Additionally, several fault conditions will turn off the switch. These include an input overvoltage 4217fc 10 LTC4217 APPLICATIONS INFORMATION LTC4217 GATE CP 2.2nF *OPTIONAL RC TO LOWER INRUSH CURRENT Tying the TIMER pin to INTVCC will force the part to use the internally generated (circuit breaker) delay of 2ms. In either case the FLT pin is pulled low to indicate an overcurrent fault has turned off the pass MOSFET. For a given the circuit breaker time delay, the equation for setting the timing capacitor’s value is as follows: 4217 F03 Figure 3. Compensation for Small CLOAD (OV pin), overcurrent circuit breaker (SENSE pin) or over temperature. Normally the switch is turned off with a 250μA current pulling down the GATE pin to ground. With the switch turned off, the OUT voltage drops which pulls the FB pin below its threshold. PG then pulls low to indicate output power is no longer good. If VDD drops below 2.65V for greater than 5μs or INTVCC drops below 2.5V for greater than 1μs, a fast shutdown of the switch is initiated. The GATE is pulled down with a 170mA current to the OUT pin. Overcurrent Fault The LTC4217 features an adjustable current limit with foldback that protects against short-circuits or excessive load current. To prevent excessive power dissipation in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the FB pin. A graph in the Typical Performance Characteristics curves shows the current limit versus FB voltage. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the timeout delay set by the TIMER. Current limiting begins when the MOSFET current reaches 0.5A to 2A (depending on the foldback). The GATE pin is then brought down with a 140mA GATEto-OUT current. The voltage on the GATE is regulated in order to limit the current to less than 2A. At this point, a circuit breaker time delay starts by charging the external timing capacitor from the TIMER pin with a 100μA pullup current. If the TIMER pin reaches its 1.2V threshold, the internal switch turns off (with a 250μA current from GATE to ground). Included in the Typical Performance Characteristics curves is a graph of the Safe Operating Area for the MOSFET. From this graph one can determine the MOSFET’s maximum time in current limit for a given output power. CT = tCB • 0.083(μF/ms) After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2μA pull-down current. When the TIMER pin reaches its 0.2V threshold, an internal 100ms timer is started. After the 100ms delay, the switch is allowed to turn on again if the overcurrent fault has been cleared. Bringing the UV pin below 0.6V and then high will clear the fault. If the TIMER pin is tied to INTVCC then the switch is allowed to turn on again (after an internal 100ms delay) if the overcurrent fault is cleared. Tying the FLT pin to the UV pin allows the part to selfclear the fault and turn the MOSFET on as soon as TIMER pin has ramped below 0.2V. In this auto-retry mode the LTC4217 repeatedly tries to turn on after an overcurrent at a period determined by the capacitor on the TIMER pin. The auto-retry mode also functions when the TIMER pin is tied to INTVCC. The waveform in Figure 4 shows how the output latches off following a short-circuit. The current in the MOSFET is 0.5A as the timer ramps up. Current Limit Adjustment The default value of the active current limit is 2A. The current limit threshold can be adjusted lower by placing VOUT 10V/DIV IOUT 1A/DIV ΔVGATE 10V/DIV TIMER 2V/DIV 1ms/DIV 4217 F04 Figure 4. Short-Circuit Waveform 4217fc 11 LTC4217 APPLICATIONS INFORMATION a resistor between the ISET pin and ground. As shown in the Functional Diagram the voltage at the ISET pin (via the clamp circuit) sets the CS amplifier’s built-in offset voltage. This offset voltage directly determines the active current limit value. With the ISET pin open, the voltage at the ISET pin is determined by a positive temperature coefficient reference. This voltage is set to 0.618V at room temperature which corresponds to a 2A current limit at room temperature. An external resistor placed between the ISET pin and ground forms a resistive divider with the internal 20k sourcing resistor. The divider acts to lower the voltage at the ISET pin and therefore lower the current limit threshold. The overall current limit threshold precision is reduced to ±16% when using a 20k resistor to halve the threshold. Using a switch (connected to ground) in series with this external resistor allows the active current limit to change only when the switch is closed. This feature can be used when the start-up current exceeds the typical maximum load current. Monitor MOSFET Temperature The voltage at the ISET pin increases linearly with increasing temperature. The temperature profile of the ISET pin is shown in the Typical Performance Characteristics section. Using a comparator or ADC to measure the ISET voltage provides an indicator of the MOSFET temperature. There is an overtemperature circuit in the LTC4217 that monitors an internal voltage similar to the ISET pin voltage. When the die temperature exceeds 145°C the circuit turns off the MOSFET until the temperature drops to 125°C. Monitor MOSFET Current The current in the MOSFET passes through a sense resistor. The voltage on the sense resistor is converted to a current that is sourced out of the IMON pin. The gain of ISENSE amplifier is 50μA/A from IMON for 1A of MOSFET current. This output current can be converted to a voltage using an external resistor to drive a comparator or ADC. The voltage compliance for the IMON pin is from 0V to INTVCC – 0.7V. A microcontroller with a built-in comparator can build a simple integrating single-slope ADC by resetting a capaci- tor that is charged with this current. When the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. The time between resets will indicate the MOSFET current. Monitor OV and UV Faults Protecting the load from an overvoltage condition is the main function of the OV pin. In the LTC4217-12, an internal resistive divider (driving the OV pin) connects to a comparator to turn off the MOSFET when the VDD voltage exceeds 15.05V. If the VDD pin subsequently falls back below 14.8V, the switch will be allowed to turn on immediately. In the LTC4217 the OV pin threshold is 1.23V when rising, and 1.21V when falling out of overvoltage. The UV pin functions as an undervoltage protection pin or as an “ON” pin. In the LTC4217-12 the MOSFET turns off when VDD falls below 9.23V. If the VDD pin subsequently rises above 9.88V for 100ms, the switch will be allowed to turn on again. The LTC4217 UV turn-on/off thresholds are 1.23V (rising) and 1.15V (falling). In the cases of an undervoltage or overvoltage the MOSFET turns off and there is indication on the PG status pin. When the overvoltage is removed the MOSFET’s gate ramps up immediately at the rate determined by the INRUSH block. Power Good Indication In addition to setting the foldback current limit threshold, the FB pin is used to determine a power good condition. The LTC4217-12 uses an internal resistive divider on the OUT pin to drive the FB pin. The PG comparator indicates logic high when OUT pin rises above 10.5V. If the OUT pin subsequently falls below 10.3V the comparator toggles low. On the LTC4217 the PG comparator drives high when the FB pin rises above 1.23V and low when falls below 1.21V. Once the PG comparator is high the GATE pin voltage is monitored with respect to the OUT pin. Once the GATE minus OUT voltage exceeds 4.2V the PG pin goes high. This indicates to the system that it is safe to load the OUT pin while the MOSFET is completely turned “on”. The PG pin goes low when the GATE is commanded off (using the UV, OV or SENSE pins) or when the PG comparator drives low. 4217fc 12 LTC4217 APPLICATIONS INFORMATION 12V Fixed Version In the LTC4217-12 the UV, OV and FB pins are driven by internal dividers which may need to be filtered to prevent false faults. By placing a bypass capacitor on these pins the faults are delayed by the RC time constant. Use the RIN value from the electrical characteristics table for this calculation. In cases where the fixed thresholds need a slight adjustment, placing a resistor from the UV or OV pins to VDD or GND will adjust the threshold up or down. Likewise placing a resistor between FB pin to OUT or GND adjusts the threshold. Again use the RIN value from the electrical characteristics table for this calculation. An example in Figure 5 raises the UV turn-on voltage from 9.88V to 10.5V. Increasing the UV level requires adding a resistor between UV and ground. The resistor, RSHUNT1, can be calculated using electrical table parameters as follows: RSHUNT1 = R(IN ) • VOLD ( VNEW – VOLD ) = 18k • 9.88 = 287k (10.5 – 9.88) In this same figure the OV threshold is lowered from 15.05V to 13.5V. Decreasing the OV threshold requires adding a resistor between VDD and OV. This resistor can be calculated as follows: ( R(IN ) • VOLD ⎛ VNEW – VOV ( TH ) ⎜ RSHUNT2 = V( TH ) ⎜ ( VOLD – VNEW ) ⎝ ) ⎞ ⎟= ⎟ ⎠ 18k • 15.05 ⎛ (13.5 – 1.235) ⎞ = 1.736M 1.235 ⎜⎝ (15.05 – 13.5) ⎟⎠ LTC4217-12 VDD OV RSHUNT2 UV RSHUNT1 4217 F05 Figure 5. Adjusting LTC4217-12 Thresholds Use the equation for RSHUNT1 for increasing the OV and FB thresholds. Likewise use the equation for RSHUNT2 for decreasing the UV and FB thresholds. Design Example Consider the following design example (Figure 6): VIN = 12V, IMAX = 2A. IINRUSH = 100mA, CL = 330μF, VUVON = 9.88V, VOVOFF = 15.05V, VPWRGD = 10.5V. A current limit fault triggers an automatic restart of the power-up sequence. VDD 12V OUT 12V UV LTC4217-12DHC FLT + CL 330μF VOUT 12V 1.5A R1 10k PG TIMER INTVCC C1 0.1μF GND IMON ADC R2 20k 4217 F06 Figure 6. 1.5A, 12V Card Resident Application The inrush current is defined by the current required to charge the output capacitor using the fixed 0.3V/ms GATE charge-up rate. The inrush current is defined as: ⎛ 0.3V ⎞ ⎛ 0.3V ⎞ = 100mA = 330µF • ⎜ IINRUSH = CL • ⎜ ⎟ ⎝ ms ⎟⎠ ⎝ ms ⎠ As mentioned previously the charge-up time is the output voltage (12V) divided by the output rate of 0.3V/ms resulting in 40ms. The peak power dissipation of 12V at 100mA (or 1.2W) is within the SOA of the pass MOSFET for 40ms (see MOSFET SOA curve in the Typical Performance Characteristics section). Next the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the MOSFET. The worst-case power dissipation occurs when the voltage versus current profile of the foldback current limit is at the maximum. This occurs when the current is 2A and the voltage is one half of the 12V or 6V. See the Current Limit Sense Voltage vs FB Voltage in the Typical Performance Characteristics section to view this profile. In order to survive 12W, the MOSFET SOA dictates a maximum time of 10ms (see SOA graph). Use the internal 2ms timer 4217fc 13 LTC4217 APPLICATIONS INFORMATION invoked by tying the TIMER pin to INTVCC. After the 2ms timeout the FLT pin needs to pull-down on the UV pin to restart the power-up sequence. Since the default values for overvoltage, undervoltage and power good thresholds for the 12V fixed version match the requirements, no external components are required for the UV, OV and FB pins. The final schematic in Figure 6 results in very few external components. The pull-up resistor, R1, connects to the PG pin while the 20k (R2) converts the IMON current to a voltage at a ratio: VIMON = 50[μA/A] • 20k • IOUT = 1[V/A] • IOUT In addition there is a 0.1μF bypass (C1) on the INTVCC pin. Layout Considerations In Hot Swap applications where load currents can be 2A, narrow PCB tracks exhibit more resistance than wider tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5mΩ/square. Small resistances add up quickly in high current applications. There are two VDD pins on opposite sides of the package that connect to the sense resistor and MOSFET. The PCB layout should be balanced and symmetrical to each VDD pin to balance current in the MOSFET bond wires. Figure 7 shows a recommended layout for the LTC4217. Although the MOSFET is self protected from overtemperature, it is recommended to solder the backside of the package to a copper trace to provide a good heat sink. Note that the backside is connected to the SENSE pin and cannot be soldered to the ground plane. During normal loads the power dissipated in the MOSFET is as high as 0.23W. A 10mm × 10mm area of 1oz copper should be sufficient. This area of copper can be divided in many layers. It is also important to put C1, the bypass capacitor for the INTVCC pin as close as possible between the INTVCC and GND. Additional Applications The LTC4217 has a wide operating range from 2.9V to 26.5V. The UV, OV and PG thresholds are set with few resistors. All other functions are independent of supply voltage. Figure 8 shows a 3.3V application with a UV threshold of 2.87V, an OV threshold of 3.77V and a PG threshold of 3.05V. The last page includes a 24V application with a UV threshold of 19.9V, an OV threshold of 26.3V and a PG threshold of 20.75V. VDD OUT OUT VDD 3.3V HEAT SINK R4 14.7k LTC4217FE R1 17.4k FB R5 3.3V 10k UV R2 3.16k VIA TO SINK FLT + VOUT 3.3V 1.5A CL 100μF R6 10k OV R3 10k PG TIMER INTVCC C GND CT 0.1μF GND IMON ADC RMON 20k 4217 F08 4217 F07 Figure 7. Recommended Layout Figure 8. 3.3V, 1.5A Card Resident Application 4217fc 14 LTC4217 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ±0.05 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5.00 ±0.10 (2 SIDES) R = 0.20 TYP 3.00 ±0.10 (2 SIDES) 9 0.40 ± 0.10 16 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH (DHC16) DFN 1103 8 0.200 REF 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 4.40 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4217fc 15 LTC4217 PACKAGE DESCRIPTION FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 6.60 ±0.10 2.74 (.108) 4.50 ±0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 4217fc 16 LTC4217 REVISION HISTORY (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 12/09 Revise Features, Description and Typical Application Revise Absolute Maximum Ratings Storage Temperature Range and Pin Configuration Revise Electrical Characteristics 1 2 3, 4 Revise Graph G11 6 Update Pin Functions 7 Update Functional Diagram 8 Update Operation Section Revise Figure 1 and Update Values and Equation in Applications Information Section 9 10-12, 14 4217fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 17 LTC4217 TYPICAL APPLICATION 24V, 1.5A Card Resident Application VDD 24V OUT 158k LTC4217FE * + VOUT 24V 100μF 1.5A FB 200k 10k UV 24V FLT 3.24k OV 10k 10k PG TIMER INTVCC 0.1μF GND IMON ADC 20k 4217 TA02 *DIODES INC. SMAJ24A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Dual Channel, Hot Swap Controller Operates from 3V to 12V, Supports –12V, SSOP-24 LTC1422 Single Channel, Hot Swap Controller Operates from 2.7V to 12V, SO-8 LTC1642A Single Channel, Hot Swap Controller Operates from 3V to 16.5V, Overvoltage Protection Up to 33V, SSOP-16 LTC1645 Dual Channel, Hot Swap Controller Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14 LTC1647-1/LTC1647-2/ LTC1647-3 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V, SO-8 or SSOP-16 LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 LTC4214 Negative Voltage, Hot Swap Controller Operates from –6V to –16V, MSOP-10 LTC4215 Hot Swap Controller with I2C Compatible Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage Monitoring LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16 LT4220 Positive and Negative Voltage, Dual Channels, Hot Swap Controller Operates from ±2.7V to ±16.5V, SSOP-16 LTC4221 Dual Hot Swap Controller/Sequencer Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 LTC4230 Triple Channels, Hot Swap Controller Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20 4217fc 18 Linear Technology Corporation LT 1209 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008