HA-5033 ® Data Sheet February 6, 2006 FN2924.8 250MHz Video Buffer Features The HA-5033 is a unity gain monolithic IC designed for any application requiring a fast, wideband buffer. Featuring a bandwidth of 250MHz and outstanding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. Other features, which include a minimum slew rate of 1000V/µs and high output drive capability, make the HA-5033 applicable for line driver and high speed data conversion circuits. • Differential Phase Error . . . . . . . . . . . . . . . . 0.02 Degrees • Differential Gain Error . . . . . . . . . . . . . . . . . . . . . . 0.03% • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . 1100V/µs • Wide Bandwidth (Small Signal) . . . . . . . . . . . . . . 250MHz • Wide Power Bandwidth . . . . . . . . . . . . . . DC to 17.5MHz • Fast Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ns • High Output Drive. . . . . . . . . . . . . . ±10V With 100Ω Load The high performance of this product is a result of the Intersil Dielectric Isolation process. A major feature of this process is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs, such as the HA-5033, practical. Alternative process methods typically produce a lower AC performance. • Wide Power Supply Range . . . . . . . . . . . . . ±5V to ±16V Ordering Information • High Frequency Buffer PART NUMBER PART MARKING TEMP. RANGE (°C) HA2-5033-2 HA2-5033-2 -55 to 125 HA3-5033-5 HA3-5033-5 0 to 75 PACKAGE PKG. DWG. # 12 Pin Metal Can T12.C 8 Ld PDIP • Replace Costly Hybrids Applications • Video Buffer • Isolation Buffer • High Speed Line Driver • Impedance Matching E8.3 • Current Boosters Pinouts • High Speed A/D Input Buffers HA-5033 (PDIP) TOP VIEW • Related Literature - AN548, Designer’s Guide for HA-5033 V+ 1 8 OUT NC 2 7 NC NC 3 6 SUBSTRATE IN 4 5 V- HA-5033 (METAL CAN) TOP VIEW V+ NC CASE OUT 12 11 1 NC V- 10 2 9 3 8 4 NC NC NC 7 5 6 +IN NC NC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA-5033 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Pins. . . . . . . . . . . . . . . . . . . . . . . . 40V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VOutput Current (Peak) (50ms On/1 Second Off) . . . . . . . . . ±200mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . 2000V Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) Metal Can Package . . . . . . . . . . . . . . . 65 34 PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Packages) . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Operating Conditions Temperature Ranges (Note 3) HA-5033-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C HA-5033-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175°C for the metal can package, and below 150°C for the plastic packages (See Figure 5.). 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. The maximum operating temperature may have to be derated depending on the output load condition. See Figure 5 for more information. VSUPPLY = ±12V, RS = 50Ω, RL = 100Ω, CL = 10pF, Unless Otherwise Specified Electrical Specifications TEST CONDITIONS HA-5033-2 HA-5033-5 TEMP. (°C) MIN TYP MAX MIN TYP MAX UNITS 25 - 5 15 - 5 15 mV Full - 6 25 - 6 25 mV Average Offset Voltage Drift Full - 33 - - 33 - µV/°C Bias Current 25 - 20 35 - 20 35 µA Full - 30 50 - 30 50 µA Input Resistance 25 - 3 - - 3 - MΩ Input Capacitance 25 - 1.6 - - 1.6 - pF 10Hz to 100MHz 25 - 20 - - 20 - µVP-P RL = 100Ω 25 0.93 - - 0.93 - - V/V RL = 1kΩ 25 0.93 0.99 - 0.93 0.99 - V/V RL = 100Ω Full 0.92 - - 0.92 - - V/V 25 - 250 - - 250 - MHz RL = 100Ω Full ±8 ±10 - ±8 ±10 - V RL = 1kΩ, VS = ±15V Full ±11 ±12 - ±11 ±12 - V Output Current 25 ±80 ±100 - ±80 ±100 - mA Output Resistance 25 - 8 - - 8 - Ω 25 - 146 - - 146 - MHz 25 15.9 17.5 - 15.9 17.5 - MHz 25 - 4.6 - - 4.6 - ns 25 - 1 - - 1 - ns PARAMETER INPUT CHARACTERISTICS Offset Voltage Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain -3dB Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing Full Power Bandwidth VOUT = 1VRMS , RL = 1kΩ Full Power Bandwidth (Note 4) TRANSIENT RESPONSE Rise Time VOUT = 500mV Propagation Delay 2 FN2924.8 HA-5033 VSUPPLY = ±12V, RS = 50Ω, RL = 100Ω, CL = 10pF, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS HA-5033-2 HA-5033-5 TEMP. (°C) MIN TYP MAX MIN TYP MAX UNITS Overshoot 25 - 3 - - 3 - % Slew Rate (Note 4) 25 1 1.1 - 1 1.1 - V/ns Settling Time to 0.1% 25 - 50 - - 50 - ns Differential Phase Error (Note 5) 25 - 0.02 - - 0.02 - Degree Differential Gain Error (Note 5) 25 - 0.03 - - 0.03 - % 25 - 21 25 - 21 25 mA Full - 21 30 - 21 30 mA Full 54 - - 54 - - dB 25 - <0.1 - - <0.1 - % PARAMETER POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio Harmonic Distortion VIN = 1VRMS at 100kHz NOTES: 4. VSUPPLY = ±15V, VOUT = ±10V, RL = 1kΩ. 5. Differential gain and phase error are nonlinear signal distortions found in video systems and are defined as follows: Differential gain error is defined as the change in amplitude at the color subcarrier frequency as the picture signal is varied from blanking to white level. Differential phase error is defined as the change in the phase of the color subcarrier as the picture signal is varied from blanking to white level. RL = 300Ω. Test Circuits and Waveforms +15V +12V 0.1µF IN OUT 0.1µF IN OUT RL 100Ω 0.1µF 0.1µF -15V -12V FIGURE 2. TRANSIENT RESPONSE FIGURE 1. SLEW RATE AND SETTLING TIME 10V 500mV INPUT INPUT 0V 0V OVERSHOOT OUTPUT 90% ∆V 10% SLEW RATE = ∆V/∆t SETTLING TIME ∆t ERROR BAND ±10mV FROM FINAL VALUE FIGURE 3. SETTLING TIME AND SLEW RATE 3 90% OUTPUT 10% NOTE: Measured on both positive and negative transitions. FIGURE 4. RISE TIME AND OVERSHOOT FN2924.8 HA-5033 Test Circuits and Waveforms (Continued) VIN VIN 0V 0V VOUT VOUT 0V 0V TA = 25°C, RS = 50Ω, RL = 100Ω TA = 25°C, RS = 50Ω, RL = 1kΩ +10V RESPONSE +10V RESPONSE 500mV VIN 0V 500mV VOUT 0V TA = 25°C, RS = 50Ω, RL = 100Ω PULSE RESPONSE Schematic Diagram V+ R5 R4 R2 Q15 Q11 Q16 Q12 R12 Q6 Q10 Q1 R9 Q7 Q19 VIN R6 Q3 VOUT Q4 Q8 R8 Q17 R11 Q13 R10 Q2 Q5 Q9 Q14 Q18 R1 R13 R3 V- 4 FN2924.8 HA-5033 Application Information It is also recommended that the bypass capacitors be connected close to the HA-5033 (preferably directly to the supply pins). The wide bandwidth of the HA-5033 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. IC sockets contribute inter-lead capacitance which limits device bandwidth and should be avoided. Pin 6 can be tied to either supply, grounded, or simply not used. But to optimize device performance and improve isolation, it is recommended that this pin be grounded. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimum device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01µF to 0.1µF will minimize high frequency variations in supply voltage. Solid tantalum capacitors 1µF or larger will optimize low frequency performance. Typical Applications Figure 5 is based on: T JMAX – T A P DMAX = -----------------------------θ JA Where: TJMAX = Maximum Junction Temperature of the Device TA = Ambient Temperature θJA = Junction to Ambient Thermal Resistance MAXIMUM TOTAL POWER DISSIPATION (W) Layout Considerations 2.4 2.2 2.0 CAN 1.8 1.6 1.4 1.2 1.0 PDIP 0.8 0.6 QUIESCENT PD = 0.72W AT VS = ±12V, ICC = 30mA 0.4 0.2 0 25 65 45 V+ HA-2539 0.1µF VIN 125 (Also see Application Note AN548) V+ 5 105 FIGURE 5. MAXIMUM POWER DISSIPATION vs TEMPERATURE +12V RS 85 TEMPERATURE (°C) 12 VIDEO SIGNAL INPUT RM 11 50Ω 10 R1 HA-5033 + 60Ω - VIDEO OUTPUT 75Ω RG -58 75Ω R2 15Ω 50Ω V- V- RL 900Ω 0.1µF -12V 100Ω FIGURE 6. VIDEO COAXIAL LINE DRIVER 50Ω SYSTEM 5 FIGURE 7. VIDEO GAIN BLOCK FN2924.8 HA-5033 Typical Applications (Also see Application Note AN548) (Continued) 0V VIN VIN 0V 0V VOUT VOUT 0V TA = 25°C, RS = 50Ω, RM = RL = 50Ω TA = 25°C, RS = 50Ω, RM = RL = 50Ω RL 1 V O = V IN ---------------------- = --- V IN RL + RM 2 RL 1 V O = V IN ---------------------- = --- V IN RL + RM 2 POSITIVE PULSE RESPONSE NEGATIVE PULSE RESPONSE Typical Performance Curves 40 7 VS = ±15V VS = ±12V INPUT BIAS CURRENT (µA) OFFSET VOLTAGE (mV) 8 6 5 4 3 VS = ±10V 2 1 -80 VS = ±10V 30 VS = ±5V 20 VS = ±12V 10 VS = ±5V -40 0 80 40 TEMPERATURE (°C) 120 0 -55 160 FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE 3000 SLEW RATE (V/µs) VS = ±15V 20 VS = ±12V VS = ±10V VS = ±5V 10 -25 25 75 TEMPERATURE (°C) 125 FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE 30 SUPPLY CURRENT (mA) VS = ±15V VS = ±15V, VIN = ±10V FALL (RL = 1kΩ) 2000 FALL (RL = 100Ω) 1000 RISE (RL = 1kΩ) RISE (RL = 100Ω) 0 -55 -25 25 75 TEMPERATURE (°C) FIGURE 10. SUPPLY CURRENT vs TEMPERATURE 6 125 -55 -25 25 75 125 TEMPERATURE (°C) FIGURE 11. SLEW RATE vs TEMPERATURE FN2924.8 HA-5033 Typical Performance Curves (Continued) 2400 2200 VS = ±15V, RL = 1kΩ TA = 25°C, VIN = ±10V 2000 SLEW RATE (V/µs) SLEW RATE (V/µs) 1800 1600 FALL 1400 1200 1000 RISE 800 600 400 200 0 100 1000 5000 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 VS = ±15V, RL = 100Ω TA = 25°C, VIN = ±10V FALL RISE 0 10,000 100 900 VS = ±15V, TA = 25°C RL = 1kΩ OUTPUT INPUT VOS (mV) OUTPUT INPUT VOS (mV) 40 20 RL = 10kΩ RL = 10kΩ -20 -40 -60 -8 -6 -4 -2 0 +2 10,000 +4 +6 RL = 50Ω 500 300 RL = 100Ω 100 0 -100 RL = 100Ω -300 -500 -700 RL = 1kΩ -80 -10 VS = ±15V, TA = 25°C 700 60 0 5000 FIGURE 13. SLEW RATE vs LOAD CAPACITANCE FIGURE 12. SLEW RATE vs LOAD CAPACITANCE 80 1000 CAPACITANCE (pF) CAPACITANCE (pF) +8 RL = 50Ω -900 -10 +10 -8 -6 -2 -4 0 +2 +4 +6 +8 +10 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 15. GAIN ERROR vs INPUT VOLTAGE FIGURE 14. GAIN ERROR vs INPUT VOLTAGE 160 VS = ±15, TA = 25°C VS = ±15V, VO = ±10V 800 700 120 VIN - VOUT (mV) OUTPUT INPUT VOS (mV) 140 100 RL = 1kΩ 80 60 40 VOUT = -10 VOUT = 0 SINKING CURRENT 600 VOUT = +10 500 VOUT = 0 SOURCING CURRENT 400 300 200 20 100 0 -55 -25 25 75 TEMPERATURE (°C) FIGURE 16. GAIN ERROR vs TEMPERATURE 7 125 10 20 30 40 50 60 70 IOUT (mA) 80 90 100 110 120 FIGURE 17. VIN - VOUT vs IOUT FN2924.8 HA-5033 Typical Performance Curves (Continued) 180 1 Y21 Y21, Y22 10-1 90 Y11 MAGNITUDE (S) PHASE ANGLE (DEGREES) 135 45 0 Y22 -45 Y12 -90 Y11 Y12 Y22 Y21 10-2 10-3 10-4 Y11 -135 Y12 -180 106 107 108 10-5 106 109 107 108 FREQUENCY (Hz) FREQUENCY (Hz) 70 60 50 40 30 20 10 10K 100K FREQUENCY (Hz) 1M 10M FIGURE 20. POWER SUPPLY REJECTION RATIO vs FREQUENCY 1.0 0.1 0.01 1 2 INPUT VOLTAGE (RMS) 3 FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE 8 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 1K 10K FREQUENCY (Hz) 100K FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY VS = ±12V = ±12V, RL = 100Ω RL = ±V 100Ω f = 100kHz 0 VS = ±12V, RL = 100Ω VIN = 1VRMS 0.09 100 PEAK TO PEAK OUTPUT VOLTAGE (V) TOTAL HARMONIC DISTORTION (%) 0.10 VS = ±12V, TA = 25°C 1K FIGURE 19. Y - PARAMETER MAGNITUDE vs FREQUENCY TOTAL HARMONIC DISTORTION (%) POWER SUPPLY REJECTION RATIO (dB) FIGURE 18. Y - PARAMETERS PHASE vs FREQUENCY 109 TA = 25°C 28 VS = ±15V VS = ±12V 24 20 16 VS = ±10V 12 8 4 VS = ±5V 0 100 200 300 400 500 600 700 800 900 1K LOAD RESISTANCE (Ω) FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FN2924.8 HA-5033 Typical Performance Curves 6.0 6.0 VS = ±15V, RL = 100Ω 5.0 4.5 4.0 NO HEAT SINK IN FREE AIR 3.5 3.0 2.5 2.0 1.5 5.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 100K 1M 10M FREQUENCY (Hz) 100M FIGURE 24. OUTPUT SWING vs FREQUENCY (NOTE) 1G NO HEAT SINK IN FREE AIR 4.0 1.0 0 10K VS = ±15V, RL = 1kΩ 5.5 OUTPUT VOLTAGE (VRMS) 5.5 OUTPUT VOLTAGE (VRMS) (Continued) 0 10K 100K 1M 10M FREQUENCY (Hz) 100M 1G FIGURE 25. OUTPUT SWING vs FREQUENCY (NOTE) NOTE: This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-5033 with increased distortion (to the right of curve shown), will also be accompanied by an increase in supply current. The resulting increase in chip temperature must be considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased beyond the curve shown, the NPN, PNP output transistors will approach a condition of being simultaneously on. Under this condition, thermal runaway can occur. 9 FN2924.8 HA-5033 Die Characteristics TRANSISTOR COUNT: 20 SUBSTRATE POTENTIAL (POWERED UP): PROCESS: Unbiased Bipolar Dielectric Isolation Metallization Mask Layout HA-5033 IN V+ OUT V- 10 FN2924.8 HA-5033 Metal Can Packages (Can) T12.C REFERENCE PLANE A 12 LEAD METAL CAN PACKAGE L e1 INCHES SYMBOL A A k1 e ØD ØD1 N 2 1 k F Øb LEAD FINISH Øb2 SECTION A-A MAX MILLIMETERS MIN MAX NOTES A 0.130 0.150 3.30 3.81 - Øb 0.016 0.019 0.41 0.48 - Øb2 0.016 0.021 0.41 0.53 - ØD 0.585 0.615 14.86 15.62 - ØD1 0.540 0.560 13.72 14.22 - e e1 BASE METAL MIN 0.400 BSC 0.100 BSC 10.16 BSC - 2.54 BSC - F 0.020 0.040 0.51 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.560 12.70 N 12 14.22 12 3 Rev. 0 5/18/94 NOTES: 1. The reference, base, and seating planes are the same for this variation. 2. Measured from maximum diameter of the product. 3. N is the maximum number of terminal positions. 4. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 5. Controlling dimension: INCH. 11 FN2924.8 HA-5033 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN2924.8