INTERSIL HA7-5147-2

[ /Title
(HA5147)
/Subject
(120M
Hz,
UltraLow
Noise
Precision
Operational
Amplifiers)
/Autho
r ()
/Keywords
(Intersil
Corporation,
Semiconductor,
single,
operational
amplifier,
low
power
op
amp,
low
input
bias
HA-5147
TM
Data Sheet
April 2000
File Number
2910.6
120MHz, Ultra-Low Noise Precision
Operational Amplifiers
Features
The HA-5147 operational amplifier features an unparalleled
combination of precision DC and wideband high speed
characteristics. Utilizing the Intersil D. I. technology and
advanced processing techniques, this unique design unites
low noise (3.2nV/√Hz) precision instrumentation
performance with high speed (35V/µs) wideband capability.
• Wide Gain Bandwidth (AV ≥ 10) . . . . . . . . . . . . . . 120MHz
• Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V/µs
This amplifier’s impressive list of features include low VOS
(30mV), wide gain bandwidth (120MHz), high open loop gain
(1500V/mV), and high CMRR (120dB). Additionally, this
flexible device operates over a wide supply range (±5V to
±20V) while consuming only 140mW of power.
Using the HA-5147 allows designers to minimize errors while
maximizing speed and bandwidth in applications requiring
gains greater than ten.
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5147’s qualities include instrumentation amplifiers, pulse
or RF amplifiers, audio preamplifiers, and signal conditioning
circuits.
This device can easily be used as a design enhancement by
directly replacing the 725, OP25, OP06, OP07, OP27 and
OP37 where gains are greater than ten. For military grade
product, refer to the HA-5147/883 data sheet.
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
HA7-5147-2
-55 to 125
8 Ld CERDIP
F8.3A
HA7-5147-5
0 to 75
8 Ld CERDIP
F8.3A
HA9P5147-9
(H51479)
-40 to 85
8 Ld SOIC
M8.15
1
• Low Noise. . . . . . . . . . . . . . . . . . . . . . 3.2nV/√Hz at 1kHz
• Low VOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV
• High CMRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120dB
• High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V/mV
Applications
• High Speed Signal Conditioners
• Wide Bandwidth Instrumentation Amplifiers
• Low Level Transducer Amplifiers
• Fast, Low Level Voltage Comparators
• Highest Quality Audio Preamplifiers
• Pulse/RF Amplifiers
• For Further Design Ideas See Application Note AN553
Pinout
HA-5147 (CERDIP, SOIC)
TOP VIEW
BAL
1
-IN
2
+IN
3
V-
4
+
8
BAL
7
V+
6
OUT
5
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HA-5147
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V
Differential Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 0.7V
Output Current . . . . . . . . . . . . . . . . . . . Full Short Circuit Protection
Operating Conditions
Temperature Range
HA-5147-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HA-5147-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HA-5147-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . .
135
50
SOIC Package . . . . . . . . . . . . . . . . . . .
158
N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. For differential input voltages greater than 0.7V, the input current must be limited to 25mA to protect the back-to-back input diodes.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
VSUPPLY = ±15V, CL ≤ 50pF, RS ≤ 100Ω
Electrical Specifications
TEMP.
(oC)
MIN
TYP
MAX
UNITS
25
-
30
100
µV
Full
-
70
300
µV
Average Offset Voltage Drift
Full
-
0.4
1.8
µV/oC
Bias Current
25
-
15
80
nA
Full
-
35
150
nA
25
-
12
75
nA
Full
-
30
135
nA
Common Mode Range
Full
±10.3
±11.5
-
V
Differential Input Resistance (Note 3)
25
0.8
4
-
MΩ
PARAMETER
TEST CONDITIONS
INPUT CHARACTERISTICS
Offset Voltage
Offset Current
Input Noise Voltage (Note 4)
0.1Hz to 10Hz
25
-
0.09
0.25
µVP-P
Input Noise Voltage Density (Note 5)
f = 10Hz
25
-
3.8
8.0
nV/√Hz
f = 100Hz
-
3.3
4.5
nV/√Hz
f = 1000Hz
-
3.2
3.8
nV/√Hz
-
1.7
-
pA/√Hz
f = 100Hz
-
1.0
-
pA/√Hz
f = 1000Hz
-
0.4
0.6
pA/√Hz
25
10
-
-
V/V
25
700
1500
-
V/mV
Full
300
800
-
V/mV
Input Noise Current Density (Note 5)
f = 10Hz
25
TRANSFER CHARACTERISTICS
Minimum Stable Gain
VOUT = ±10V, RL = 2kΩ
Large Signal Voltage Gain
2
HA-5147
VSUPPLY = ±15V, CL ≤ 50pF, RS ≤ 100Ω (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP.
(oC)
MIN
TYP
MAX
UNITS
Common Mode Rejection Ratio
VCM = ±10V
Full
100
120
-
dB
Gain-Bandwidth-Product
f = 10kHz
25
120
140
-
MHz
-
120
-
MHz
f = 1MHz
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 600Ω
25
±10.0
±11.5
-
V
RL = 2kΩ
Full
±11.4
±13.5
-
V
25
445
500
-
kHz
25
-
70
-
Ω
25
16.5
25
-
mA
25
-
22
50
ns
Full Power Bandwidth (Note 6)
Output Resistance
Open Loop
Output Current
TRANSIENT RESPONSE (Note 7)
Rise Time
Slew Rate
VOUT = ±3V
25
28
35
-
V/µs
Settling Time
Note 8
25
-
400
-
ns
25
-
20
40
%
25
-
3.5
-
mA
Full
-
-
4.0
mA
Full
-
16
51
µV/V
Overshoot
POWER SUPPLY CHARACTERISTICS
Supply Current
VS = ±4V to ±18V
Power Supply Rejection Ratio
NOTES:
3. This parameter value is based upon design calculations.
4. Refer to Typical Performance section of the data sheet.
5. The limits for this parameter are guaranteed based on lab characterization, and reflect lot-to-lot variation.
Slew Rate
6. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ----------------------------- .
2πV PEAK
7. Refer to Test Circuits section of the data sheet.
8. Settling time is specified to 0.1% of final value for a 10V output step and AV = -10.
3
HA-5147
Test Circuits and Waveforms
IN
+
OUT
1.8kΩ
50pF
200Ω
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
IN
IN
OUT
OUT
Vertical Scale: Input = 0.5V/Div.
Output = 5V/Div.
Horizontal Scale: 500ns/Div.
Vertical Scale: Input = 10mV/Div.
Output = 100mV/Div.
Horizontal Scale: 100ns/Div.
LARGE SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
+15V
2N4416
500Ω
TO
OSCILLOSCOPE
5kΩ
2kΩ
+15V
+
VOUT
AUT
-
VIN
200Ω
50pF
-15V
2kΩ
NOTES:
9. AV = -10.
10. Feedback and summing resistors should be 0.1%
matched.
11. Clipping diodes are optional. HP5082-2810 recommended.
FIGURE 2. SETTLING TIME TEST CIRCUIT
4
Schematic Diagram
7
1
R25
C7
8
BALANCE
R1
R16
R15
R2
R20
QP43
QP35
D1
QN45
R21
R17
QP32
QP37
QP38
QP44
QP55
5
C5
QN19
D8
QN46
C4
QN13
QP56
QP
27
R7
QP26
QP26
6
R18
QP36A
D41
QP40
QN1A
QN18
QN1
QN42
R4
QN6
QN42A
QN25
R5
R8
R10
QN10
QN11
4
3
QN50
QN49
R6
2
C3
QN5
QN48
QN39
D60
QP30
R19
D23
QN24
QN57
R13
D34
QN7
D22
D59
R12
OUTPUT
QN2A
Z58
QN20
D33
R3
C2
R22
R23
R11
QP21
HA-5147
QP36
QN2
QN29
QP16
QN4
D54
R9
QN12
D9
D53
R24
QN15
C1
QN52
C6
QN3
R2A
QP17
QN51
R14
QN14
QN47
R1A
HA-5147
Application Information
V+
RP
10K
8
1
7
-
2
NOTE: Tested Offset Adjustment
Range is |VOS +1mV| minimum referred to output. Typical range is ±4mV
with RP = 10kΩ.
6
+
5
3
4
FIGURE 3.
SUGGESTED OFFSET VOLTAGE ADJUSTMENT
CS
R1
+
-
R2
R1
-
R3
+
R3
R2
CS
NOTE: Low resistances are preferred for low noise applications as a 1kΩ resistor has 4nV/√Hz of thermal noise. Total resistances of greater than
10kΩ on either input can reduce stability. In most high resistance applications, a few picofarads of capacitance across the feedback resistor will improve stability.
FIGURE 4. SUGGESTED STABILITY CIRCUITS
TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified
12
VOLTAGE NOISE (nV/√Hz)
OFFSET VOLTAGE (µV)
20
10
0
-10
-20
-30
-40
10
5
8
4
6
3
NOISE VOLTAGE
4
2
1
2
-50
-60
-60
6
VS = ±15V, TA = 25oC
30
NOISE CURRENT
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (oC)
FIGURE 5. TYPICAL OFFSET VOLTAGE vs TEMPERATURE
6
0
1
10
100
1K
10K
FREQUENCY (Hz)
100K
FIGURE 6. NOISE CHARACTERISTICS
0
1M
CURRENT NOISE (pA/√Hz)
Typical Performance Curves
HA-5147
Typical Performance Curves
TA = 25oC
VS = ±15V
TA = 25oC
160
0.12
0.1
120
0.08
CMRR (dB)
0.06
0.04
80
40
0.02
0
4
6
8
10
12
14
16
18
0
10
20
100
1K
10K
SUPPLY VOLTAGE (±V)
FIGURE 7. NOISE vs SUPPLY VOLTAGE
1M
10M
FIGURE 8. CMRR vs FREQUENCY
120
0
TA = 25oC
100
GAIN (dB)
20
40
PSRR (dB)
100K
FREQUENCY (Hz)
60
80
GAIN
60
40
0
20
80
PHASE
0
90
100
120
180
10
100
1K
10K
100K
1M
100
1K
10K
FIGURE 9. PSRR vs FREQUENCY
SLEW RATE NORMALIZED TO 1 AT 30oC
AVOL (100kV/V) AND VOUT (V)
1.05
AVOL
15
14
13
VOUT
12
11
10
9
8
7
6
5
4
0
2
4
6
8
LOAD RESISTANCE (kΩ)
FIGURE 11. AVOL AND VOUT vs LOAD RESISTANCE
7
10M
100M
FIGURE 10. OPEN LOOP GAIN AND PHASE vs FREQUENCY
TA = 25oC
16
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
17
100K
PHASE (DEGREES)
INPUT NOISE VOLTAGE (µVP-P)
0.14
TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
10
RL = 2K, CL = 50pF, TA = 25oC
1.04
1.03
1.02
1.01
1.0
0.99
0.98
0.97
0.96
0.95
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (oC)
FIGURE 12. NORMALIZED SLEW RATE vs TEMPERATURE
HA-5147
Typical Performance Curves
TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
28
2.82
RL = 2K, CL = 50pF, TA = 25oC
VO = 0V, VS = ±15V
24
OUTPUT VOLTAGE (VP-P)
SUPPLY CURRENT (mA)
2.80
2.78
2.76
2.74
2.72
20
16
12
8
2.70
4
2.68
-55
25
125
TEMPERATURE (oC)
0
0.4
0.8
1.2
1.6
2
FREQUENCY (MHz)
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. VOUT MAX (UNDISTORTED SINEWAVE OUTPUT)
vs FREQUENCY
RL = 2K, CL = 50pF, TA = 25oC
30
GAIN
20
10
0
0
PHASE
90
180
1K
10K
100K
1M
10M
PHASE (DEGREES)
GAIN (dB)
40
100M
ACL = 25,000V/V; EN = 0.08µVP-P RTI
Horizontal Scale = 1s/Div.; Vertical Scale = 0.002µV/Div.
FREQUENCY (Hz)
FIGURE 15. CLOSED LOOP GAIN AND PHASE vs FREQUENCY
8
FIGURE 16. PEAK-TO-PEAK NOISE VOLTAGE (0.1Hz TO 10Hz)
HA-5147
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
104 mils x 65 mils x 19 mils
2650µm x 1650µm x 483µm
METALLIZATION:
TRANSISTOR COUNT:
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
63
SUBSTRATE POTENTIAL (POWERED UP):
PROCESS:
V-
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5147
BAL
BAL
-IN
V+
+IN
OUT
V-
9
NC
HA-5147
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
LEAD FINISH
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
eA
ccc M C A - B S
e
eA/2
c
aaa M C A - B S D S
D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
10
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
8
8
8
Rev. 0 4/94
HA-5147
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C A M
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
MILLIMETERS
MIN
0.050 BSC
1.27 BSC
0.2284
0.2440
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
5.80
-
H
8
0o
6.20
-
8
7
8o
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
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