HA-5002 Data Sheet October 18, 2013 FN2921.12 110MHz, High Slew Rate, High Output Current Buffer Features The HA-5002 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. • High input impedance . . . . . . . . . . . . . . . . . . . . . .3000kΩ Utilizing the advantages of the Intersil D.I. technologies, the HA-5002 current buffer offers 1300V/μs slew rate with 110MHz of bandwidth. The ±200mA output current capability is enhanced by a 3Ω output impedance. • Very wide bandwidth . . . . . . . . . . . . . . . . . . . . . . 110MHz The monolithic HA-5002 will replace the hybrid LH0002 with corresponding performance increases. These characteristics range from the 3000kΩ input impedance to the increased output voltage swing. Monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. • Voltage gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995 • Low output impedance . . . . . . . . . . . . . . . . . . . . . . . . . 3Ω • Very high slew rate. . . . . . . . . . . . . . . . . . . . . . . 1300V/μs • High output current . . . . . . . . . . . . . . . . . . . . . . . . . . ±200mA • Pulsed output current . . . . . . . . . . . . . . . . . . . . . . . 400mA • Monolithic construction • Pb-Free available (RoHS Compliant) Applications • Line driver The HA-5002 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. • Data acquisition For the military grade product, refer to the HA-5002/883 datasheet. • High power current booster • 110MHz buffer • Radar cable driver • High power current source • Sample and holds • Video products Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) -55 to +125 PACKAGE PKG. DWG. # HA2-5002-2 HA2- 5002-2 HA4P5002-5Z (Note 1) HA4P 5002-5Z HA9P5002-5Z (Note 1) 5002 5Z 0 to +75 8 Ld SOIC (Pb-free) M8.15 HA9P5002-9Z (Note 1) 5002 9Z -40 to +85 8 Ld SOIC (Pb-free) M8.15 0 to +75 8 Pin Metal Can T8.C 20 Ld PLCC (Pb-free) N20.35 NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003-2006, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HA-5002 Pinouts 2 7 V2+ NC 3 6 NC 4 5 V1- NC V2- OUT OUT NC 8 V1+ 1 NC V1+ IN 3 2 1 20 19 8 V1+ NC 4 18 NC V2- 5 17 V2+ NC 6 16 NC NC 7 15 NC NC 8 14 NC V2+ 1 7 2 NC V1- 6 5 3 V2- NC 4 OUT 2 10 11 12 13 IN NC V1- NC NOTE: Case Voltage = Floating 9 NC IN HA-5002 (8 PIN METAL CAN) TOP VIEW HA-5002 (20 LD PLCC) TOP VIEW HA-5002 (8 LD SOIC) TOP VIEW FN2921.12 October 18, 2013 HA-5002 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 44V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V1+ to V1Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±200mA Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . ±400mA Thermal Resistance θJA (°C/W) θJC (°C/W) Metal Can Package (Notes 3, 4) . . . . . 155 67 PLCC Package (Note 3). . . . . . . . . . . . 74 N/A SOIC Package (Note 3) . . . . . . . . . . . . 157 N/A Max Junction Temperature (Hermetic Packages, Note 2). . . . . +175°C Max Junction Temperature (Plastic Packages, Note 2). . . . . . . +150°C Max Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300°C (PLCC and SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 2. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below +175°C for the can packages, and below +150°C for the plastic packages. 3. For θJA is measured with the component mounted on an evaluation PC board in free air. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified Electrical Specifications TEST CONDITIONS PARAMETER HA-5002-2 TEMP (°C) MIN TYP HA-5002-5, -9 MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage 25 - 5 20 - 5 20 mV Full - 10 30 - 10 30 mV Average Offset Voltage Drift Full - 30 - - 30 - μV/°C Bias Current 25 - 2 7 - 2 7 μA Full - 3.4 10 - 2.4 10 μA Input Resistance Input Noise Voltage Full 1.5 3 - 1.5 3 - MΩ 10Hz-1MHz 25 - 18 - - 18 - μVP-P TRANSFER CHARACTERISTICS Voltage Gain (VOUT = ±10V) -3dB Bandwidth RL = 50Ω 25 - 0.900 - - 0.900 - V/V RL = 100Ω 25 - 0.971 - - 0.971 - V/V RL = 1kΩ 25 - 0.995 - - 0.995 - V/V RL = 1kΩ Full 0.980 - - 0.980 - - V/V VIN = 1VP-P 25 - 110 - - 110 - MHz 25 - 40 - - 40 - A/mA AC Current Gain OUTPUT CHARACTERISTICS Output Voltage Swing Output Current RL = 100Ω 25 ±10 ±10.7 - ±10 ±11.2 - V RL = 1kΩ, VS = ±15V Full ±10 ±13.5 - ±10 ±13.9 - V RL = 1kΩ, VS = ±12V Full ±10 ±10.5 - ±10 ±10.5 - V VIN = ±10V, RL = 40Ω 25 - 220 - - 220 - mA Full - 3 10 - 3 10 Ω 25 - <0.005 - - <0.005 - % MHz Output Resistance VIN = 1VRMS, f = 10kHz Harmonic Distortion TRANSIENT RESPONSE Full Power Bandwidth (Note 5) 25 - 20.7 - - 20.7 - Rise Time 25 - 3.6 - - 3.6 - ns Propagation Delay 25 - 2 - - 2 - ns Overshoot 25 - 30 - - 30 - % Slew Rate 25 1.0 1.3 - 1.0 1.3 - V/ns To 0.1% 25 - 50 - - 50 - ns Differential Gain RL = 500Ω 25 - 0.06 - - 0.06 - % Differential Phase RL = 500Ω 25 - 0.22 - - 0.22 - ° Settling Time 3 FN2921.12 October 18, 2013 HA-5002 VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS PARAMETER TEMP (°C) HA-5002-2 MIN TYP HA-5002-5, -9 MAX MIN TYP MAX UNITS POWER REQUIREMENTS Supply Current AV = 10V Power Supply Rejection Ratio 25 - 8.3 - - 8.3 - mA Full - - 10 - - 10 mA Full 54 64 - 54 64 - dB NOTE: Slew Rate 5. FPBW = -------------------------- ; V = 10V . 2πV P EAK P Test Circuit and Waveforms +15V V2+ V1+ RS IN OUT V2- V1-15V RL FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE VIN VIN VOUT VOUT RS = 50Ω, RL = 100Ω RS = 50Ω, RL = 1kΩ SMALL SIGNAL WAVEFORMS SMALL SIGNAL WAVEFORMS VIN VIN VOUT VOUT RS = 50Ω, RL = 100Ω RS = 50Ω, RL = 1kΩ LARGE SIGNAL WAVEFORMS LARGE SIGNAL WAVEFORMS 4 FN2921.12 October 18, 2013 HA-5002 Schematic Diagram V1+ R8 R9 RN1 Q19 R4 Q26 Q20 Q25 R10 V2+ R1 Q18 Q12 Q3 Q9 Q1 Q27 Q6 Q10 R5 Q7 IN R11 Q4 OUT RN2 Q21 Q5 Q11 Q15 Q2 Q22 Q8 Q23 Q24 Q17 Q16 Q13 Q14 R7 R12 V2- R6 R2 R3 RN3 V1- Application Information Short Circuit Protection Layout Considerations The output current can be limited by using the following circuit: The wide bandwidth of the HA-5002 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. V+ VR LIM = -------------------------- = -------------------------I OUTMAX I OUTMAX Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. Power Supply Decoupling For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01 to 0.1μF will minimize high frequency variations in supply voltage, while low frequency bypassing requires larger valued capacitors since the impedance of the capacitor is dependent on frequency. It is also recommended that the bypass capacitors be connected close to the HA-5002 (preferably directly to the supply pins). Operation at Reduced Supply Levels V+ V1+ IOUTMAX = 200mA (CONTINUOUS) RLIM V2+ OUT IN V2- V1- RLIM V- Capacitive Loading The HA-5002 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. Following the formula I = Cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. The HA-5002 can become unstable with small capacitive loads (50pF) if certain precautions are not taken. Stability is enhanced by any one of the following: a source resistance in series with the input of 50Ω to 1kΩ; increasing capacitive load to 150pF or greater; decreasing CLOAD to 20pF or less; adding an output resistor of 10Ω to 50Ω; or adding feedback capacitance of 50pF or greater. Adding source resistance generally yields the best results. The HA-5002 can operate at supply voltage levels as low as ±5V and lower. Output swing is directly affected as well as slight reductions in slew rate and bandwidth. 5 FN2921.12 October 18, 2013 HA-5002 1.8 MAXIMUM POWER DISSIPATION (W) 1.6 1.4 T JMAX – T A P DMAX = -------------------------------------------θ JC + θ CS + θ SA PLCC 1.2 Where: TJMAX = Maximum Junction Temperature of the Device CAN 1.0 TA = Ambient 0.8 θJC = Junction to Case Thermal Resistance SOIC 0.6 θCS = Case to Heat Sink Thermal Resistance θSA = Heat Sink to Ambient Thermal Resistance 0.4 QUIESCENT POWER DISSIPATION AT ±15V SUPPLIES 0.2 T JMAX – T A P DMAX = -------------------------------θ JA Graph is based on: 0.0 25 65 45 85 125 105 TEMPERATURE (°C) FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE Typical Application +12V V1+ V2+ RS RM 50Ω 50Ω VIN RG -58 VOUT VIN V1- RL 50Ω V2-12V VOUT FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM Typical Performance Curves 9 VS = ±15V, RS = 50Ω GAIN 0 -3 PHASE -6 0° -9 45° -12 90° -15 135° -18 180° 10 100 FREQUENCY (MHz) FIGURE 4. GAIN/PHASE vs FREQUENCY (RL = 1kΩ) 6 VOLTAGE GAIN (dB) 3 1 VS = ±15V, RS = 50Ω 6 PHASE SHIFT VOLTAGE GAIN (dB) 6 3 GAIN 0 -3 PHASE -6 0° -9 45° -12 90° -15 135° PHASE SHIFT 9 180° -18 1 10 100 FREQUENCY (MHz) FIGURE 5. GAIN/PHASE vs FREQUENCY (RL = 50Ω) FN2921.12 October 18, 2013 HA-5002 Typical Performance Curves (Continued) 0.994 0.998 VS = ±15V VS = ±15V 0.992 0.997 VOLTAGE GAIN (V/V) VOLTAGE GAIN (V/V) 0.990 0.988 VOUT = -10V TO +10V 0.986 0.984 0.982 0.980 0.978 VOUT = 0 TO +10V 0.996 0.995 0.994 VOUT = 0 TO -10V 0.993 0.992 0.976 0.974 -60 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 -20 20 40 60 80 100 120 7 VS = ±15V VS = ±15V 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 -60 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. BIAS CURRENT vs TEMPERATURE FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE 15 0 FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1kΩ) BIAS CURRENT (μA) OFFSET VOLTAGE (mV) -40 TEMPERATURE (°C) FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (RL = 100Ω) 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -60 0.991 -60 120 10 VS = ±15V, RLOAD = 100Ω VS = ±15V, IOUT = 0mA 14 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) 9 +VOUT -VOUT 13 12 8 7 6 5 4 11 -60 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE 7 3 -60 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 FIGURE 11. SUPPLY CURRENT vs TEMPERATURE FN2921.12 October 18, 2013 HA-5002 Typical Performance Curves (Continued) 10 VS = ±15V IOUT = 0mA 100K 8 -55°C IMPEDANCE (Ω) SUPPLY CURRENT (mA) 125°C, 25°C 6 4 ZIN 10K 1000 100 2 10 ZOUT 0 0 2 4 6 8 10 12 14 16 1 100K 18 1M SUPPLY VOLTAGE (±V) 100M FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY 80 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 15 RLOAD = 100Ω 70 60 PSRR (dB) VOUT MAX, VP-P AT 100kHz FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE TA = 25°C TA = 125°C, TA = -55°C 50 40 30 20 10 12 8 SUPPLY VOLTAGE (±V) 0 10K 5 100K 1M FREQUENCY (Hz) 10M 100M FIGURE 15. PSRR vs FREQUENCY FIGURE 14. VOUT MAXIMUM vs VSUPPLY 1500 150 1400 100 VOUT - VIN (mV) SLEW RATE (V/μs) 10M FREQUENCY (Hz) 1300 1200 1100 VS = ±15V TA = 25°C RL = 100 50 RL = 1K 0 -50 RL = 600 1000 -100 900 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE 8 18 -150 -10 -8 -6 -4 -2 0 2 4 INPUT VOLTAGE (VOLTS) 6 8 10 FIGURE 17. GAIN ERROR vs INPUT VOLTAGE FN2921.12 October 18, 2013 HA-5002 Die Characteristics TRANSISTOR COUNT: 27 SUBSTRATE POTENTIAL (POWERED UP): PROCESS: V1- Bipolar Dielectric Isolation Metallization Mask Layout HA-5002 IN V1- V1- (ALT) V1+ (ALT) V2+ V2- V1+ OUT For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN2921.12 October 18, 2013 HA-5002 Metal Can Packages (Can) T8.C MIL-STD-1835 MACY1-X8 (A1) REFERENCE PLANE A 8 LEAD METAL CAN PACKAGE e1 L L2 L1 INCHES SYMBOL ØD2 A A k1 Øe ØD ØD1 2 N 1 β Øb1 Øb F α k C L BASE AND SEATING PLANE BASE METAL Øb1 LEAD FINISH Øb2 SECTION A-A NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. MILLIMETERS MAX MIN MAX NOTES A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e Q MIN e1 0.200 BSC 5.08 BSC 0.100 BSC - 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 12.70 19.05 1 1.27 1 L 0.500 0.750 L1 - 0.050 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - - β 45o BSC 45o BSC 45o BSC 45o BSC N 8 8 α 3 3 4 Rev. 0 5/18/94 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. 10 FN2921.12 October 18, 2013 HA-5002 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N20.35 (JEDEC MS-018AA ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N 20 20 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 11 FN2921.12 October 18, 2013 HA-5002 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. 12 FN2921.12 October 18, 2013