DATASHEET Nineteen Output Differential Buffer for PCIe Gen3 9DB1933 Recommended Application Features/Benefits 19 output PCIe Gen3 zero-delay/fanout buffer • 8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment • 11 dedicated and 3 group OE# pins/Hardware control of the outputs • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled • Supports undriven differential outputs in Power Down mode for power management General Description The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features • 19 - 0.7V current mode differential HCSL output pairs Key Specifications • • • Cycle-to-cycle jitter <50ps Output-to-output skew < 150 ps PCIe Gen3 phase jitter < 1.0ps RMS Functional Block Diagram OE(17_18)# OE(15_16)# OE(14:5)#, OE_01234# 13 PLL (SS Compatible) DIF_IN DIF_IN# 19 DIF(18:0) HIGH_BW# CKPWRGD/PD# SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK Logic IREF IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 1 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 DIF_14 DIF_14# CKPWRGD/PD# DIF_15 DIF_15# OE_15_16# DIF_ 16 DIF_16# VDD GND DIF_17 DIF_17# DIF_18 DIF_18# OE_17_18# DIF_IN DIF_IN# SMB_A2_PLLBYP# Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF GNDA VDDA HIGH_BW# VDD DIF_0 DIF_0# DIF_1 DIF_1# GND VDD DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 9DB1933AKLF OE14# DIF_13# DIF_13 OE13# DIF_12# DIF_12 OE12# VDD GND DIF_11# DIF_11 OE11# DIF_10# DIF_10 OE10# DIF_9# DIF_9 OE9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SMB_A1 SMB_A0 DIF_8# DIF_8 OE8# DIF_7# DIF_7 OE7# GND VDD DIF_6# DIF_6 OE6# DIF_5# DIF_5 OE5# SMBDAT SMBCLK Power Down Functionality INPUTS CKPWRGD/ DIF_IN/ PD# DIF_IN# 1 Running 0 X OUTPUTS PLL State DIF/DIF# Running Hi-Z ON OFF Power Groups Pin Number VDD GND 3 2 5,11,27,47,63 10,28,46,64 Description PLL, Analog DIF clocks IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 2 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Pin Description PIN # PIN NAME PIN TYPE 1 IREF OUT 2 3 GNDA VDDA PWR PWR 4 HIGH_BW# IN 5 6 7 8 9 10 11 12 13 14 15 16 17 VDD DIF_0 DIF_0# DIF_1 DIF_1# GND VDD DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT OUT OUT 18 OE_01234# IN 19 20 SMBCLK SMBDAT IN I/O 21 OE5# IN 22 23 DIF_5 DIF_5# 24 OE6# 25 26 27 28 DIF_6 DIF_6# VDD GND 29 OE7# 30 31 DIF_7 DIF_7# 32 OE8# 33 34 35 36 DIF_8 DIF_8# SMB_A0 SMB_A1 OUT OUT IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT IN IN DESCRIPTION This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 3.3V input for selecting PLL Band Width 0 = High, 1= Low Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pairs 0, 1, 2, 3 and 4. 1 =disable outputs, 0 = enable outputs Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Active low input for enabling DIF pair 5. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 6. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. Active low input for enabling DIF pair 7. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 8. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output SMBus address bit 0 (LSB) SMBus address bit 1 IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 3 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Pin Description (cont.) PIN # PIN NAME PIN TYPE 37 OE9# IN 38 39 DIF_9 DIF_9# OUT OUT 40 OE10# IN 41 42 DIF_10 DIF_10# 43 OE11# 44 45 46 47 DIF_11 DIF_11# GND VDD 48 OE12# 49 50 DIF_12 DIF_12# 51 OE13# 52 53 DIF_13 DIF_13# 54 OE14# 55 56 DIF_14 DIF_14# 57 CKPWRGD/PD# 58 59 DIF_15 DIF_15# 60 OE_15_16# 61 62 63 64 65 66 67 68 DIF_ 16 DIF_16# VDD GND DIF_17 DIF_17# DIF_18 DIF_18# 69 OE_17_18# IN 70 71 DIF_IN DIF_IN# IN IN 72 SMB_A2_PLLBYP# IN OUT OUT IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT IN OUT OUT IN OUT OUT IN OUT OUT PWR PWR OUT OUT OUT OUT DESCRIPTION Active low input for enabling DIF pair 9. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 10. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 11. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. Power supply, nominal 3.3V Active low input for enabling DIF pair 12. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 13. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 14. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output A rising edge samples latched inputs and release Power Down Mode, a low puts the part into power down mode and tristates all outputs. 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 15 and 16. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 17, 18. 1 = tri-state outputs, 0 = enable outputs 0.7 V Differential TRUE input 0.7 V Differential Complementary Input SMBus address bit 2. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating. 0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used) IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 4 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP UNITS NOTES MAX 4.6 4.6 V V V V V GND-0.5 Except for SMBus interface SMBus clock and data pins VDD+0.5V 5.5V -65 Human Body Model 1,2 1,2 1 1 1 1 1 1 ° 150 125 C °C V 2000 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Ambient Operating Temperature TCOM Commmercial range Single-ended inputs, except SMBus, low Input High Voltage VIH threshold and tri-level inputs Single-ended inputs, except SMBus, low Input Low Voltage VIL threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = VDD I IN Input Current Input Frequency Pin Inductance Capacitance I INP Fibyp Fipll Lpin CIN CINDIF_IN MIN TYP MAX UNITS NOTES 1 0 70 °C 2 VDD + 0.3 V 1 GND - 0.3 0.8 V 1 -5 5 uA 1 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode 10 90 Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 166 110 7 5 2.7 MHz MHz nH pF pF 2 2 1 1 1,4 100 COUT Output pin capacitance 2.5 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.000 1.8 ms 1,2 Input SS Modulation Frequency f MODIN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 OE# Latency t LATOE# 4 12 cycles 1,3 Tdrive_PD# t DRVPD 300 us 1,3 Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs VILSMB VIHSMB VOLSMB I PULLUP VDDSMB t RSMB t FSMB 5 5 0.8 @ I PULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 5.5 1000 300 ns ns V V V mA V ns ns 1,2 1,2 1 1 1 1 1 1 1 f MAXSMB Maximum SMBus operating frequency 100 kHz 1,5 2.1 4 2.7 VDDSMB 0.4 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 5 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Clock Input Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage - DIF_IN VIHDIF Input Low Voltage - DIF_IN VILDIF Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 VSWING dv/dt I IN dtin J DIFIn Peak to Peak value Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement 300 0.4 -5 45 0 1450 8 5 55 125 mV V/ns uA % ps 1 1,2 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Slew rate Slew rate matching Trf ∆Trf CONDITIONS MIN TYP MAX UNITS NOTES V/ns 1, 2, 3 Scope averaging on 1 2 4 % Slew rate matching, Scope averaging on 20 1, 2, 4 Statistical measurement on single-ended signal Voltage High VHigh 660 789 850 1 using oscilloscope math function. (Scope averaging mV Voltage Low VLow -150 45 150 1 on) Measurement on single ended signal using absolute Max Voltage Vmax 834 1150 1 mV value. (Scope averaging off) Min Voltage Vmin -300 17 1 Vswing Vswing Scope averaging off 300 744 mV 1, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 380 550 mV 1, 5 ∆-Vcross Crossing Voltage (var) Scope averaging off 24 140 mV 1, 6 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). 2 Measured from differential waveform Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 3 4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% 1 PARAMETER SYMBOL CONDITIONS Operating Supply Current Powerdown Current I DD3.3OP I DD3.3PDZ All outputs active @100MHz, CL = Full load; All differential pairs tri-stated MIN TYP MAX 427 32 500 40 UNITS NOTES mA mA 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 6 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL MIN 2 0.7 tJPEAK tDC CONDITIONS -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode PLL Bandwidth BW PLL Jitter Peaking Duty Cycle Duty Cycle Distortion 45 TYP 3 1 1.4 49.5 MAX 4 1.4 2 55 tDCD Measured differentially, Bypass Mode @100MHz -2 1 2 UNITS NOTES MHz 1 MHz 1 dB 1 % 1,2 % Bypass Mode, nominal value @ 25°C, 3.3V, 2500 3700 4500 ps VT = 50% Skew, Input to Output PLL Mode, nominal value @ 25°C, 3.3V, tpdPLL 100 300 500 ps VT = 50% Input-to-Output Skew Variation in Bypass mode ∆tpd_BYP (over specified voltage / temperature operating DIF_IN, DIF [x:0] |500| |600| ps ranges) Input-to-Output Skew Variation in PLL mode ∆tpd_PLL (over specified voltage / temperature operating DIF_IN, DIF [x:0] |250| |350| ps ranges) tJPH DIF[X:0] Differential Phase Jitter (RMS Value) 2 10 ps Differential Spread Spectrum Tracking Error (peak tSSTERROR DIF[X:0] 40 80 ps to peak) tsk3 VT = 50% Skew, Output to Output 100 150 ps PLL mode 40 50 ps tjcyc-cyc Jitter, Cycle to cycle Additive Jitter in Bypass Mode 25 50 ps 1 Guaranteed by design and characterization, not 100% tested in production. CLOAD = 2pF 2 Measured from differential cross-point to differential cross-point 3 PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input. 4 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 5 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 6 VT = 50% of Vout 7 This parameter is deterministic for a given device 8 Measured with scope averaging on to find mean value. 9 Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 10 This parameter is measured at the outputs of two separate 9DB1933 devices driven by a single main clock. The 9DB1933's must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the 11 t is the period of the input clock 12 Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1933 devices This parameter is measured at the outputs of two separate 9DB1933 devices driven by a single main clock in Spread Spectrum mode. The 9DB1933's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear 13 This parameter is an absolute value. It is not a double-sided figure. tpdBYP IDT® Nineteen Output Differential Buffer for PCIe Gen3 1,2,5 1,2,4 1,2,3 1,2,4,6, 7,8,9, 13 1,2,3,6, 7,8,9, 13 1,7,10 1,7,12 1 1,2 1,2 1676A—07/12/10 7 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Electrical Characteristics - PCIe Phase Jitter Parameters TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Phase Jitter, PLL Mode SYMBOL t jphPCIeG1 t jphPCIeG2 t jphPCIeG3 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) t jphPCIeG1 Additive Phase Jitter, Bypass Mode t jphPCIeG2 t jphPCIeG3 PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) MIN TYP 44 MAX 86 1.4 3 2.5 3.1 0.6 1 3 5 0.02 0.1 0.2 0.3 0.04 0.1 UNITS Notes ps (p-p) 1,2,3 ps 1,2 (rms) ps 1,2 (rms) ps 1,2,4 (rms) ps (p-p) ps (rms) ps (rms) ps (rms) 1,2,3 1,2 1,2 1,2,4 1 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 2 IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 8 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol Definition DIF DIF 100 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 -SSC Short-term Average Minimum Absolute Period 9.99900 -ppm error Long-Term Average Minimum Absolute Period 9.99900 0ppm + ppm error Long-Term Average +SSC Short-term Average Lg+ Nominal Maximum Maximum Maximum 10.00000 10.00100 10.05130 10.17630 Period Period Units Notes ns 1,2,3 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol Definition DIF DIF 100 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock LgAbsolute Period Minimum Absolute Period 9.87400 -SSC Short-term Average Minimum Absolute Period -ppm error Long-Term Average Minimum Absolute Period 9.99900 0ppm + ppm error Long-Term Average +SSC Short-term Average Lg+ Nominal Maximum Maximum 10.00000 10.00100 Period Period Maximum 10.17630 Units Notes ns 1,2,3 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy requirements. The 9DB1933 itself does not contribute to ppm error. 3 Driven by SRC output of main clock, PLL or Bypass mode IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 9 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' IDT® Nineteen Output Differential Buffer for PCIe Gen3 PCI Express Add-in Board REF_CLK Input L3 1676A—07/12/10 10 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® Nineteen Output Differential Buffer for PCIe Gen3 PCIe Device REF_CLK Input 1676A—07/12/10 11 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 General SMBus serial interface information for the 9DB1933 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address DC(h) WRite WR Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address DC(h) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(h) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK P X Byte ACK stoP bit Byte N + X - 1 N P Not acknowledge stoP bit Note: Addresses show assumes pin 29 is low. IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 12 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Reserved Register Byte 0 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMBusTable: Output Control Register Byte 1 Pin # Name DIF_7 Bit 7 DIF_6 Bit 6 DIF_5 Bit 5 DIF_4 Bit 4 DIF_3 Bit 3 DIF_2 Bit 2 DIF_1 Bit 1 DIF_0 Bit 0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type R R R R R R R R 0 1 Default 1 1 1 1 1 0 1 1 Type RW RW RW RW RW RW RW RW 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 Enable Enable Enable Enable Enable Enable Enable Enable Default 1 1 1 1 1 1 1 1 SMBusTable: Output and PLL BW Control Register Byte 2 Pin # Name Control Function Type 0 1 see note PLL_BW# adjust RW High BW Low BW Bit 7 RW Bypass PLL see note BYPASS# test mode / PLL Bit 6 DIF_13 Output Control RW Hi-Z Enable Bit 5 DIF_12 Output Control RW Hi-Z Enable Bit 4 DIF_11 Output Control RW Hi-Z Enable Bit 3 DIF_10 Output Control RW Hi-Z Enable Bit 2 DIF_9 Output Control RW Hi-Z Enable Bit 1 DIF_8 Output Control RW Hi-Z Enable Bit 0 Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function Readback - OE9# Input Bit 7 Readback - OE8# Input Bit 6 Readback - OE7# Input Bit 5 Readback - OE6# Input Bit 4 Readback - OE5# Input Bit 3 Readback - OE_01234# Input Bit 2 8 Readback - HIGH_BW# In Bit 1 72 Readback - SMB_A2_PLLBYP# In Bit 0 IDT® Nineteen Output Differential Buffer for PCIe Gen3 Type R R R R R R R R 0 1 Readback Readback Readback Readback Readback Readback Readback Readback Default 1 1 1 1 1 1 1 1 Default X X X X X X X X 1676A—07/12/10 13 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Control Function 69 Readback OE17_18# Input Bit 7 Readback - OE15_16# Input 60 Bit 6 Reserved Bit 5 54 Readback - OE14# Input Bit 4 51 Readback - OE13# Input Bit 3 48 Readback - OE12# Input Bit 2 43 Readback - OE11# Input Bit 1 Readback - OE10# Input 40 Bit 0 Type R R 0 R R R R R Type R R R R R R R R 0 - SMBusTable: DEVICE ID (194 Decimal or C2 Hex) Byte 6 Pin # Name Control Function Device ID 7 (MSB) Bit 7 Device ID 6 Bit 6 Device ID 5 Bit 5 Device ID 4 Bit 4 Device ID 3 Bit 3 Device ID 2 Bit 2 Device ID 1 Bit 1 Device ID 0 Bit 0 Type RW RW RW RW RW RW RW RW 0 Type RW RW RW Writing to this register RW configures how many RW bytes will be read back. RW RW RW 0 - Control Function IDT® Nineteen Output Differential Buffer for PCIe Gen3 Default X X 0 X X X X X 1 - Default 0 0 0 1 0 0 0 1 1 Default 1 1 0 0 0 0 1 0 1 - Default 0 0 0 0 0 1 1 1 Readback Readback Readback Readback Readback SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name Control Function RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 1 Readback Readback Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1676A—07/12/10 14 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 SMBusTable: Output Control Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 DIF_18 Bit 4 DIF_17 Bit 3 DIF_16 Bit 2 DIF_15 Bit 1 DIF_14 Bit 0 Control Function RESERVED RESERVED RESERVED Output Control Output Control Output Control Output Control Output Control Type 0 1 RW RW RW RW RW Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Enable Enable Enable Enable Enable SMBusTable: Reserved Register Byte 9 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Type 0 1 Default 1 X X 1 1 1 1 1 Default 0 0 0 0 0 1 0 1 SMBus Address Mapping SMBus Address (Hex) D0 D2 D4 D6 D8 DA DC DE Note: Main Clock (CKxxx) 9DB233 9DB433 9DB633 9DB833 9DB1233 9DB1933 Indicates Bypass Mode. PLL is OFF. IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 15 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 (Ref.) Seating Plane (N D -1)x e (Ref.) A1 Index Area ND & N Even A3 N L N 1 Anvil Singulation 2 OR E2 Chamfer 4x 0.6 x 0.6 max OPTIONAL (N -1)x e (Ref.) E2 b (Re f.) A D are Even 2 Sawn Singulation Top V iew (T yp.) e 2 If N & N D e ND & N Odd Thermal Base D2 2 D2 0. 08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS (mm) DIMENSIONS SYMBOL N ND NE 72L 72 18 18 SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC 10.00 x 10.00 5.75 6.15 5.75 6.15 0.3 0.5 Ordering Information Part / Order Number 9DB1933AKLF 9DB1933AKLFT Shipping Packaging Tubes Tape and Reel Package 72-pin MLF 72-pin MLF Temperature 0 to +70°C 0 to +70°C “LF” after the package code denotes the Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). IDT® Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10 16 9DB1933 Nineteen Output Differential Buffer for PCIe Gen3 Revision History Rev. 0.1 Issue Date 7/7/2010 Who RDW A 7/12/2010 RDW Description Initial release 1. Updated 'PWD' to 'Default' in SMBus column headings 2. Updated electrical tables with char data 3. Added SMBusAddressing Table to page 15 Page # 5-8,13-15 Innovate with IDT and accelerate your future networks. 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