SiC772CD Datasheet

SiC772CD
Vishay Siliconix
DrMOS Integrated Power Stage
DESCRIPTION
FEATURES
The SiC772 is an integrated power stage solution optimized
for synchronous buck applications to offer high current, high
efficiency and high power density performance. Packaged in
Vishay’s proprietary 6 mm x 6 mm MLP package, SiC772
enables voltage regulator design to deliver in excess of 40 A
per phase current.
The internal Power MOSFETs utilizes Vishay’s state-of-theart TrenchFET Gen IV technology that delivers industry
bench-mark performance to significantly reduce switching
and conduction losses.
The SiC772 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, and integrated bootstrap Schottky diode;
a thermal warning (THWn) alerts the system of excessive
junction temperature. This driver is also compatible with wide
range of PWM controllers with the support of Tri-state PWM,
5 V PWM Logic, and skip mode (SMOD) for improve light
load efficiency.
• Thermally enhanced PowerPAK MLP6x6-40L
Available
package
• Industry benchmark MOSFET with integrated
Available
Schottky diode
• Delivers in excess of 40 A continuous current
• 86 % peak efficiency at 19 V to 1 V and 18 A
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 19 V input stage
• 5 V PWM Logic with Tri-state and hold-off
• SMOD logic for light load efficiency boost
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Faster enable/disenable (10 ns)
• VCIN UVLO
• Compliant with Intel DrMOS 4.0 specification
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
Note:
* This datasheet provides information about parts that are
RoHS-compliant and/or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information/tables in this datasheet for details.
APPLICATIONS
•
•
•
•
Synchronous buck converters
Multi-phase VRDs for CPU, GPU, and memory
DC/DC POL modules
Notebook computers
TYPICAL APPLICATION DIAGRAMM
VIN
5V
VIN
GH
VDRV
BOOT
VCIN
SMOD
VSHW
PWM
Controller
DSBL#
PWM
Gate
Driver
VOUT
PHASE
THWn
PGND
GL
CGND
Figure 1: SiC772 Typical Application Diagram
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
For technical questions, contact: [email protected]
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
Vishay Siliconix
SMOD 1
VCIN 2
32 VSWH
31 VSWH
33 VSWH
35 VSWH
34 VSWH
36 GL
37 CGND
38 THWn
40 PWM
39 DSBL#
PIN CONFIGURATION
30 VSWH
29 VSWH
28 PGND
27 PGND
26 PGND
25 PGND
24 PGND
23 PGND
22 PGND
21 PGND
CGND
P1
VDRV 3
BOOT 4
CGND 5
GH 6
PHASE 7
VIN 8
VIN 9
VIN 10
VSWH
P3
PGND 20
PGND 18
PGND 19
PGND 17
VSWH 15
PGND 16
VIN 13
VIN 14
VIN 11
VIN 12
VIN
P2
Figure 2 - SiC772 Pin Configuration
PIN DESCRIPTION
Pin Number
Symbol
Description
1
SMOD#
2
VCIN
Supply voltage for internal logic circuitry
3
VDRV
Supply voltage for internal gate driver
4
BOOT
High side driver bootstrap voltage
5, 37, P1
CGND
Analog ground for the driver IC
LS FET Turn-OFF Logic. Active low
6
GH
7
PHASE
High side gate signal
8 to 14, P2
VIN
15, 29 to 35, P3
VSWH
Phase node of the power stage
16 to 28
PGND
Power ground
36
GL
Return path of HS Gate Driver
Power stage input voltage. Drain of high side MOSFET
Low side gate signal
38
THWn
Thermal warning open drain output
39
DSBL#
Disable pin. Active low
40
PWM
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2
PWM input logic
For technical questions, contact: [email protected]
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
Vishay Siliconix
ORDERING INFORMATION
Part Number
Package
SiC772CD-T1-GE3
Marking Code
PowerPAK MLP66-40L
SiC772DB
SiC772CD
Reference Board
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Limits
Input Voltage
VIN
- 0.3 to 30
Control Input Voltage
VCIN
- 0.3 to 7
Drive Input Voltage
VDRV
- 0.3 to 7
Switch Node (DC)
VSW
- 0.3 to 30
Switch Node (AC) (2)
VSW
- 8 to 35
VBS
- 0.3 to 33
VBS_SW
- 0.3 to 7
Electrical Parameter
Boot Voltage (DC Voltage)
Boot to Switching Node (DC Voltage)
Unit
V
- 0.3 to VCIN + 0.3
All Logic Inputs and Outputs (PWM, DSBL, SMOD and THWn)
Max. Operating Junction Temperature
TJ
150
Ambient Temperature
TA
- 40 to 125
Storage Temperature
°C
- 65 to 150
Note:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The specification values indicated "AC" is VSW to PGND - 8 V (< 20 ns, 10 µJ), min. and 35 V (< 50 ns), max.
RECOMMENDED OPERATING CONDITIONS
Parameter
Min.
Typ.
Max.
Input Voltage (VIN)
4.5
Drive Input Voltage (VDRV)
4.5
5
5.5
Control Input Voltage (VCIN)
4.5
5
5.5
Unit
24
Switching Node (LX, DC Voltage)
V
27
BOOT-SW
4
4.5
5.5
THERMAL RESISTANCE RATINGS
Parameter
Min.
Thermal Resistance from Junction to Case (to P3 PAD (VSHW)
Thermal Resistance from Junction to PCB
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
Typ.
2.5
5
For technical questions, contact: [email protected]
Max.
Unit
°C/W
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SiC772CD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VDSBL# = VSMOD = 5 V,
VIN = 19 V, VDRV = VCIN = 5 V,
TA = 25 °C
Min.
Typ.(3) Max.(5)
Unit
Power Supplies
VDSBL# = 0 V, no switching
VCIN Control Input Current
IVCIN
Drive Input Current (Dynamic)
IVDRV
100
VDSBL# = 5 V, no switching
300
VDSBL# = 5 V, fs = 300 kHz, D = 0.1
300
fs = 300 kHz, D = 0.1
16
fs = 1 MHz, D = 0.1
60
VDSBL# = 0 V, no switching
30
VDSBL# = 5 V, no switching
60
µA
25
mA
µA
Bootstrap Supply
Bootstrap Switch Forward Voltage
VF
VCIN = 5 V, forward bias current 2 mA
0.4
V
PWM Control Input
Rising Threshold
PWMth_r
3.4
3.7
4.2
Falling Threshold
PWMth_f
0.7
0.9
1.2
Tri-state Voltage
Vtri
PWM pin floating
2.3
V
Tri-state Falling Threshold
Vtri_th_f
0.9
1.2
1.5
Tri-state Rising Threshold
Vtri_th_r
3
3.4
3.7
Tri-state Rising Threshold Hysteresis
Vtri_hys_r
225
Tri-state Falling Threshold Hysteresis
Vtri_hys_f
325
PWM Input Current
IPWM
mV
VPWM = 5 V
500
VPWM = 0 V
- 500
µA
Notes:
3. Typical limits are established by characterization and are not production tested.
4. Guaranteed by design.
5. Min. and max. not 100 % production tested.
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For technical questions, contact: [email protected]
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VDSBL# = VSMOD = 5 V,
VIN = 19 V, VVDRV = VVCIN = 5 V,
TA = 25 °C
Min.
Enable
2
Typ.(3)
Max.(5)
Unit
DSBL#, SMOD INPUT
DSBL# Logic Input Voltage
SMOD Logic Input Voltage
VDSBL
VSMOD
Disenable
High State
0.8
2
Low State
V
0.8
Protection
Under Voltage Lockout
VUVLO
Rising, on Threshold
Falling, off Threshold
3.7
2.7
3.2
Under Voltage Lockout Hysteresis
550
THDn Flag Set(4)
160
THDn Flag Clear(4)
135
THDn Flag Hysteresis(4)
25
THDn Output Low
0.02
4.3
V
mV
°C
V
Timing Specifications
Tri-State to GH/GL Rising
Propagation Delay
Tri-state Hold-off Time
GH - Turn off Propagation Delay
tpd_r_tri
20
ttsho
150
20
tpd_off_GH
No load, see fig.4
GH - Turn on Propagation Delay
(Dead Time Rising)
tpd_on_GH
GL - Turn off Propagation Delay
tpd_off_GL
10
GL - Turn on Propagation Delay
(Dead Time Falling)
tpd_on_GL
10
10
ns
Notes:
3. Typical limits are established by characterization and are not production tested.
4. Guaranteed by design.
5. Min. and max. not 100 % production tested.
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
For technical questions, contact: [email protected]
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the
VR controller IC. The PWM input is designed to be
compatible with standard controllers using two state logic
(H and L) and advanced controllers that incorporate Tri-state
logic (H, L, and Tri-state) on the PWM output. For two state
logic, the PWM input operates as follows. When PWM is
driven above Vth_pwm_r the low side is turned OFF and the
high side is turned ON. When PWM input is driven below
Vth_pwm_f the high side turns off and the low side turns on.
For Tri-state logic, the PWM input operates as above for
driving the MOSFETs. However, there is an third state
that is entered into as the PWM output of Tri-state
compatible controller enters its high impedance state during
shut-down. The high impedance state of the controller's
PWM output allows the SiC772 to pull the PWM input
into the Tri-state region (see the Tri-state Voltage
Threshold Diagram below). If the PWM input stays in this
region for the Tri-state hold-off period, tTSHO, both high side
and low side MOSFETs are turned off. This function allows
the VR phase to be disabled without negative output voltage
swing caused by inductor ringing and saves a schottky diode
clamp. The PWM and Tri-state regions are separated
by hysteresis to prevent false triggering. The SiC772CD
incorporates PWM voltage thresholds that are compatible
with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFET. In this
state, the standby current is minimized. If DSBL# is
left unconnected an internal pull-down resistor will pull the
pin down to CGND and shut down the IC.
Diode Emulation Mode (SMOD) Skip
When SMOD pin is low the diode emulation mode is enabled
and GL is turned off. This is a non-synchronous conversion
mode
that
improves
light
load
efficiency
by
reducing switching losses. Conducted losses that occur in
synchronous buck regulators when inductor current
is negative can also be reduced. Circuitry in the external
controller IC detects when inductor current crosses zero and
drive SMOD Lo turning the low side MOSFET off. See SMOD
Operation diagram for additional details. If SMOD is left
unconnected, an internal pull up resistor will pull the pin up to
VCIN (Logic High) to disable the SMOD function.
Thermal Shutdown Warning (THDn)
The THDn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect a maximum of
20 k to pull this pin up to VCIN. An internal
temperature sensor detects the junction temperature.
The temperature threshold is 160 °C. When this
junction temperature is exceeded the THDn flag is set. When
the junction temperature drops below 135 °C the device will
clear the THDn signal. The SiC772 does not stop operation
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when the flag is set. The decision to shutdown must be made
by an external thermal control function.
Voltage Input (VIN)
This is the power input to the drain of the high-side
Power MOSFET. This pin is connected to the high
power intermediate BUS rail.
Switch Node (VSWH and PHASE)
The Switch node VSWH is the circuit PWM regulated output.
This is the output applied to the filter circuit to deliver
the regulated high output for the buck converter. The PHASE
pin is internally connected to the switch node VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20.2 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
Ground connections (CGND and PGND)
PGND (power ground) should be externally connected
to CGND (control signal ground). The layout of the
Printed Circuit Board should be such that the inductance
separating the CGND and PGND should be a minimum.
Transient differences due to inductance effects between
these two pins should not exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap switch and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one leg
tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC772 has an internal adaptive logic to avoid shoot
through
and
optimize
dead
time.
The
shoot
through protection ensures that both high-side and low-side
MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning on until the
other's gate voltage is sufficiently low (1 V), that and built in
delays ensure the one Power MOS is completely off, before
the other can be turned on. This feature helps to adjust dead
time as gate transitions change with respect to output current
and temperature.
For technical questions, contact: [email protected]
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
Vishay Siliconix
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the
logic circuitry can be safely activated. The SiC772 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of
the device. As an added precaution, a 20.2 k resistor
is connected between GH and PHASE to provide
a discharge path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
THWn
BOOT
VIN
GH
VDRV
Thermal Monitor
& Warning
VCIN
UVLO
DSBL#
+
VCIN
20K
PHASE
Vref = 1V
VSWH
PWM Logic
Control&
State
Machine
PWM
Anti- Cross
Conduction
Control Logic
GL
+
VDRV
Vref = 1V
CGND
GL
SMOD#
PGND
Figure 3: SiC772 Functional Block Diagram
DEVICE TRUTH TABLE
DSBL#
SMOD
PWM
GH
GL
Open
X
X
L
L
L
X
X
L
L
H
L
L
L
L
H
L
H
H
L
H
H
H
H
L
H
H
L
L
H
H
L
Tri-state
L
L
H
H
Tri-state
L
L
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
For technical questions, contact: [email protected]
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SiC772CD
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PWM TIMING DIAGRAM
PWMTH_R
PWMTri_F
PWMTri_R
PWMTH_F
PWM
TTSHO
TPD_OFF_GH
TPD_ON_GH
TPD_R_Tri
GH
TTSHO
TPD_OFF_GL
GL
TPD_R_Tri
TPD_ON_GL
Figure 4: Definition of PWM Logic and Tri-state
SMOD OPERATION DIAGRAM
PWM
PWM
0V
GH
IL
0V
GH
0A
IL
0A
10nS
GL
GL
SMOD#
SMOD#
Figure 5: CCM Operation with SMOD# = HIGH
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Figure 6: DCM Operation with SMOD# = Active Toggle
For technical questions, contact: [email protected]
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC772CD
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ELECTRICAL CHARACTERISTICS
VDRV/VCIN :5V/div
VDRV/VCIN :5V/div
VIN :10V/div
Vo:0.5V/div
PWM:5V/div
VIN :10V/div
Vo:0.5V/div
PWM:5V/div
t:2ms/div
t:20ms/div
Start-up with VIN Ramping Up
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 0 A
Power Off with VIN Ramping Down
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 1.2 A
DSBL#:2V/div
DSBL#:2V/div
Vo:0.5V/div
Vo:0.5V/div
VSWH:5V/div
VSWH:5V/div
t:20us/div
t:200us/div
Enable with VIN = 19 V,
VOUT = 1 V, fSW = 800 kHz, IOUT = 1.2 A
VDRV/VCIN :5V/div
Disable with VIN = 19 V,
VOUT = 1.2 V, fSW = 800 kHz, IOUT = 1.2 A
VDRV/VCIN :5V/div
VIN :10V/div
VIN :10V/div
Vo:0.5V/div
Vo:0.5V/div
PWM:5V/div
PWM:5V/div
t:100us/div
t:20us/div
PWM Start with VIN = 19 V,
VOUT = 1 V, fSW = 800 kHz, IOUT = 1.2 A
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
PWM Turn-off with VIN = 19 V,
VOUT = 1 V, fSW = 800 kHz, IOUT = 1.2 A
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ELECTRICAL CHARACTERISTICS
VIN :10V/div
VIN :10V/div
VDRV/VCIN :2V/div
VDRV/VCIN :2V/div
Vo:0.5V/div
Vo:0.5V/div
PWM:5V/div
PWM:5V/div
t:20ms/div
t:200us/div
Start-up with VDRV/VCIN Ramping Up
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 0 A
Power off with VDRV/VCIN Ramping Down
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 1.2 A
PWM:2V/div
PWM:2V/div
GH:5V/div
VSWH:5V/div
GL:2V/div
GH:5V/div
VSWH:5V/div
GL:2V/div
t:10ns/div
t:10ns/div
Switching Waveform at PWM Rising Edge
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 0 A
Switching Waveform at PWM Falling Edge
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 0 A
GH:5V/div
PWM:2V/div
GH:5V/div
VSWH:5V/div
PWM:2V/div
VSWH:5V/div
GL:2V/div
GL:2V/div
t:10ns/div
t:10ns/div
Switching Waveform at PWM Rising Edge
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 30 A
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Switching Waveform at PWM Falling Edge
VIN = 19 V, VOUT = 1 V, fSW = 800 kHz, IOUT = 30 A
For technical questions, contact: [email protected]
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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PACKAGE DIMENSIONS
K1
2x
5 6
Pin 1 dot
by marking
A
0.10 C A
D
A
K2
0.08 C
A1
Pin #1 dent
D2-1
0.41
A2
31
40
2x
30
1
21
10
E2-3
E2-1
4
E
0.10 M C A B
MLP66-40
(6 mm x 6 mm)
(Nd-1)X e
ref.
E2-2
e
0.10 C B
B
20
D2-2
D2-3
11
C
(Nd-1)X e
ref.
Top View
DIM
Bottom View
Side View
MILLIMETERS
INCHES
Min.
Nom.
Max.
Min.
Nom.
Max.
A(8)
0.70
0.75
0.80
0.027
0.029
0.031
A1
0.00
-
0.05
0.000
-
0.002
A2
b(4)
0.20 ref.
0.20
0.25
0.008 ref.
0.30
0.078
0.098
D
6.00 BSC
0.236 BSC
e
0.50 BSC
0.019 BSC
E
6.00 BSC
L
0.35
0.40
0.011
0.236 BSC
0.45
0.013
0.015
N(3)
40
40
Nd(3)
10
10
Ne(3)
10
0.017
10
D2-1
1.45
1.50
1.55
0.057
0.059
0.061
D2-2
1.45
1.50
1.55
0.057
0.059
0.061
D2-3
2.35
2.40
2.45
0.095
0.094
0.096
E2-1
4.35
4.40
4.45
0.171
0.173
0.175
E2-2
1.95
2.00
2.05
0.076
0.078
0.080
E2-3
1.95
2.00
2.05
0.076
0.078
0.080
K1
0.73 BSC
0.028 BSC
K2
0.21 BSC
Notes:
1. Use millimeters as the primary measurement.
0.008 BSC
2. Dimensioning and tolerances conform to ASME Y14.5M-1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction .
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body .
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63822.
Document Number: 63822
S13-1024-Rev. B, 10-Jun-13
For technical questions, contact: [email protected]
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11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP66-40 Case Outline
2x
5 6
Pin 1 dot
by marking
K1
0.08 C
A
0.10 C A
D
A
K2
A1
D2-1
0.41
A2
31
40
2x
30
1
21
10
E2-3
E2-1
4
E
0.10 M C A B
MLP66-40
(6 mm x 6 mm)
(Nd-1)X e
ref.
E2-2
e
0.10 C B
B
20
D2-2
D2-3
11
C
(Nd-1)X e
ref.
Top View
DIM.
Bottom View
Side View
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
A (8)
0.70
0.75
0.80
0.027
0.029
0.031
A1
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b (4)
0.20 ref.
0.20
0.25
0.008 ref.
0.098
D
6.00 BSC
0.236 BSC
e
0.50 BSC
0.019 BSC
E
6.00 BSC
0.236 BSC
L
0.35
0.40
MAX.
0.45
0.013
0.015
N (3)
40
40
Nd (3)
10
10
Ne (3)
10
0.011
0.017
10
D2-1
1.45
1.50
1.55
0.057
0.059
0.061
D2-2
1.45
1.50
1.55
0.057
0.059
0.061
D2-3
2.35
2.40
2.45
0.095
0.094
0.096
E2-1
4.35
4.40
4.45
0.171
0.173
0.175
E2-2
1.95
2.00
2.05
0.076
0.078
0.080
E2-3
1.95
2.00
2.05
0.076
0.078
0.080
K1
0.73 BSC
0.028 BSC
K2
0.21 BSC
0.008 BSC
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Document Number: 64846
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 12-Jan-15
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Revision: 02-Oct-12
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Document Number: 91000