SiC770CD www.vishay.com Vishay Siliconix DrMOS Integrated Power Stage DESCRIPTION FEATURES The SiC770 is an integrated power stage solution optimized for synchronous buck applications to offer high current, high efficiency and high power density performance. Packaged in Vishay’s proprietary 6 mm x 6 mm MLP package, SiC770 enables voltage regulator design to deliver in excess of 40 A per phase current. • Industry benchmark MOSFET with integrated Schottky diode The internal power MOSFETs utilizes Vishay’s state-of-the-art TrenchFET Gen IV technology that delivers industry bench-mark performance to significantly reduce switching and conduction losses. • Power MOSFETs optimized for 19 V input stage The SiC770 incorporates an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, and integrated bootstrap Schottky diode, a thermal warning (THWn) alerts the system of excessive junction temperature. This driver is also compatible with wide range of PWM controllers with the support of tri-state PWM, 5 V PWM logic, and skip mode (ZCD) for improve light load efficiency. • Built-in bootstrap Schottky diode • Delivers in excess of 40 A continuous current • 91 % peak efficiency • High frequency operation up to 1 MHz • 5 V PWM logic with tri-state and hold-off • Automatic skip mode operation (ZCD) for light load efficiency • Thermal monitor flag • VCIN under voltage lockout • Compliant with Intel DrMOS 4.0 specification • Thermally enhanced PowerPAK® MLP6x6-40L package • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Synchronous buck converters • Muliti-phase VRDs for CPU, GPU and memory • DC/DC POL modules TYPICAL APPLICATION DIAGRAM 5V VIN VIN GH VDRV BOOT PHASE VCIN ZCD_EN# SW PWM Controller DSBL # PWM VOUT Gate Driver THWn PGND GL CGND Fig. 1 - SiC770 Typical Application Diagram S13-1119-Rev. A, 27-May-13 Document Number: 62727 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix 31 VSWH 32 VSWH 33 VSWH 34 VSWH 35 VSWH 36 GL 37 CGND 38 THWn 39 DSBL# 40 PWM 39 DSBL# 38 THWn 37 CGND 36 GL 35 VSWH 34 VSWH 33 VSWH 32 VSWH 31 VSWH 40 PWM PINOUT CONFIGURATION ZCD_EN# 30 VSWH 30 VSWH ZCD_EN# VCIN 2 29 VSWH 29 VSWH VCIN 2 VDRV 3 28 PGND 28 PGND BOOT 4 27 PGND 27 PGND CGND 5 26 PGND 26 PGND GH 6 25 PGND 25 PGND PHASE 7 24 PGND 24 PGND 23 PGND 23 PGND VIN 9 22 PGND 22 PGND VIN 9 VIN 10 21 PGND 21 PGND VIN 10 CGND VSWH PGND 20 PGND 19 PGND 18 PGND 17 VIN 11 PGND 16 VIN 8 VIN 12 VIN 13 VIN 14 VSWH 15 PGND 16 VSWH 15 PHASE 7 VIN PGND 17 VIN 14 GH 6 PGND 18 VIN 13 CGND 5 VSWH PGND 19 VIN 11 BOOT 4 PGND 20 VIN 12 VIN VIN 8 VDRV 3 CGND Fig. 2 - SiC770 Pin Configuration PIN DESCRIPTION PIN# 1 NAME ZCD_EN# FUNCTION LS FET turn-off logic; active low 2 VCIN 3 VDRV 4 BOOT High side driver bootstrap voltage 5, 37, P1 CGND Analog ground for the driver IC 6 GH 7 PHASE 8 to 14, P2 VIN 15, 29 to 35, P3 VSWH 16 to 28 PGND Supply voltage for internal logic circuitry Supply voltage for internal gate driver High side gate signal Return path of HS gate driver Power stage input voltage. Drain of high side MOSFET Phase node of the power stage Power ground 36 GL Low side gate signal 38 THWn Thermal warning open drain output 39 DSBL# Disable pin; active low 40 PWM PWM input logic ORDERING INFORMATION PART NUMBER SiC770CD-T1-GE3 SiC770DB S13-1119-Rev. A, 27-May-13 PACKAGE MARKING CODE PowerPAK MLP66-40L SiC770CD Reference Board Document Number: 62727 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER SYMBOL LIMITS UNIT VIN - 0.3 to 30 V Control Input Voltage VCIN - 0.3 to 7 V Drive Input Voltage VDRV - 0.3 to 7 V Switch Node (DC) VSW - 0.3 to 30 V - 8 to 35 V VBS - 0.3 to 32 V VBS_SW - 0.3 to 7 V - 0.3 to VCIN + 0.3 V Input Voltage Switch Node (AC) (1) Boot Voltage (DC Voltage) Boot to Switching Node (DC Voltage) All Logic Inputs and Outputs (PWM, DSBL, SMOD, and THDN) Max. Operating Junction Temperature TJ 150 °C Ambient Temperature TA - 40 to 125 °C - 65 to 150 °C Storage Temperature Notes • Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (1) The specification values indicated “AC” is VSW to PGND - 8 V (< 20 ns, 10 μJ), minimum and 35 V (< 50 ns), maximum. RECOMMENDED OPERATING RANGE ELECTRICAL MIN. Input Voltage (VIN) 4.5 Drive Input Voltage (VDRV) 4.5 Control Input Voltage (VCIN) 4.5 TYP. MAX. UNIT 24 V 5 5.5 V 5 5.5 V 27 V 5.5 V Switching Node (LX, DC Voltage) BOOT-SW 4 4.5 THERMAL RESISTANCE Thermal Resistance from Junction to Case (to P3 PAD “VSWH”) Thermal Resistance from Junction to PCB S13-1119-Rev. A, 27-May-13 2.5 °C/W 5 °C/W Document Number: 62727 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (DSBL# = 5 V, SMOD = 5 V, VIN = 19 V, VDRV and VCIN = 5 V, TA = 25 °C) PARAMETER SYMBOL TEST CONDITIONS UNLESS SPECIFIED MIN. TYP. MAX. UNIT POWER SUPPLIES Control Logic Input Current IVCIN Drive Input Current (Dynamic) IVDRV BOOTSTRAP SUPPLY Bootstrap Switch Forward Voltage PWM CONTROL INPUT Rising Threshold Falling Threshold Tri-state Voltage Tri-state Rising Threshold Tri-state Falling Threshold Tri-state Rising Threshold Hysteresis Tri-state Falling Threshold Hysteresis PWM Input Current TIMING SPECIFICATIONS Tri-state to GH/GL Rising Propagation Delay Tri-state Hold-Off Time GH - Turn Off Propagation Delay GH - Turn ON Propagation Delay (Dead Time Rising) GL - Turn Off Propagation Delay GL - Turn ON Propagation Delay (Dead Time Falling) DSBL# Hi to GH/GL Rising Propagation Delay DSBL# Lo to GH/GL Falling Propagation Delay DSBL# , ZCD_EN# INPUT VF PWMTH_R PWMTH_F VTRI VTRI_TH_R VTRI_TH_F VTRI_HYS_R VTRI_HYS_F IPWM VDSBL# = 0 V, no switching VDSBL# = 5 V, no switching VDSBL# = 5 V, fS = 300 kHz, D = 0.1 fS = 300 kHz, D = 0.1 fS = 1 MHz, D = 0.1 21 350 500 14 40 VCIN = 5 V, forward bias current 2 mA 0.6 3.5 0.8 PWM pin floating 0.9 3.4 VPWM = 5 V VPWM = 0 V 3.9 1.0 2.3 1.3 3.7 280 180 250 - 250 μA mA V 4.2 1.2 1.8 4.0 V V V V V mV mV μA 20 150 20 ns ns ns 15 ns TPD_OFF_GL 20 ns TPD_ON_GL 20 ns TPD_R_DSBL TPD_F_DSBL 500 200 ns ns TPD_R_Tri TTSHO TPD_OFF_GH TPD_ON_GH DSBL# Logic Input Voltage VDSBL ZCD_EN# Logic Input Voltage VSMOD No load, see fig. 4 Enable Disenable High State Low State 2 0.8 2 0.8 V V PROTECTION Under Voltage Lockout Under Voltage Lockout Hysteresis THWn Flag Set(2) VUVLO Rising, On Threshold Falling, Off Threshold (2) 2.3 3.3 2.95 400 160 3.9 V mV °C THWn Flag Clear(2) 135 °C THWn Flag Hysteresis(2) 25 °C 0.02 V THWn Output Low Notes (1) Typical limits are established by characterization and are not production tested. (2) Guaranteed by design. (3) Min. and max. parameters are not 100 % production tested. S13-1119-Rev. A, 27-May-13 Document Number: 62727 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix DETAILED OPERATIONAL DESCRIPTION PWM Input with Tri-State Function Thermal Shutdown Warning (THWn) The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L, and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above Vth_pwm_r the low side is turned OFF and the high side is turned ON. When PWM input is driven below Vth_pwm_f the high side turns off and the low side turns on. For tri-state logic, the PWM input operates as above for driving the MOSFETs. However, there is an third state that is entered into as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC770 to pull the PWM input into the tri-state region (see the tri-state Voltage Threshold diagram below). If the PWM input stays in this region for the tri-state hold-off period, tTSHO, both high side and low side MOSFETs are turned off. This function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC770CD incorporates PWM voltage thresholds that are compatible with 5 V logic. The THWn pin is an open drain signal that flags the presence of excessive junction temperature. Connect a maximum of 20 k to pull this pin up to VCIN. An internal temperature sensor detects the junction temperature. The temperature threshold is 160 °C. When this junction temperature is exceeded the THWn flag is set. When the junction temperature drops below 135 °C the device will clear the THWn signal. The SiC770 does not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function. Disable (DSBL#) In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFET. In this state, the standby current is minimized. If DSBL# is left unconnected an internal pull-down resistor will pull the pin down to CGND and shut down the IC. Diode Emulation Mode (ZCD_EN#) Skip When ZCD_EN# pin is low the diode emulation mode is enabled. This is a non-synchronous conversion mode that improves light load efficiency by reducing switching losses. Conducted losses that occur in synchronous buck regulators when inductor current is negative are also reduced. Circuitry in the gate drive IC detects the inductor valley current when inductor current crosses zero and automatically stops switching the low side MOSFET. See ZCD_EN# operation diagram for additional details. This function can be also be used for a pre-biased output voltage. If ZCD_EN# is left un-connected, an internal pull up resistor will pull the pin up to VCIN (logic high) to disable the ZCD_EN# function. S13-1119-Rev. A, 27-May-13 Voltage Input (VIN) This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail. Switch Node (VSWH and PHASE) The switch node VSWH is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. The PHASE pin is internally connected to the switch node VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 k resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied. Ground connections (CGND and PGND) PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the printed circuit board should be such that the inductance separating the CGND and PGND should be a minimum. Transient differences due to inductance effects between these two pins should not exceed 0.5 V. Control and Drive Supply Voltage Input (VDRV, VCIN) VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gated rive noise into the IC. Bootstrap Circuit (BOOT) The internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin. Document Number: 62727 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix Shoot-Through Protection and Adaptive Dead Time (AST) Under Voltage Lockout (UVLO) During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC770 also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20.2 k resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. The SiC770 has an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFET are not turned on the same time. The adaptive dead time control operates as follows. The HS and LS gate voltages are monitored to prevent the one turning on until the other's gate voltage is sufficiently low (1.0 V), that and built in delays ensure the one Power MOS is completely off, before the other can be turned on. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. FUNCTIONAL BLOCK DIAGRAM VDRV GH VIN UVLO VCIN BOOT DSBL# PHASE Thermal Shutdown THWn ADT CNTL DCM DETECT VSWH Tristate PWM PWM ZCD_EN# PGND ńňŏŅ GL Fig. 3 - SiC770 Functional Block Diagram DEVICE TRUTH TABLE DSBL# SMOD PWM GH GL Open X X L L L X X L L H L L L H (IL > 0), L (IL 0) H L H H L H H H H L H H L L H S13-1119-Rev. A, 27-May-13 Document Number: 62727 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix PWM TIMING DIAGRAM PWMTH_R PWMTri_F PWMTri_R PWMTH_F PWM TPD_OFF_GL TTSHO GL TPD_OFF_GL TPD_R_Tri ġ TTSHO TPD_ON_GH TPD_OFF_GH TPD_R_Tri GH Fig. 4 - Definition of PWM Logic and Tri-State PWM TIMING DIAGRAM VIN VIN BOOT PHASE ZCD_EN# PWM Controller SW Gate Driver PWM ZCD PWM PWM VOUT Enable DSBL# DSBL# CS PGND CGND GH GH GL GL IL Sense t PWM ZCD_EN# t DSBL# Hi to GH Rising propagation delay High PWM Low IL = 0A DSBL# Hi to GL Rising propagation delay PWM Disable DSBL# DSBL# IL 0A GH GH GL GL HG t t DSBL# Lo to GH Falling propagation delay DSBL# Lo to GL Falling propagation delay LG Fig. 5 - ZCD_EN# Operation Timing Diagram S13-1119-Rev. A, 27-May-13 Fig. 6 - DSBL# Function Timing Diagram Document Number: 62727 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 96 94 fsw - 350KHz fsw - 350KHz 94 92 fsw - 800KHz 90 fsw - 800KHz 90 88 Efficiency (%) Efficiency (%) 92 fsw - 1MHz 86 88 fsw - 1MHz 86 84 84 350kHz 800kHz 1MHz 82 80 O/P Inductor IHLP-5050-FD 0.56uH DCR=1.20mΩ IHLP-5050-FD 0.22uH DCR=0.63mΩ IHLP-5050-FD 0.15uH DCR=0.53mΩ 0.1 1 Load (A) 350kHz 800kHz 1MHz 82 O/P Inductor IHLP-5050-FD 0.56uH DCR=1.20mΩ IHLP-5050-FD 0.22uH DCR=0.63mΩ IHLP-5050-FD 0.15uH DCR=0.53mΩ 80 0.1 10 1 4 2.5 3.75 2.45 3.5 2.4 3.25 Power Loss (W) Power Loss (W) 10 Efficiency Performance vs. fSW VIN = 19 V, VOUT = 1.8 V Efficiency Performance vs. fSW VIN = 12 V, VOUT = 1.8 V 3 2.75 2.5 2.25 2.35 2.3 2.25 2.2 2.15 2 2.1 200 300 400 500 600 700 Switching Frequency (KHz) 800 900 1000 5 Power Loss vs. Switching Frequency VIN = 19 V, VOUT = 1.8 V, IOUT = 15 A, Rboot = 4.7 , Inductance = 0.47 μH 7 9 11 13 15 Input Voltage (V) 17 19 Power Loss vs. Input Voltage VOUT = 1.8 V, IOUT = 15 A, fSW = 300 kHz, Rboot = 4.7 , Inductance = 0.47 μH 50 1.4 45 1.35 40 35 ICIN Current (mA) IDRV Current (mA) Load (A) 30 1.3 1.25 25 20 15 1.2 1.15 10 1.1 5 200 300 400 500 600 700 800 Switching Frequency (KHz) 900 1000 Driver Current vs. Switching Frequency VIN = 12 V, VOUT = 1.8 V, IOUT = 20 A, VCIN = VDRV = 5 V S13-1119-Rev. A, 27-May-13 200 300 400 500 600 700 800 Switching Frequency (KHz) 900 1000 VCIN Current vs. Switching Frequency VIN = 12 V, VOUT = 1.8 V, IOUT = 20 A, VCIN = VDRV = 5 V Document Number: 62727 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix Switching Waveform at PWM Rising Edge VIN = 19 V, VO = 1.8 V, IO = 20 A, fSW = 500 kHz Switching Waveform at PWM Falling Edge VIN = 19 V, VO = 1.8 V, IO = 20 A, fSW = 500 kHz Switching Waveform at ZCD_EN# - High VIN = 12 V, VO = 1.8 V, , IL = 1 A, fSW = 500 kHz Switching Waveform at ZCD_EN# - Low VIN = 12 V, VO = 1.8 V, , IL = DCM, ton = 200 ns DSBL# Hi to GH Rising Propagation Delay VIN = 12 V, ton = 200 ns, fSW = 500 kHz, IO = 0 A DSBL# Hi to GL Rising Propagation Delay VIN = 12 V, ton = 200 ns, fSW = 500 kHz, IO = 0 A S13-1119-Rev. A, 27-May-13 Document Number: 62727 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix DSBL# Lo to GH Falling Propagation Delay DSBL# Lo to GL Falling Propagation Delay S13-1119-Rev. A, 27-May-13 Document Number: 62727 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC770CD www.vishay.com Vishay Siliconix PACKAGE MECHANICAL DRAWING K1 2x 5 6 Pin 1 dot by marking 0.10 C A D A K2 0.08 C A A1 Pin #1 dent D2-1 0.41 A2 31 40 2x 30 1 21 10 E2-3 E2-1 4 E 0.10 M C A B MLP66-40 (6 mm x 6 mm) (Nd-1)X e ref. E2-2 e 0.10 C B B 20 D2-2 D2-3 11 C (Nd-1)X e ref. Top View DIM. Bottom View Side View MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.078 A2 b (4) 0.20 ref. 0.20 0.25 0.008 ref. 0.098 D 6.00 BSC 0.236 BSC e 0.50 BSC 0.019 BSC E 6.00 BSC L 0.35 0.40 MAX. 0.011 0.236 BSC 0.45 0.013 0.015 N (3) 40 40 Nd (3) 10 10 Ne (3) 10 0.017 10 D2-1 1.45 1.50 1.55 0.057 0.059 0.061 D2-2 1.45 1.50 1.55 0.057 0.059 0.061 D2-3 2.35 2.40 2.45 0.095 0.094 0.096 E2-1 4.35 4.40 4.45 0.171 0.173 0.175 E2-2 1.95 2.00 2.05 0.076 0.078 0.080 E2-3 1.95 2.00 2.05 0.076 0.078 0.080 K1 0.73 BSC 0.028 BSC K2 0.21 BSC 0.008 BSC Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62727. S13-1119-Rev. A, 27-May-13 Document Number: 62727 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® MLP66-40 Case Outline 2x 5 6 Pin 1 dot by marking K1 0.08 C A 0.10 C A D A K2 A1 D2-1 0.41 A2 31 40 2x 30 1 21 10 E2-3 E2-1 4 E 0.10 M C A B MLP66-40 (6 mm x 6 mm) (Nd-1)X e ref. E2-2 e 0.10 C B B 20 D2-2 D2-3 11 C (Nd-1)X e ref. Top View DIM. Bottom View Side View MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.078 A2 b (4) 0.20 ref. 0.20 0.25 0.008 ref. 0.098 D 6.00 BSC 0.236 BSC e 0.50 BSC 0.019 BSC E 6.00 BSC 0.236 BSC L 0.35 0.40 MAX. 0.45 0.013 0.015 N (3) 40 40 Nd (3) 10 10 Ne (3) 10 0.011 0.017 10 D2-1 1.45 1.50 1.55 0.057 0.059 0.061 D2-2 1.45 1.50 1.55 0.057 0.059 0.061 D2-3 2.35 2.40 2.45 0.095 0.094 0.096 E2-1 4.35 4.40 4.45 0.171 0.173 0.175 E2-2 1.95 2.00 2.05 0.076 0.078 0.080 E2-3 1.95 2.00 2.05 0.076 0.078 0.080 K1 0.73 BSC 0.028 BSC K2 0.21 BSC 0.008 BSC ECN: T14-0826-Rev. B, 12-Jan-15 DWG: 5986 Notes 1. Use millimeters as the primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Document Number: 64846 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 12-Jan-15 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000