IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: IDT74SSTU32865 DESCRIPTION: • • • • • • • 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in 160-pin CTBGA package The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32865 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32865 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PYTERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hard-wired to ground, in which case the set-up time requirement for DCS would be the same as for the other D data inputs. The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PYTERR pin (active low). APPLICATIONS: • Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs • Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE APRIL 2005 1 c 2005 Integrated Device Technology, Inc. DSC-6493/14 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:2) (CS ACTIVE) VREF D PARIN Q PARITY GENERATOR AND CHECKER 22 PYTERR R Q0A D D0 Q Q0B R Q21A D D21 Q Q21B R QCS0A DCS0 D Q QCS0B R CSGateEN QCS1A DCS1 D Q QCS1B R DCKE0, DCKE1 2 D 2 Q QCKE0B, QCKE1B R DODT0, DODT1 2 D QCKE0A, QCKE1A 2 Q QODT0A, QODT1A QODT0B, QODT1B R RESET CLK CLK 2 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 1 2 3 4 5 8 9 10 11 12 A VREF NC PARIN NC NC QCKE1A QCKE0A Q21A Q19A Q18A Q17B Q17A B D1 D2 NC NC NC QCKE1B QCKE0B Q21B Q19B Q18B QODT0B QODT0A C D3 D4 QODT1B QODT1A D D6 D5 VDDL GND NC NC GND GND Q20B Q20A E D7 D8 VDDL GND VDDL VDDR GND GND Q16B Q16A F D11 D9 VDDL GND VDDR VDDR Q1B Q1A G D18 D12 VDDL GND VDDR VDDR Q2B Q2A H CSGate EN D15 VDDL GND GND GND Q5B Q5A J CLK DCS0 GND GND VDDR VDDR QCS0B QCS0A K CLK DCS1 VDDL VDDL GND GND QCS1B QCS1A L RESET D14 GND GND VDDR VDDR Q6B Q6A M D0 D10 GND GND GND GND Q10B Q10A N D17 D16 VDDL VDDL VDDR VDDR Q9B Q9A P D19 D21 GND VDDL VDDL VDDR VDDR GND Q11B Q11A R D13 D20 GND VDDL VDDL GND GND GND Q15B Q15A Q14B Q14A T DODT1 DODT0 U DCKE0 DCKE1 V VREF MCL 6 7 MCL PYTERR MCH Q3B Q12B Q7B Q4B Q13B Q0B Q8B MCL NC MCH Q3A Q12A Q7A Q4A Q13A Q0A Q8A MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH. 160-BALL CTBGA TOP VIEW 3 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 160 BALL CTBGA PACKAGE ATTRIBUTES Top Mark 1 2 3 4 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V TOP VIEW BOTTOM VIEW SIDE VIEW 4 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs Outputs CSGate Dn, DODTn, RESET DCS0 DCS1 Enable CLK CLK H L L X ↑ ↓ H L L X ↑ ↓ H L L X L or H L or H H L H X ↑ H L H X ↑ DCKEn Qn QCS L L L L H H L H X Q0(2) Q0(2) Q0(2) ↓ L L L L ↓ H H L H (2) Q0(2) H L H X L or H L or H X Q0 H H L X ↑ ↓ L L H L H H L X ↑ ↓ H H H H (2) Q0 (2) QODT, QCKE Q0 (2) Q0(2) H H L X L or H L or H X Q0 H H H L ↑ ↓ L L H L H H H L ↑ ↓ H H H H (2) Q0 (2) Q0(2) H H H L L or H L or H X Q0 H H H H ↑ ↓ L Q0(2) H L H H H H ↑ ↓ H Q0(2) H H H H H H L or H L or H X Q0(2) Q0(2) Q0(2) L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating L L L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. Output level before the indicated steady-state conditions were established. 5 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE PARITY AND STANDBY FUNCTION TABLE(1) Inputs Output RESET DCS0 DCS1 CLK CLK Σ of Inputs = H (D0 - D21) PARIN(2) PYTERR(3) H L H ↑ ↓ Even L H H L H ↑ ↓ Odd L L H L H ↑ ↓ Even H L H L H ↑ ↓ Odd H H H H L ↑ ↓ Even L H H H L ↑ ↓ Odd L L H H L ↑ ↓ Even H L H H L ↑ ↓ Odd H H H H H ↑ ↓ X X PYTERR0(4) H X X L or H L or H X X PYTERR0(4) L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating H NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2. PARIN arrives one clock cycle after the data to which it applies 3. This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles, or until RESET is driven LOW. 4. Output level before the indicated steady-state conditions were established. 6 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE REGISTER TIMING n-1 n n +1 n+2 n+3 n+4 n+5 CLK CLK tSU tH Dn tSU tH PARIN tPDM, tPDMSS Qn tPDM tPDH PTYERR PARITY LOGIC DIAGRAM Dn 22 22 D Q QnA QnB D PARIN D D CLOCK NOTE: 1. This function holds the error for two cycles. See REGISTER TIMING diagram. 7 LATCHING AND (1) RESET FUNCTION PYTERR IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD VI (2,3) Description Supply Voltage Range Max. Unit –0.5 to 2.5 V Input Voltage Range –0.5 to 2.5 V VO(2,3) Output Voltage Range –0.5 to VDD +0.5 V IIK Input Clamp Current ±50 mA ±50 mA ±50 mA ±100 mA –65 to +150 °C VI < 0 VI > VDD IOK Output Clamp Current VO < 0 VO > VDD IO Continuous Output Current, VO = 0 to VDD VDD Continuous Current through each VDD or GND TSTG Storage Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V ± 0.1V Symbol Min. Max. Unit Clock Frequency — 270 MHz Pulse Duration, CLK, CLK HIGH or LOW 1 — ns tACT(1,2) Differential Inputs Active Time — 10 ns tINACT(1,3) Differential Inputs Inactive Time — 15 ns tSU Setup Time DCSn before CLK↑, CLK↓ 0.7 — ns Data, PARIN, DODT, and DCKE before CLK↑, CLK↓ 0.5 — tH Hold Time Data, DCSn, PARIN, DCKE, and DODT 0.5 — fCLOCK tw Parameter after CLK↑, CLK↓ NOTES: 1. This parameter is not production tested. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW. 8 ns IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TERMINAL FUNCTIONS Signal Group Terminal Name Ungated Inputs DCKE0, DCKE1 DODT0, DODT1 SSTL_18 DRAM function pins not associated with Chip Select Chip Select Gated Inputs D0:D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW Chip Select Inputs DCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN HIGH) when at least one Chip Select input is LOW. Re-Driven Outputs Q0A:Q21A Q0B:Q21B QCS0-1A, B QCKE0-1A, B QODT0-1A, B SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock Parity Input PARIN SSTL_18 Input parity is received on pin PARIN, and should maintain odd parity across the D0:D21 inputs, at the rising edge of the clock Parity Error Output PTYERR Open Drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Program Inputs CSGateEN 1.8V LVCMOS Chip Select Gate Enable. When HIGH, the D0:D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0:D21 inputs will be latched and redriven on every rising edge of the clock. Clock Inputs CLK, CLK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Miscellaneous MCL, MCH Inputs RESET 1.8V LVCMOS Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. VREF 0.9V nominal Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. Type Description Must be connected to a Logic LOW or HIGH. 9 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25ºC (1,2) Symbol Parameter Min. Typ. Max. Unit VDD Supply Voltage 1.7 — 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V V TT Termination Voltage VREF– 40mV VREF VREF+ 40mV V VI Input Voltage VIH AC High-Level Input Voltage Data Inputs 0 — VDD V VREF+ 250mV — — V VIL AC Low-Level Input Voltage Data Inputs — — VREF– 250mV V VIH DC High-Level Input Voltage Data Inputs VREF+ 125mV — — V VIL DC Low-Level Input Voltage Data Inputs — — VREF– 125mV V VIH High-Level Input Voltage RESET, Cx 0.65 * VDD — — V VIL Low-Level Input Voltage RESET, Cx — — 0.35 * VDD V VICR Common Mode Input Voltage CLK, CLK 0.675 — 1.125 V VID Differential Input Voltage CLK, CLK 600 — — mV IOH High-Level Output Current — — –8 mA IOL Low-Level Output Current — — 8 mA TA Operating Free-Air Temperature 0 — 70 °C NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V Symbol Test Conditions Min. Typ. VOH VDD = 1.7V to 1.9V, IOH = – 6 mA 1.2 VOL VDD = 1.7V to 1.9V, IOL = 6 mA — II IDD IDDD Parameter Max. Unit — — V — 0.5 V All Inputs VI = VDD or GND — — ±5 μA Static Standby IO = 0, VDD = 1.9V, RESET = GND — — 200 μA Static Operating IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) — — 40 mA Dynamic Operating IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), — — — μA/Clock (Clock Only) CLK and CLK Switching 50% Duty Cycle. 1:1 Mode — — — 1:2 Mode — — — 2.5 — 3.5 IO = 0, VDD = 1.8V, RESET = VDD, Dynamic Operating VI = VIH (AC) or VIL (AC), CLK and CLK Switching at (Per Each Data Input) 50% Duty Cycle. One Data Input Switching at MHz μA/Clock Half Clock Frequency, 50% Duty Cycle. Dn CI VI = VREF ± 250mV, VDD = 1.8V DCSn and CSGateENable Input 4 — 6 CLK and CLK VICR = 0.9V, VID = 600mV, VDD = 1.8V 4 — 6 RESET VI = VDD or GND, VDD = 1.8V 2 — 6 10 MHz/Data pF IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V ± 0.1V Symbol Parameter Min Max. Unit 270 — MHz CLK and CLK to Q 1.41 2.15 ns tLH LOW to HIGH Delay, CLK and CLK to PYTERR 1.2 3 ns tHL HIGH to LOW Delay, CLK and CLK to PYTERR 1 3 ns tPLH LOW to HIGH Propagation Delay, RESET to PYTERR — 3 ns CLK and CLK to Q (simultaneous switching) — 2.35 ns fMAX tPDM(2) tPDMSS(2,3) RESET to Q — 3 ns dV/dt_r tRPHL Output slew rate from 20% to 80% 1 4 V/ns dV/dt_f Output slew rate from 20% to 80% 1 4 V/ns dV/dt_Δ(4) Output slew rate from 20% to 80% — 1 V/ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 11 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) VDD DUT RL = 1KΩ TL = 50Ω CLK CLK CLK Inputs TL = 350ps, 50Ω Test Point Out CL = 30 pF RL = 1KΩ Test Point RL = 100Ω Load Circuit Test Point VDD LVCMOS RESET Input VDD/2 VDD/2 0V CLK tACT tINACT 90% IDD VICR VICR CLK tPLH VID tPHL VOH 10% Output VTT VTT VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times tW Input VICR VICR VID LVCMOS RESET Input Voltage Waveforms - Pulse Duration VIH VDD/2 VIL tRPHL VOH Output VTT VOL CLK VICR VID CLK Voltage Waveforms - Propagation Delay Times tSU tH VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. 12 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) VDD DUT RL = 50Ω Out Test Point CL = 10 pF Load Circuit: High-to-Low Slew-Rate Output VOH 80% 20% dv_f VOL dt_f Voltage Waveforms: High-to-Low Slew-Rate DUT Out Test Point CL = 10 pF RL = 50Ω Load Circuit: Low-to-High Slew-Rate dt_r VOH dv_r 80% 20% VOL Output Voltage Waveforms: Low-to-High Slew-Rate NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 13 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V) VDD DUT RL = 1KΩ Out Test Point CL = 10 pF Load Circuit: High-to-Low Slew-Rate LVCMOS RESET Input VDD VDD/2 0V tPLH VOH 0.15V Output Waveform 2 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to RESET Input) Timing Inputs VICR VICR VI(PP) tHL VDD Output Waveform 1 VDD/2 VOL Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with Respect to Clock Inputs) Timing Inputs VICR VICR VI(PP) tHL VOH Output Waveform 2 0.15V 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to Clock Inputs) NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 14 IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXX XX SSTU32 Temp. Range Device Type Package BKG Thin Profile, Fine Pitch, Ball Grid Array - Green 865 28-Bit 1:2 Registered Buffer with Parity 74 0°C to +70°C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 15 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com