IDT IDT77V1253

TRIPLE PORT PHY (PHYSICAL LAYER)
FOR 25.6 AND 51.2 MBPS ATM NETWORKS
IDT77V1253
FEATURES:
DESCRIPTION:
• Performs the PHY-Transmission Convergence (TC) and Physical
Media Dependent (PMD) Sublayer functions for three 25.6 Mbps
ATM channels
• Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
• Also operates at 51.2Mbps
• UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
• 3-Cell Transmit & Receive FIFOs
• LED Interface for status signalling
• Supports UTP Category 3 physical media
• Interfaces to standard magnetics
• Low-Power CMOS
• 3.3V supply with 5V tolerant inputs
• 144-pin PQFP Package (28 x 28 mm)
The IDT77V1253 is a member of IDT's family of products supporting
Asynchronous Transfer Mode (ATM) data communications and networking.
The IDT77V1253 implements the physical layer for 25.6 Mbps ATM, connecting three serial copper links (UTP Category 3) to one ATM layer device such
as a SAR or a switch ASIC. The IDT77V1253 also operates at 51.2 Mbps, and
is well suited to backplane driving applications.
The 77V1253-to-ATM layer interface is selectable as one of three options:
16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or triple 4-bit DPI
(Data Path Interface).
The IDT77V1253 is fabricated using IDT's state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with
the low-power consumption characteristics of CMOS.
FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE
TxREF
TxCLK
TxDATA[15:0]
TxPARITY
TxSOC
TxEN
TxCLAV
TxADDR[4:0]
MODE[1:0]
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Driver
+
Tx 0
-
Clock/Data
Recovery
+
Rx 0
-
Driver
+
Tx 1
-
Clock/Data
Recovery
+
Rx 1
-
Driver
+
- Tx 2
Clock/Data
Recovery
+
- Rx 2
PHY-ATM
Interface
(UTOPIA or DPI)
RxADDR[4:0]
RxCLK
RxDATA[15:0]
RxPARITY
RxSOC
RxEN
RxCLAV
Tx/Rx ATM
Cell FIFO
P/S and S/P
NRZI
INT
RST
RD
WR
CS
Microprocessor
(Utility Bus)
Interface
Tx/Rx ATM
Cell FIFO
AD[7:0]
P/S and S/P
NRZI
ALE
3
OSC
RxREF
RxLED[2:0]
3
TxLED[2:0]
4781 drw 01
DECEMBER 2004
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
 2004
Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.
DSC-4781/2
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
TX1+
TX1GND
AGND
AVDD
RX0+
RX0AVDD
AGND
AGND
AVDD
RX1+
RX1AVDD
AGND
AGND
AVDD
AGND
OSC
AVDD
AGND
AGND
AVDD
RX2+
RX2AVDD
AGND
AGND
AVDD
MB
MA
AVDD
AGND
GND
TX2+
TX2-
PIN CONFIGURATION:
77V1253
144-PQFP
PU-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
GND
DNC
DNC
VDD
DA
SE
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
VDD
ALE
CS
RD
WR
RST
GND
INT
VDD
GND
DNC
RXLED2
RXLED1
RXLED0
VDD
GND
RXDATA0
RXDATA1
RXDATA2
RXDATA3
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TXADDR3
VDD
TXADDR2
TXADDR1
TXADDR0
TXCLAV
TXCLK
GND
VDD
RXCLK
RXEN
RXADDR0
RXADDR1
GND
RXADDR2
RXADDR3
RXADDR4
RXCLAV
RXSOC
GND
VDD
RXPARITY
RXDATA15
RXDATA14
RXDATA13
RXDATA12
RXDATA11
RXDATA10
RXDATA9
RXDATA8
GND
VDD
RXDATA7
RXDATA6
RXDATA5
RXDATA4
VDD
GND
TX0TX0+
VDD
MM
MODE1
MODE0
RXREF
TXREF
GND
DNC
TXLED2
TXLED1
TXLED0
VDD
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXEN
TXSOC
TXADDR4
4781 drw 02
Figure 1. Pin Assignments
2
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS
LINE SIDE SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RX0+,-
139, 138
In
Port 0 positive and negative receive differential input pair.
RX1+,-
133, 132
In
Port 1 positive and negative receive differential input pair.
RX2+,-
121, 120
In
Port 2 positive and negative receive differential input pair.
TX0+,-
4, 3
Out
Port 0 positive and negative transmit differential output pair.
TX1+,-
144, 143
Out
Port 1 positive and negative transmit differential output pair.
TX2+,-
110, 109
Out
Port 2 positive and negative transmit differential output pair.
UTILITY BUS SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
AD[7:0]
101, 100, 99, 98,
96, 95, 94, 93
In/Out
Utility bus address/data bus. The address input is sampled on the falling
e dge of ALE. Data is output on this bus when a read is performed. Input
data is sampled at the completion of a write operation.
ALE
91
In
Utility bus address latch enable. Asynchronous input. An address on the
AD bus is sampled on the falling edge of ALE. ALE may be either high
low when the AD bus is being used for data.
CS
90
In
Utility bus asynchronous chip select. CS must be asserted to read or
write an internal register. It may remain asserted at all times if desired.
RD
89
In
Utility bus read enable. Active low asynchronous input. After latching
an address, a read is performed by deasserting WR and asserting
RD and CS.
WR
88
In
Utility bus write enable. Active low asynchronous input. After latching
an address, a write is performed by deasserting RD, placing data
on the AD bus, and asserting WR and CS. Data is sampled.
MISCELLANEOUS SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
DA
103
In
DNC
12, 82, 105, 106
Out
Do Not Connect. Do not connect these pins to anything external to the
chip. They must remain open.
INT
85
Out
Interrupt. INT is an op en-drain output, driven low to indicate an interrupt.
Once low, INT remains low until the interrupt status in the appropriate
interrupt Status Register is read. Interrupt sources are programmable
via the interrupt Mask Registers.
MA
114
In
Reserved signal. This input must be connected to logic low.
MB
115
In
Reserved signal. This input must be connected to logic low.
MM
6
In
Reserved signal. This input must be connected to logic high.
MODE[1:0]
7, 8
In
Mod e Selects. They determine the configuration of the PHY/ATM
interface. 00 = UTOPIA Level 2. 01 = UTOPIA Le vel 1. 10 = DPI.
11 is reserved.
OSC
126
In
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz
for 25.6 Mb ps; 64 MHz for 51.2 Mbps.
RST
87
In
Reset. Active low asynchronous input resets all control logic, counters
and FIFOs. A reset must be performed after power up prior to normal
operation of the part.
RXLED[2:0]
81, 80, 79
Out
Reserved signal. This input must be connected to logic low.
Receive LED drivers. Driven low for 2 23 RCLK or DPICLK cycles,
beginning with RXSOC when that port receives a good (non-null and
non-errored) cell. Drives 8 mA both high and low. One per port.
4781 tbl 01
3
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
PIN NUMBER
I/O
RXREF
9
Out
SE
102
In
TXLED[2:0]
13, 14, 15
Out
TXREF
10
In
SIGNAL DESCRIPTION
Receive Refere nce. Active low, synchronous to OSC. RXREF pulses
low for a programmable number of clock cycles when an x_8 command
byte is received. Re gister 0x40 is programmed to indicate which port
is referenced.
Reserved signal. This input must be connected to logic low.
Ports 2 thru 0 Transmit LED driver. Goes low for 223 TCLK or DPICLK
cycles, beginning with TXSOC when this port receives a cell for
transmission. 8 mA drive current both high and low. One per port.
Transmit Reference. Synchronous to OSC. On the falling edge of TXREF,
an X_8 command byte is inserted into the transmit data stream. Logic
for this signal is programmed in register 0x40. Typical application is
WAN timing.
POWER SUPPLY SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
AGND
112, 117, 118, 123,
124, 127, 129, 130,
135, 136, 141
____
Analog ground. AGND supply a ground reference to the analog
portion of the ship, which sources a more constant current than the
digital portion.
AVDD
113, 116, 119, 122,
125, 128, 131, 134,
137, 140
____
Analog power supply 3.3 + 0.3V AVDD supply power to the analog
portion of the chip, which draws a more constant current than the
digital portion.
2, 11, 44, 50, 56,
67, 77, 83, 86, 97,
107, 111, 142
____
Digital Ground.
1, 5, 16, 38, 45,
57, 68, 78, 84, 92,
104, 108
____
Digital power supply. 3.3 + 0.3V.
GND
VDD
SIGNAL DESCRIPTION
16-BIT UTOPIA 2 SIGNALS (MODE[1:0] = 00)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RXADDR[4:0]
53, 52, 51, 49, 48
In
Utopia 2 Receive Address Bus. This bus is used in polling and selecting
the receive port. The port addresses are defined in bits [4:0] of the
Enhanced Control Registers.
RXCLAV
54
Out
Utopia 2 Receive Cell Available. Indicates the cell available status of the
addressed port. It is asserted when a full cell is available for retrieval
from the receive FIFO. When non of the three ports is addressed.
RXCLAV is high impedance.
RXCLK
46
In
RXDATA[15:0]
59, 60, 61, 62, 63, 64,
65, 66, 69, 70, 71, 72,
73, 74, 75, 76
Out
RXEN
47
In
RXPARITY
58
Out
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
RXSOC
55
Out
Utopia 2 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA.
TXADDR[4:0]
36, 37, 39, 40, 41
In
Utopia 2 Transmit Address Bus. This bus is used in polling and selecting
the transmit port. The port addresses are defined in bits [4:0] of the
Enhanced Control Registers.
TXCLAV
42
Out
Utopia 2 Receive Clock. This is a free running clock input.
Utopia 2 Receive Data. When one of the three ports is selected, the
77V1253 transfers received cells to an ATM device across this bus.
Also see RXPARITY.
Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability
to receive data across the RXDATA bus.
Utopia 2 Transmit Cell Available. Indicates the availability of room in the
transmit FIFO of the addressed port for a full cell. When none of the
three ports is addressed, TXCLAV is high impedance.
4781tbl 02
4
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
TXCLK
43
In
Utopia Transmit Clock. This is a free running clock input.
TXDATA[15:0]
32, 31, 30, 29, 28,
27, 26, 25, 24, 23, 22,
21, 20, 19, 18, 17
In
Utopia 2 Transmit Data. An ATM d evice transfers cells across this bus to
the 77V1253 for transmission. Also see TXPARITY.
TXEN
34
TXPARITY
33
In
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other actio n is taken in the
event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
SIGNAL NAME
PIN NUMBER
I/O
RXCLAV[2:0]
65, 66, 54
Out
RXCLK
46
In
RXDATA[7:0]
69, 70, 71, 72,
73, 74, 75, 76
Out
RXEN[2:0]
49, 48, 47
In
RXPARITY
58
Out
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
RXSOC
55
Out
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA. Tri-statable as determined by bit 5 in the
Diagnostic Control Registers.
TXCLAV[2:0]
40, 41, 42
Out
Utopia 1 Transmit cell Available. Indicates the availability of room in the
transmit FIFO of the re spective p ort for a full cell.
TXCLK
43
In
Utopia 1 Transmit Clock. This is a free running clock input.
TXDATA[7:0]
24, 23, 22, 21,
20, 19, 18, 17
In
Utopia 1 Transmit Data. An ATM d evice transfers cells across the bus to
the 77V1253 for transmission. Also see TXPARITY.
TXEN[2:0]
26, 25, 34
In
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus. One for each port.
TXPARITY
33
In
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other actio n is taken in the
event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus.
In
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01)
SIGNAL DESCRIPTION
Utopia 1 Receive Cell Available. Indicates the cell available status of the
respective port. It is asserted when a full cell is available for retrieval
from the receive FIFO.
Utopia 1 Receive Clock. This is a free running clock input.
Utopia 1 Receive Data. When one of the three ports is selected, the
77V1253 transfers received cells to an ATM d evice across this bus. Bit 5
in the Diagnostic Control Registers determines whether RXDATA tri-states
when RXEN[2:0] are high. Also see RXPARITY.
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability
to receive data across the RXDATA bus. One for each port.
DPI MODE SIGNALS (MODE[1:0] = 10)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
DPICLK
43
In
DPI Source Clock for Transmit. This is the free-running clock used as the
source to geenrate Pn_TCLK.
Pn_RCLK
51, 49, 48
In
DPI Port 'n' Receive Clock. Pn_RCLK is cycled to indicate that the
interfacing device is ready to receive a nibb le of data on Pn_RD[3:0] of
port 'n'.
Pn_RD[3:0]
63, 64, 65, 66,
69, 70, 71, 72,
73, 74, 75, 76
Out
DPI Port 'n' Receive Data. Cells received on port 'n' are passed to the
interfacing device across this bus. Each port has its own dedicated bus.
4781 tbl 03
5
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
Pn_PFRM
58, 54, 55
Out
DPI Port 'n' Receive Frame. Pn_RFRM is asserted for one cycle
immediately p receding the transfer of each cell on Pn_RD[3:0].
Pn_TCLK
39, 40, 41
Out
DPI Port 'n' Transmit Clock. Pn_TCLK is derrived from DPICLK and is
cycled when the respective port is ready to accept another 4 bits of data
on Pn_TD[3:0].
Pn_TD[3:0]
28, 27, 26, 25,
24, 23, 22, 21,
20, 19, 18, 17
In
DPI Port 'n' Transmit Data. Cells are passed across this bus to the PHY
for transmission on port 'n'. Each port has its own dedicated bus.
Pn_TFRM
36, 33, 34, 35
In
DPI Port 'n' Transmit Frame. Start of cell signal which is asserted for one
cycle immediately preceding the first 4 bits of each cell on Pn_TD[3:0].
4781 tbl 04
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE:
SIGNAL NAME
PIN NUMBER
VDD
1
GND
2
TX0-
3
TX0+
4
VDD
5
MM
6
MODE1
7
MODE0
8
RXREF
9
TXREF
10
GND
11
DNC
12
TXLED2
13
TXLED1
14
TXLED0
15
VDD
16
16-BIT UTOPIA 2
MODE[1,0] = 00
8-BIT UTOPIA 1
MODE[1,0] = 01
DPI
MODE[1,0] = 10
TXDATA0
17
TXDATA0
TXDATA0
P0_TD[0]
TXDATA1
18
TXDATA1
TXDATA1
P0_TD[1]
TXDATA2
19
TXDATA2
TXDATA2
P0_TD[2]
TXDATA3
20
TXDATA3
TXDATA3
P0_TD[3]
TXDATA4
21
TXDATA4
TXDATA4
P1_TD[0]
TXDATA5
22
TXDATA5
TXDATA5
P1_TD[1]
TXDATA6
23
TXDATA6
TXDATA6
P1_TD[2]
TXDATA7
24
TXDATA7
TXDATA7
P1_TD[3]
TXDATA8
25
TXDATA8
TXEN[1]
P2_TD[0]
TXDATA9
26
TXDATA9
TXEN[2]
P2_TD[1]
TXDATA10
27
TXDATA10
see note 2
P2_TD[2]
TXDATA11
28
TXDATA11
see note 2
P2_TD[3]
TXDATA12
29
TXDATA12
see note 2
see note 2
4781 tbl 05
6
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE (CONTINUED):
SIGNAL NAME
PIN NUMBER
16-BIT UTOPIA 2
8-BIT UTOPIA 1
DPI
TXDATA13
30
TXDATA13
see note 2
see note 2
TXDATA14
31
TXDATA14
see note 2
see note 2
TXDATA15
32
TXDATA15
see note 2
see note 2
TXPARITY
33
TXPARITY
TXPARITY
P2_TFRM
P1_TFRM
TXEN
34
TXEN
TXEN[0]
TXSOC
35
TXSOC
TXSOC
P0_TFRM
TXADDR4
36
TXADDR4
see note 2
see note 2
TXADDR3
37
TXADDR3
see note 2
see note 2
VDD
38
TXADDR2
39
TXADDR2
see note 1
P2_TCLK
TXADDR1
40
TXADDR1
TXCLAV[2]
P1_TCLK
TXADDR0
41
TXADDR0
TXCLAV[1]
P0_TCLK
TXCLAV
42
TXCLAV
TXCLAV[0]
see note 1
TXCLK
43
TXCLK
TXCLK
DPICLK
GND
44
VDD
45
RXCLK
46
RXCLK
RXCLK
see note 2
RXEN
47
RXEN
RXEN[0]
see note 2
RXADDR0
48
RXADDR0
RXEN[1]
P0_RCLK
RXADDR1
49
RXADDR1
RXEN[2]
P1_RCLK
GND
50
RXADDR2
51
RXADDR2
see note 2
P2_RCLK
RXADDR3
52
RXADDR3
see note 2
see note 2
RXADDR4
53
RXADDR4
see note 2
see note 2
RXCLAV
54
RXCLAV
RXCLAV[0]
P1_RFRM
RXSOC
55
RXSOC
RXSOC
P0_FRM
GND
56
VDD
57
RXPARITY
58
RXPARITY
RXPARITY
P2_RFRM
RXDATA15
59
RXDATA15
see note 1
see note 1
RXDATA14
60
RXDATA14
see note 1
see note 1
RXDATA13
61
RXDATA13
see note 1
see note 1
RXDATA12
62
RXDATA12
see note 1
see note 1
RXDATA11
63
RXDATA11
see note 1
P2_RD[3]
RXDATA10
64
RXDATA10
RXCLAV[3]
P2_RD[2]
RXDATA9
65
RXDATA9
RXCLAV[2]
P2_RD[1]
RXDATA8
66
RXDATA8
RXCLAV[1]
P2_RD[0]
GND
67
VDD
68
RXDATA7
69
RXDATA7
RXDATA7
P1_RD[3]
RXDATA6
70
RXDATA6
RXDATA6
P1_RD[2]
RXDATA5
71
RXDATA5
RXDATA5
P1_RD[1]
RXDATA4
72
RXDATA4
RXDATA4
P1_RD[0]
RXDATA3
73
RXDATA3
RXDATA3
P0_RD[3]
RXDATA2
74
RXDATA2
RXDATA2
P0_RD[2]
RXDATA1
75
RXDATA1
RXDATA1
P0_RD[1]
4781 tbl 06
7
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE (CONTINUED):
SIGNAL NAME
PIN NUMBER
16-BIT UTOPIA 2
8-BIT UTOPIA 1
DPI
RXDATA0
76
RXDATA0
RXDATA0
P0_RD[0]
GND
77
VDD
78
RXLED0
79
RXLED1
80
RXLED2
81
DNC
82
GND
83
VDD
84
INT
85
GND
86
RST
87
WR
88
RD
89
CS
90
ALE
91
VDD
92
AD0
93
AD0
94
AD0
95
AD0
96
GND
97
AD0
98
AD0
99
AD0
100
AD0
101
SE
102
DA
103
VDD
104
DNC
105
DNC
106
GND
107
VDD
108
TX2-
109
TX2+
110
GND
111
AGND
112
AVDD
113
MA
114
MB
115
AVDD
116
AGND
117
AGND
118
AVDD
119
RX2-
120
RX2+
121
4781 tbl 07
8
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE (CONTINUED):
SIGNAL NAME
PIN NUMBER
AVDD
122
AGND
123
AGND
124
AVDD
125
OSC
126
AGND
127
AVDD
128
AGND
129
AGND
130
AVDD
131
RX1-
132
RX1+
133
AVDD
134
AGND
135
AGND
136
AVDD
137
RX0-
138
RX0+
139
AVDD
140
AGND
141
GND
142
TX1-
143
TX1+
144
16-BIT UTOPIA 2
8-BIT UTOPIA 1
DPI
4781 tbl 08
NOTES:
1. This output signal is unused in this mode. It must be left unconnected.
2. This input signal is unused in this mode. It must be connected to either logic high or logic low.
9
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
77V1253 OVERVIEW:
The 77V1253 is based on the 77105, and maintains significant register
compatibility with it. The 77V1253, however, has additional register features,
and also duplicates most of its registers to provide significant independence
between the three ports.
Access to these status and control registers is through the utility bus. This
is an 8-bit muxed address and data bus, controlled by a conventional
asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8 kHz timing marker, and
provide LED indication of receive and transmit status.
The 77V1253 is a three-port implementation of the physical layer standard
for 25.6Mbps ATM network communications as defined by ATM Forum
document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided
into a Physical Media Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer. The PMD sub layer includes the functions for the
transmitter, receiver and clock recovery for operation across 100 meters of
category 3 unshielded twisted pair (UTP) cable. This is referred to as the Line
Side Interface. The TC sub layer defines the line coding, scrambling, data
framing and synchronization.
On the other side, the 77V1253 interfaces to an ATM layer device (such
as a switch core or SAR). This cell level interface is configurable as either 8bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as three 4-bit DPI
interfaces, as determined by two MODE pins. This is referred to as the PHYATM Interface. The pinout and front page block diagram are based on the
Utopia 2 configuration. Table 2 shows the corresponding pin functions for the
other two modes, and Figures 2 and 3 show functional block diagrams.
OPERATION AT 51.2 Mbps
In addition to operation at the standard rate of 25.6 Mbps, the 77V1253 is
also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other
aspects of operation are identical to the 25.6 Mbps mode. The data rate is
determined by the frequency of the clock applied to the OSC input. OSC is 32
MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All
ports operate at the same frequency.
See page 30 for recommended line magnetics. Magnetics for 51.2 Mbps
operation have a higher bandwidth than magnetics optimized for 25.6 Mbps.
TxREF
TxCLK
TxDATA[7:0]
TxParity
TxSOC
TxEN[2:0]
TxCLAV[2:0]
Mode[1:0]
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Tx/Rx ATM
Cell FIFO
P/S and S/P
NRZI
Driver
+
Tx Port 0
-
Clock/Data
Recovery
+
Rx Port 0
-
Driver
+
Tx Port 1
-
Clock/Data
Recovery
+
Rx Port 1
-
Driver
+
- Tx Port 2
Clock/Data
Recovery
+
- Rx Port 2
UTOPIA
Multi-PHY
Interface
RxCLK
RxDATA[7:0]
RxParity
RxSOC
RxEN[2:0]
RxCLAV[2:0]
INT
RST
RD
WR
CS
AD[7:0]
ALE
Microprocessor
(Utility Bus)
Interface
3
OSC
RxREF
3
RxLED[2:0] TxLED[2:0]
Figure 2. Block Diagram for Utopia Level 1 configuration (MODE[1:0] = 01)
10
4781 drw 03
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
DPICLK
IDT77V1253
TxREF
Mode[1:0]
P0_TCLK
P0_TFRM
P0_TD[3:0]
P0_RCLK
P0_RFRM
P0_RD[3:0]
P1_TCLK
P1_TFRM
P1_TD[3:0]
P1_RCLK
P1_RFRM
P1_RD[3:0]
DPI
Multi-PHY
Interface
P2_TCLK
P2_TFRM
P2_TD[3:0]
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
P/S and S/P
NRZI
Scrambler/
Descrambler
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
P2_RCLK
P2_RFRM
P2_RD[3:0]
3
INT
RST
RD
WR
CS
AD[7:0]
ALE
P/S and S/P
NRZI
Driver
+
Tx Port 0
-
Clock/Data
Recovery
+
Rx Port 0
-
Driver
+
Tx Port 1
-
Clock/Data
Recovery
+
Rx Port 1
-
Driver
+
- Tx Port 2
Clock/Data
Recovery
+
- Rx Port 2
3
Microprocessor
(Utility Bus)
Interface
OSC
RxREF
RxLED[2:0] TxLED[2:0]
Figure 3. Block Diagram for DPI configuration (MODE[1:0] = 10)
11
4781 drw 04
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
FUNCTIONAL DESCRIPTION
2. X_4 ('escape' followed by '4'): Start-of-cell without scrambler/
descrambler reset.
3. X_8 ('escape' followed by '8'): 8kHz timing marker. This command byte
is generated when the 8kHz sync pulse is detected, and has priority over
all line activity (data or command bytes). It is transmitted immediately
when the sync pulse is detected. When this occurs during a cell
transmission, the data transfer is temporarily interrupted on an octet
boundary, and the X_8 command byte is inserted. This condition is the
only allowed interrupt in an otherwise contiguous transfer.
Below is an illustration of the cell structure and command byte usage:
TRANSMISSION CONVERGENCE (TC) SUB LAYER
Introduction
The TC sub layer defines the line coding, scrambling, data framing and
synchronization. Under control of a switch interface or Segmentation and
Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell,
scrambles the data, appends a command byte to the beginning of the cell, and
encodes the entire 53 bytes before transmission. These data transformations
ensure that the signal is evenly distributed across the frequency spectrum. In
addition, the serialized bit stream is NRZI coded. An 8 kHz timing sync pulse may
be used for isochronous communications.
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ...
In the above example, the first ATM cell is preceded by the X_X start-of-cell
command byte which resets both the transmitter-scrambler and receiverdescrambler pseudo-random nibble generators (PRNG) to their initial states.
The following cell illustrates the insertion of a start-of-cell command without
scrambler/descrambler reset. During this cell's transmission, an 8kHz timing
sync pulse triggers insertion of the X_8 8kHz timing marker command byte.
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte is
distinguished by an escape symbol followed by one of 17 encoded symbols.
Together, this byte forms one of seventeen possible command bytes. Three
command bytes are defined:
1. X_X (read: 'escape' symbol followed by another 'escape'): Start-of-cell
with scrambler/descrambler reset.
FUNCTIONAL BLOCK DIAGRAM (CONTINUED):
Start of Cell
TxRef (8kHz)
3 Cells
UTOPIA
or
DPI Interface
PHY-ATM
Interface
Control,
HEC Gen. &
Insertion
4
Scrambler
4
4
Scramble
Nibble
Command
Byte
Insertion
Reset
4
Next
PRNG
4b/5b
Encoding
1
OSC
Clock Input
NRZI
Encoding
Tx +
Tx 4781 drw 05
Figure 4. TC Transmit Block Diagram
12
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Transmission Description
Refer to Figure 4 on the previous page. Cell transmission begins with the
PHY-ATM Interface. An ATM layer device transfers a cell into the 77V1253
across the Utopia or DPI transmit bus. This cell enters a 3-cell deep transmit
FIFO. Once a complete cell is in the FIFO, transmission begins by passing the
cell, four bits (MSB first) at a time to the 'Scrambler'.
The 'Scrambler' takes each nibble of data and exclusive-ORs them against
the 4 high order bits (X(t), X(t-1), X(t-2), X(t-3)) of a 10 bit pseudo-random nibble
generator (PRNG). Its function is to provide the appropriate frequency
distribution for the signal across the line.
The PRNG is clocked every time a nibble is processed, regardless of
whether the processed nibble is part of a data or command byte. Note however
that only data nibbles are scrambled. The entire command byte (X _C) is NOT
scrambled before it's encoded (see diagram for illustration). The PRNG is based
upon the following polynomial:
Data
0000
0100
1000
1100
Symbol
10101
00111
10010
10111
Data
0001
0101
1001
1101
Symbol
01001
01101
11001
11101
Data
0010
0110
1010
1110
Symbol
01010
01110
11010
11110
Data
0011
0111
1011
1111
Symbol
01011
01111
11011
11111
ESC(X) = 00010
X10 + X7 + 1
4781 drw 05a
This encode/decode implementation has several very desirable properties. Among them is the fact that the output data bits can be represented by a
set of relatively simple symbols;
• Run length is limited to <= 5;
• Disparity never exceeds +/- 1.
On the receiver, the decoder determines from the received symbols
whether a timing marker command (X_8) or a start-of-cell command was sent
(X_X or X_4). If a start-of-cell command is detected, the next 53 bytes received
are decoded and forwarded to the descrambler. (See TC Receive Block
Diagram, Figure 4).
The output of the 4b/5b encoder provides serial data to the NRZI encoder.
The NRZI code transitions the wire voltage each time a '1' bit is sent. This,
together with the previous encoding schemes guarantees that long run lengths
of either '0' or '1's are prevented. Each symbol is shifted out with its most significant
bit sent first.
When no cells are available to transmit, the 77V1253 keeps the line active
by continuing to transmit valid symbols. But it does not transmit another startof-cell command until it has another cell for transmission. The 77V1253 never
generates idle cells.
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
generated from the following equations:
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1).
A scrambler lock between the transmitter and receiver occurs each time an
X_X command is sent. An X_X command is initiated only at the beginning of a
cell transfer after the PRNG has cycled through all of its states (210 - 1 = 1023
states). The first valid ATM data cell transmitted after power on will also be
accompanied with an X_X command byte. Each time an X_X command byte is
sent, the first nibble after the last escape (X) nibble is XOR'd with 1111b (PRNG
= 3FFx).
Because a timing marker command (X_8) may occur at any time, the
possibility of a reset PRNG start-of-cell command and a timing marker command
occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection
of the last two consecutive escape (X) nibbles will cause the PRNG to reset to
its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble
of the second consecutive escape pair.
Once the data nibbles have been scrambled using the PRNG, the nibbles
are further encoded using a 4b/5b process. The 4b/5b scheme ensures that
an appropriate number of signal transitions occur on the line. A total of seventeen
5-bit symbols are used to represent the sixteen 4-bit data nibbles and the one
escape (X) nibble. The table below lists the 4-bit data with their corresponding
5-bit symbols:
Transmit HEC Byte Calculation/Insertion
Byte #5 of each ATM cell, the HEC (Header Error Control) is calculated
automatically across the first 4 bytes of the cell header, depending upon the
setting of bit 5 of registers 0x03, 0x13 and 0x23. This byte is then either inserted
as a replacement of the fifth byte transferred to the PHY by the external system,
or the cell is transmitted as received. A third operating mode provides for
insertion of "Bad" HEC codes which may aid in communication diagnostics.
These modes are controlled by the LED Driver and HEC Status/Control
Registers.
13
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Receiver Description
The receiver side of the TC sublayer operates like the transmitter, but
in reverse. The data is NRZI decoded before each symbol is reassembled.
The symbols are then sent to the 5b/4b decoder, followed by the Command
Byte Interpreter, De-Scrambler, and finally through a FIFO to the UTOPIA
or DPI interface to an ATM Layer device.
Note that although the IDT77V1253 can detect symbol and HEC errors,
it does not attempt to correct them.
Upon reset or the re-connect, each port's receiver is typically not symbolsynchronized. When not symbol-synchronized, the receiver will indicate a
significant number of bad symbols, and will deassert the Good Signal Bit as
described below. Synchronization is established immediately once that port
receives an Escape symbol, usually as part of the start-of-cell command byte
preceding the first received cell.
The IDT77V1253 monitors line conditions and can provide an interrupt if the
line is deemed 'bad'. The Interrupt Status Registers (registers 0x01, 0x11 and
0x21) contain a Good Signal Bit (bit 6, set to 0 = Bad signal initially) which shows
the status of the line per the following algorithm:
ATM CELL FORMAT
Bit 7
Bit 0
To declare 'Good Signal' (from "Bad" to "Good"):
There is an up-down counter that counts from 7 to 0 and is initially set to
7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles =
204.8 symbols) and no "bad symbol" has been received, the counter
decreases by one. However, if at least one "bad symbol" is detected
during these 1,024 clocks, the counter is increased by one, to a
maximum of 7. The Good Signal Bit is set to 1 when this counter reaches
0. The Good Signal Bit could be set to 1 as quickly as 1,433 symbols
(204.8 x 7) if no bad symbols have been received.
Header Byte 1
Header Byte 2
Header Byte 3
Header Byte 4
UDF
Payload Byte 1
•
•
•
Payload Byte 48
4781 drw 52
UDF = User Defined Field (or HEC)
FUNCTIONAL BLOCK DIAGRAM (CONTINUED):
PRNG
RxRef
Scramble
Nibble
Reset
4
Next
Rx +
NRZI
Decoding
5
5b/4b
Decoding
4
Rx
Command
Byte
Detection,
Removal,
& Decode
4
DeScrambler
Start of Cell
4
3 Cells
32.0MHz
Clock
Synthesizer
& PLL
PHY-ATM
Interface
Control RECV
OSC
UTOPIA
or
DPI Interface
4781 drw 06
Figure 5. TC Receive Block Diagram
14
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
8kHz Timing Marker
The 8kHz timing marker, described earlier, is a completely optional feature
which is essential for some applications requiring synchronization for voice or
video, and unnecessary for other applications. Figure 6 shows the options
available for generating and receiving the 8kHz timing marker.
The source of the marker is programmable in the RXREF and TXREF
Control Register (0x40). Each port is individually programmable to either a local
source or a looped remote source. The local source is TXREF, which is an
8kHz clock of virtually any duty cycle. When unused, TXREF should be tied
high. Also note that it is not limited to 8kHz, should a different frequency be
desired. When looped, a received X_8 command byte causes one to be
generated on the transmit side.
A received X_8 command byte causes the 77V1253 to issue a negative
pulse on RXREF. The source channel of the marker is programmable.
To declare 'Bad Signal' (from "Good" to "Bad"):
The same up-down counter counts from 0 to 7 (being at 0 to provide a
"Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the counter increases by one. If it detects all "good symbols" and no
"bad symbols" in the next time period, the counter decreases by one.
The "Bad Signal" is declared when the counter reaches 7. The Good
Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at
least one "bad symbol" is detected in each of seven consecutive groups
of 204.8 symbols.
TxREF
Input
LTSel#0 ( Reg 40, Bit 0)
RxRef#0
(X_8 received)
Mux
TxRef#0
(X_8 generator)
LTSel#1 ( Reg 40, Bit 1)
RxRef#1
(X_8 received)
Mux
TxRef#1
(X_8 generator)
LTSel#2 ( Reg 40, Bit 2)
RxRef#2
(X_8 received)
RxRefSel[1:0]
Mux
TxRef#2
(X_8 generator)
RxRef
Select
Decoder
IDT77V1253
RxREF
Output
4781 drw 07
Figure 6. RXREF and TXREF Block Diagram
15
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
PHY-ATM Interface
The 77V1253 PHY offers three choices in interfacing to ATM layer devices
such as segmentation and reassembly (SAR) and switching chips. MODE[1:0]
are used to select the configuration of this interface, as shown in the table below.
MODE[1:0]
PHY-ATM Interface Configuration
00
one 16-bit UTOPIA Level 2 port
01
one 8-bit UTOPIA Level 1 (Multi-PHY) port
10
three 4-bit Data Path Interface (DPI) ports
4781 tbl 09
UTOPIA is a Physical Layer to ATM Layer interface standardized by the
ATM Forum. It has separate transmit and receive channels and specific
handshaking protocols. UTOPIA Level 2 has dedicated address signals for
both the transmit and receive directions that allow the ATM layer device to specify
with which of the four PHY channels it is communicating. UTOPIA Level 1 does
not have address signals. Instead, key handshaking signals are duplicated so
that each channel has its own signals. In both versions of UTOPIA, all channels
share a single transmit data bus and a single receive data bus for data transfer.
DPI is a low-pin count Physical Layer to ATM Layer interface. The lowpin count characteristic allows the 77V1253 to incorporate three separate DPI
4-bit ports, one for each of the three serial ports. As with the UTOPIA interfaces,
the transmit and receive directions have their own data paths and handshaking.
UTOPIA LEVEL 2 INTERFACE OPTION
The 16-bit Utopia Level 2 interface operates as defined in ATM Forum
document af-phy-0039. This PHY-ATM interface is selected by setting the
MODE[1:0] pins both low.
This mode is configured as a single 16-bit data bus in the transmit (ATMto-PHY) direction, and a single 16-bit data bus in the receive (PHY-to-ATM)
direction. In addition to the data bus, each direction also includes a single optional
parity bit, an address bus, and several handshaking signals. The UTOPIA
address of each channel is determined by bits 4 to 0 in the Enhanced Control
Registers. Please note that the transmit bus and the receive bus operate
completely independently. The Utopia 2 signals are summarized below:
TXDATA[15:0]
TXPARITY
TXSOC
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
RXDATA[15:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
RXCLK
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
The ATM device starts by polling the PHY ports on the Utopia 2 bus to
determine if any of them has room to accept a cell for transmission (TXCLAV),
or has a receive cell available to pass on to the ATM device (RXCLAV). To
poll, the ATM device drives an address (TXADDR or RXADDR) then observes
TXCLAV or RXCLAV on the next cycle of TXCLK or RXCLK. A port must tristate TXCLAV and RXCLAV except when it is addressed.
If TXCLAV or RXCLAV is asserted, the ATM device may select that port,
then transfer a cell to or from it. Selection of a port is performed by driving the
address of the desired port while TXEN or RXEN is high, then driving TXEN
or RXEN low. When TXEN is driven low, TXSOC (start of cell) is driven high
to indicate that the first 16 bits of the cell are being driven on TXDATA. The ATM
device may chose to temporarily suspend transfer of the cell by deasserting
TXEN. Otherwise, TXEN remains asserted as the next 16 bits are driven onto
TXDATA with each cycle of TXCLK.
In the receive direction, the ATM device selects a port if it wished to receive
the cell that the port is holding. It does this by asserting RXEN. The PHY then
transfers the data 16 bits each clock cycle, as determined by RXEN. As in the
transmit direction, the ATM device may suspend transfer by deasserting RXEN
at any time. Note that the PHY asserts RXSOC coincident with the first 16 bits
of each cell.
TXPARITY and RXPARITY are parity bits for the corresponding 16-bit data
fields. Odd parity is used.
Figures 8 through 13 may be referenced for Utopia 2 bus examples.
Because this interface transfers an even number of bytes, rather than the
ATM standard of 53 bytes, a filler byte is inserted between the 5-byte header
and the 48-byte payload. This is shown in Figure 7.
Bit 15
First
Last
Bit 0
Header byte 1
Header byte 2
Header byte 3
Header byte 4
Header byte 5
stuff byte
Payload byte 1
Payload byte 2
Payload byte 3
Payload byte 4
Payload byte 5
Payload byte 6
Payload byte 45
Payload byte 46
Payload byte 47
Payload byte 48
4781 drw 08
Figure 7. Utopia Level 2 Data Format and Sequence
16
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling:
polling
TxCLK
TxADDR[4:0]
TxCLAV
1F
N+1
N+3
High-Z
1F
N+2
1F
N+3
N+3
N+2
1F
N
N+3
1F
N
TxEN
TxData[15:0],
TxPARITY
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
H5, undefined
P1, 2
TxSOC
PHY N+3
PHY N
cell transmission to:
4781 drw 09
Figure 8. Utopia 2 Transmit Handshake - Back to Back Cells
selection
polling
polling:
polling
TxCLK
TxADDR[4:0]
TxCLAV
1F
N+1
N+3
High-Z
1F
N+2
1F
N+3
N+2
N+3
1F
N
N+3
1F
N
TxEN
TxData[15:0],
TxPARITY
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
H5, undefined
P1, 2
TxSOC
cell transmission to:
PHY N+3
PHY N
4781 drw 10
Figure 9. Utopia 2 Transmit Handshake - Delay Between Cells
17
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling:
polling
TxCLK
TxADDR[4:0]
TxCLAV
1F
N+1
N+3
High-Z
1F
N+2
1F
N+3
M
1F
N+2
N
M
1F
N
TxEN
TxData[15:0],
TxPARITY
P25, 26
P27, 28
High-Z
P29, 30
P31, 32
P33, 34
P35, 36
High-Z
TxSOC
PHY M
PHY M
cell transmission to:
4781 drw 11
Figure 10. Utopia 2 Transmit Handshake - Transmission Suspended
selection
polling
polling:
polling
RxCLK
RxADDR[4:0]
N+3
RxCLAV
1F
N+2
N+3
1F
N+3
High-Z
N+2
1F
N
1F
N+3
N+1
1F
N
RxEN
RxData[15:0],
RxPARITY
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
H5, undefined
P1, 2
High-Z
RxSOC
cell transmission to:
High-Z
PHY N+3
PHY N
4781 drw 12
Figure 11. Utopia 2 Receive Handshake - Back to Back Cells
18
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling:
polling
RxCLK
RxADDR[4:0]
N+3
1F
RxCLAV
N+2
N+3
1F
High-Z
N+1
1F
N+2
N+1
1F
N+1
N
1F
H1, 2
H3, 4
N+1
RxEN
RxData[15:0],
RxPARITY
P45, 46
P47, 48
High-Z
undefined
High-Z
RxSOC
cell transmission to:
PHY N+1
PHY N+3
4781 drw 13
Figure 12. Utopia 2 Receive Handshake - Delay Between Cells
polling:
re-selection
polling
polling
RxCLK
RxADDR[4:0]
N+3
1F
RxCLAV
N+3
N+2
High-Z
1F
M
N+2
1F
N+1
1F
M
N+2
N+1
RxEN
RxData[15:0],
RxPARITY
P25, 26
P27, 28
High-Z
P31, 32
P33, 34
P35, 36
High-Z
RxSOC
cell transmission from:
P29, 30
PHY M
PHY M
4781 drw 14
Figure 13. Utopia 2 Receive Handshake - Suspended Transfer of Data
19
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTOPIA LEVEL 1 MULTI-PHY INTERFACE OPTION
The UTOPIA Level 1 MULTI-PHY interface operates as defined in ATM
Forum document af-phy-0017 and clarified in af-phy-0039. Utopia Level 1 is
essentially the same as Utopia Level 2, but without the addressing, polling and
selection features. Instead of addressing, it utilizes separate TxCLAV, TxEN,
RxCLAV and RxEN signals for each channel of the 77V1254. There are just
one each of the TxSOC and RxSOC signals, which are shared across all three
channels.
In addition to Utopia Level 2's cell mode transfer protocol, Utopia Level 1
also offers the option of a byte mode protocol. Bit 1 of the Master Control
Registers is used to program whether the UTOPIA Level 1 bus is in cell mode
or byte mode. In byte mode, the PHY is allowed to control data transfer on a
byte-by-byte basis via the TXCLAV and RXCLAV signals. In cell mode,
TXCLAV and RXCLAV are ignored once the transfer of a cell has begun. In
every other way the two modes are identical. Cell mode is the default
configuration and is the one described later.
The Utopia 1 signals are summarized below:
Bit 7
First
Bit 0
Header byte 1
Header byte 2
Header byte 3
Header byte 4
Header byte 5
Payload byte 1
Payload byte 2
Payload byte 3
Payload byte 46
Payload byte 47
TXDATA[7:0]
TXPARITY
TXSOC
TXEN[2:0]
TXCLAV[2:0]
TXCLK
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
RXDATA[7:0]
RXPARITY
RXSOC
RXEN[2:0]
RXCLAV[2:0]
RXCLK
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
Last
Payload byte 48
4781 drw 15
Figure 14. Utopia 1 Data Format and Sequence
Transmit and receive both utilize free running clocks, which are inputs to
the 77V1253. All Utopia signals are timed to these clocks.
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
available) to indicate that it has room in its transmit FIFO to accept at least one
53-byte ATM cell. When the ATM layer device is ready to begin passing the
cell, it asserts TXEN (transmit enable) and TXSOC (start of cell), coincident with
the first byte of the cell on TXDATA. TXEN remains asserted for the duration
of the cell transfer, but the ATM device may deassert TXEN at any time once the
cell transfer has begun, but data is transferred only when TXEN is asserted.
In the receive direction, RXEN indicates when the ATM device is prepared
to receive data. As with transmit, it may be asserted or deasserted at any time.
The PHY asserts RXCLAV to indicate that it has an entire cell to transfer.
In both transmit and receive, TXSOC and RXSOC (start of cell) is asserted
for one clock, coincident with the first byte of each cell. Odd parity is utilized across
each 8-bit data field.
Figure 14 shows the data sequence for an ATM cell over Utopia Level 1,
and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
X
H1
H2
P44
P45
P46
P47
P48
X
TxSOC
4781 drw 16
Figure 15. Utopia 1 Transmit Handshake - Single Cell
20
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
P46
P47
P48
H1
H2
H3
H4
X
H5
TxSOC
4781 drw 17
Figure 16. Utopia 1 Transmit Handshake - Back-to-Back Cells, and TXEN Suspended Transmission
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
P42
P43
P44
P45
P46
X
X
X
P47
P48
H1
TxSOC
4781 drw 18
Figure 17. Utopia 1 Transmit Handshake - TXEN Suspended Transmission and Back-to-Back Cells
(Byte Mode Only)
RxCLK
RxCLAV[2:0]
RxEN[2:0]
RxDATA[7:0],
RxPARITY
RxSOC
P47
P48
High-Z
H1
H2
H3
High-Z
4781 drw 19
Figure 18. Utopia 1 Receive Handshake - Delay Between Cells
21
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
RxCLK
RxCLAV[2:0]
RxEN[2:0]
RxDATA[7:0],
RxPARITY
P47
High-Z
P48
H1
P47
P48
X
X
H1
H2
High-Z
RxSOC
4781 drw 20
Figure 19. Utopia 1 Receive Handshake - RXEN and RXCLAV Control
RxCLK
RxCLAV[2:0]
Early RxCLAV option (bit 6=1, registers 0x02, 0x12, 0x22)
RxEN[2:0]
RxDATA[7:0],
RxPARITY
RxSOC
P42
High-Z
P43
P44
P45
P46
P47
P48
X
X
High-Z
High-Z
High-Z
4781 drw 21
Figure 20. Utopia 1 Receive Handshake - RXCLAV Deassertion
RxCLK
RxCLAV[2:0]
RxEN[2:0]
RxDATA[7:0],
RxPARITY
High-Z
RxSOC
High-Z
H1
H2
X
H3
H4
H5
P1
4781 drw 22
Figure 21. Utopia 1 Receive Handshake - RXCLAV Suspended Transfer (Byte Mode Only)
22
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
The DPI protocol is exactly symmetrical in the receive direction, with the
77V1253 driving the data and start-of-cell signals while receiving Pn_RCLK
as an input.
The DPI data interface is four bits, so the 53 bytes of an ATM cell are
transferred in 106 cycles. Figure 22 shows the sequence of that data transfer.
Figures 23 through 30 show how the handshake operates.
DPI INTERFACE OPTION
The DPI interface is relatively new and worth additional description. The
biggest difference between the DPI configurations and the UTOPIA configurations
is that each channel has its own DPI interface. Each interface has a 4-bit data
path, a clock and a start-of-cell signal, for both the transmit direction and the
receive direction. Therefore, each signal is point-to-point, and none of these
signals has high-Z capability. Additionally, there is one master DPI clock input
(DPICLK) into the 77V1253 which is used as a source for the DPI transmit clock
outputs. DPI is a cell-based transfer scheme like Utopia Level 2, whereas
UTOPIA Level 1 transfers can be either byte- or cell-based.
Another unique aspect of DPI is that it is a symmetrical interface. It is as easy
to connect two PHYs back-to-back as it is to connect a PHY to a switch fabric
chip. In contrast, Utopia is asymmetrical. Note that for the 77V1253, we are
using the "transmit" and "receive" nomenclature in the naming of the DPI signals,
whereas other devices may use more generic "in" and "out" nomenclature for
their DPI signals.
Bit 3
First
The DPI signals are summarized below, where "Pn_" refers to the signals for
channel number "n":
DPICLK
Pn_TCLK
Pn_TD[3:0]
Pn_TFRM
input to PHY
PHY to ATM
ATM to PHY
ATM to PHY
Pn_RCLK
Pn_RD[3:0]
Pn_RFRM
ATM to PHY
PHY to ATM
PHY to ATM
In the transmit direction (ATM to PHY), the ATM layer device asserts startof-cell signal (Pn_TFRM) for one clock cycle, one clock prior to driving the first
nibble of the cell on Pn_TD[3:0]. Once the ATM side has begun sending a cell,
it is prepared to send the entire cell without interruption. The 77V1253 drives
the transmit DPI clocks (Pn_TCLK) back to the ATM device, and can modulate
(gap) it to control the flow of data. Specifically, if it cannot accept another nibble,
the 77V1253 disables Pn_TCLK and does not generate another rising edge
until it has room for the nibble. Pn_TCLK are derived from the DPICLK free
running clock source.
Last
Bit 0
Header byte 1, (8:5)
Header byte 1, (4:1)
Header byte 2, (8:5)
Header byte 2, (4:1)
Header byte 3, (8:5)
Header byte 3, (4:1)
Header byte 4, (8:5)
Header byte 4, (4:1)
Header byte 5, (8:5)
Header byte 5, (4:1)
Payload byte 1, (8:5)
Payload byte 1, (4:1)
Payload byte 47, (8:5)
Payload byte 47, (4:1)
Payload byte 48, (8:5)
Payload byte 48, (4:1)
4781 drw 23
Figure 22. DPI Data Format and Sequence
23
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
X
Cell 1
Nibble 104
Cell 1
Nibble 0
X
Cell 1
Nibble 105
X
X
4781 drw 24
Figure 23. DPI Receive Handshake - One Cell Received
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
X
X
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
4781 drw 25
Figure 24. DPI Receive Handshake - Back-to-Back Cells
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 1
Cell 2
Nibble 0
Cell 2
Nibble 2
Cell 2
Nibble 3
Cell 2
Nibble 4
4781 drw 26
Figure 25. DPI Receive Handshake - ATM Layer Device Suspends Transfer
24
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
ATM Layer Device Not Ready
77V1253 Not Ready
P_RCLK (in)
P_RFRM (out)
P_RD(3:0) (out)
Cell 1
Nibble 104
Cell 1
Nibble 105
X
X
X
X
Cell 2
Nibble 1
Cell 2
Nibble 0
Cell 2
Nibble 2
4781 drw 27
Figure 26. DPI Receive Handshake - Neither Device Ready
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
X
X
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Nibble 104
Cell 1
Nibble 105
X
X
4781 drw 28
Figure 27. DPI Transmit Handshake - One Cell for Transmission
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
X
X
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
4781 drw 29
Figure 28. DPI Transmit Handshake - Back-to-Back Cells for Transmission
25
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 1
Cell 2
Nibble 0
Cell 2
Nibble 2
Cell 2
Nibble 3
Cell 2
Nibble 4
4781 drw 30
Figure 29. DPI Transmit Handshake - 77V1254 Transmit FIFO Full
77V1253 Not Ready
ATM Layer Device Not Ready
P_TCLK (out)
P_TFRM (in)
P_TD(3:0) (in)
Cell 1
Nibble 104
Cell 1
Nibble 105
X
X
X
X
Cell 2
Nibble 0
Cell 2
Nibble 1
Cell 2
Nibble 2
4781 drw 31
Figure 30. DPI Transmit Handshake - Neither Device Ready
26
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
CONTROL AND STATUS INTERFACE
different interrupt sources. Additional interrupt signal control is provided by bit
5 of the Master Control Registers. When this bit is set (=1), receive cell errors
will be flagged via interrupt signalling and all other interrupt conditions are
masked. These errors include:
UTILITY BUS
The Utility Bus is a byte-wide interface that provides access to the registers
within the IDT77V1253. These registers are used to select desired operating
characteristics and functions, and to communicate status to external systems.
The Utility Bus is implemented using a multiplexed address and data bus
(AD[7:0]) where the register address is latched via the Address Latch Enable
(ALE) signal.
- Bad receive HEC
- Short (fewer than 53 bytes) cells
- Received cell symbol error
Normal interrupt operations are performed by setting bit 0 and clearing bit
5 in the Master Control Registers. INT (pin 85) will go to a low state when an
interrupt condition is detected. The external system should then interrogate the
77V1253 to determine which one (or more) conditions caused this flag, and reset
the interrupt for further occurrences. This is accomplished by reading the
Interrupt Status Registers. Decoding the bits in these bytes will tell which error
condition caused the interrupt. Reading these registers also:
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms in Figures 42 - 43. A register read
is performed as follows:
1. Initial condition:
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
2. Set up register address:
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
3. Read register data:
- Remove register address data from AD[7:0]
- assert CS by setting to logic 0;
- assert RD by setting to logic 0
- wait minimum pulse width time (see AC specifications)
- clears the (sticky) interrupt status bits in the registers that are read
- resets INT
This leaves the interrupt system ready to signal an alarm for further problems.
LED CONTROL AND SIGNALLING
The LED outputs provide bi-directional LED drive capability of 8 mA. As an
example, the RxLED outputs are described in the truth table:
STATE
PIN VOLTAGE
Cells being received
Low
Cells not being received
High
4781 tbl 10
Write Operation
A register write is performed as described below:
1. Initial condition:
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
2. Set up register address:
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
3. Write data:
- place data on AD[7:0]
- assert CS by setting to logic 0;
- assert WR (logic 0) for minimum time
(according to timing specification); reset WR
complete register write cycle.
As illustrated in the following drawing (Figure 31), this could be connected
to provide for a two-LED condition indicator. These could also be different colors
to provide simple status indication at a glance. (The minimum value for R should
be 330Ω, but a value closer to 1 kΩ is recommended).
TxLED Truth Table
STATE
PIN VOLTAGE
Cells being transmitted
Low
Cells not being transmitted
High
4781 tbl 11
3.3V
to logic 1 to
R
(Indicates: Cells
being received
or transmitted)
INTERRUPT OPERATIONS
The IDT77V1253 provides a variety of selectable interrupt and signalling
conditions which are useful both during ‘normal’ operation, and as diagnostic
aids. Refer to the Status and Control Register List section.
Overall interrupt control is provided via bit 0 of the Master Control Registers.
When this bit is cleared (set to 0), interrupt signalling is prevented on the
respective port. The Interrupt Mask Registers allow individual masking of
RxLED(2:0)
TxLED(2:0)
R
(Indicates: Cells are
not being received or
transmitted)
4781 drw 32
Figure 31.
27
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
DIAGNOSTIC FUNCTIONS
1. LOOPBACK
There are two loopback modes supported by the 77V1253. The loopback
mode is controlled via bits 1 and 0 of the Diagnostic Control Registers:
Bit 1
Bit 0
MODE
0
0
Normal operating mode
1
0
PHY Loopback
1
1
Line Loopback
4781 tbl 12
PHY Loopback
As Figure 33 illustrates below, this loopback mode provides a connection
within the PHY from the transmit PHY-ATM interface to the PHY-ATM receive
interface. Note that while this mode is operating, no data is forwarded to or
received from the line interface.
Line Loopback
Figure 34 might also be called “remote loopback” since it provides for a
means to test the overall system, including the line. Since this mode will probably
be entered under direction from another system (at a remote location), receive
data is also decoded and transferred to the upstream system to allow it to listen
for commands. A common example would be a command asking the upstream
system to direct the TC to leave this loopback state, and resume normal
operations.
Normal Mode
This mode, Figure 32, supports normal operating conditions: data to be
transmitted is transferred to the TC, where it is queued and formatted for
transmission by the PMD. Receive data from the PMD is decoded along with
its clock for transfer to the receiving "upstream system".
ATM Layer
Device
Utopia/DPI
Interface
TC sublayer
PMD sublayer
Line
Interface
4781 drw 33
Figure 32. Normal Mode
ATM Layer Utopia/DPI
Device
Interface
PMD sublayer
TC sublayer
Line
Interface
4781 drw 34
Figure 33. PHY Loopback
28
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
ATM Layer Utopia/DPI
Device
Interface
IDT77V1253
PMD
sublayer
TC sublayer
Line
Interface
4781 drw 35
Figure 34. Line Loopback
VPI/VCI Swapping
2. COUNTERS
Several condition counters are provided to assist external systems (e.g.
software drivers) in evaluating communications conditions. It is anticipated that
these counters will be polled from time to time (user selectable) to evaluate
performance. A separate set of registers exists for each channel of the PHY.
For compatibility with IDT's Switch Star products (77V400 and 77V500), the
77V1253 has the ability to swap parts of the VPI/VCI address space in the header
of receive cells. This function is controlled by the VPI/VCI Swap bits, which are
bit 5 of the Enhanced Control Registers (0x08, 0x18 and 0x28). The portions
of the VPI/VCI that are swapped are shown below. Bits X(7:0) are swapped
with Y(7:0) when the VPI/VCI Swap bit is set and the chip is in DPI mode.
• Symbol Error Counters
- 8 bits
- counts all invalid 5-bit symbols received
• Transmit Cell Counters
- 16 bits
- counts all transmitted cells
• Receive Cell Counters
- 16 bits
- counts all received cells, excluding idle cells and HEC errored
cells
• Receive HEC Error Counters
- 5 bits
- counts all HEC errors received
7
0
VPI
VCI
GFC/VPI
VPI
VCI
VCI
PTI
HEC
The TxCell and RxCell counters are sized (16 bits) to provide a full cell count
(without roll over) if the counter is read once/second. The Symbol Error counter
and HEC Error counter were given sufficient size to indicate exact counts for
low error-rate conditions. If these counters overflow, a gross condition is
occurring, where additional counter resolution does not provide additional
diagnostic benefit.
7
Reading Counters
1. Decide which counter value is desired. Write to the Counter Select
Register(s) (0x06, 0x16 and 0x26) to the bit location corresponding to the
desired counter. This loads the High and Low Byte Counter Registers with
the selected counter’s value, and resets this counter to zero.
Byte 0
Byte 1
Byte 2
CLP Byte 3
Byte 4
0
X7
X6
X5
X4
Y3
Y2
Y1
Y0
X3
Y7
X2
Y6
X1
Y5
X0
Y4
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
4781 drw 51
NOTE: Only one counter may be enabled at any time in each of the Counter Select
Registers.
2. Read the Counter Registers (0x04, 0x14 or 0x24 (low byte)) and (0x05,
0x15 or 0x25 (high byte)) to get the value.
Further reads may be accomplished in the same manner by writing to the
Counter Select Registers.
29
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
LINE SIDE (SERIAL) INTERFACE
Also, the receive circuitry biases the positive and negative RX inputs to
slightly different voltages. This is done so that the receiver does not receive false
signals in the absence of a real signal. This can be important because the
77V1253 does not disable error detection or interrupts when an input signal is
not present.
When connecting to UTP at 51.2 Mbps, it is necessary to use magnetics with
sufficient bandwidth. Such a device can also operate satisfactorily at 25.6 Mbps.
Each of the four ports has two pins for differential serial transmission,
and two pins for differential serial receiving.
PHY TO MAGNETICS INTERFACE
A standard connection to 100ý and 120ý unshielded twisted pair
cabling is shown in Figure 35. Note that the transmit signal is somewhat
attenuated in order to meet the launch amplitude specified by the standards.
The receive circuitry is designed to attenuate low frequencies in order to
compensate for the high frequency attenuation of the cable.
IDT77V1253
AGND
R1
1
7
RJ45 Connector
2
3
4
5
TxD+
1
R3
8
TxD-
2
3
R2
Magnetics
4
AVDD
R5
C1
5
RxD+
R8
16
6
7
10
8
9
R7
R4
R9
15
L1
RxD-
14
13
12
C2
R6
AGND
AGND
4781 drw 36
Figure 35. Recommended Connection to Magnetics
TABLE 3 — ANALOG COMPONENT
VALUES
Component
Value
Tolerance
R1
47Ω
+5%
R2
47Ω
+5%
R3
620Ω
+5%
R4
110Ω
+5%
R5
2700Ω
+5%
R6
2700Ω
+5%
R7
82Ω
+5%
R8
33Ω
+5%
R9
33Ω
+5%
C1
470pF
+20%
C2
470pF
+20%
L1
3.3µH
+20%
Magnetics Modules for 25.6 Mbps
Pulse PE-67583 or R4005
TDK TLA-6M103
Valor SF1153
(619) 674-8100
(847) 803-6100
(800) 318-2567
Magnetics Modules for 51.2 Mbps
Pulse R4005
4781 tbl 13
30
(619) 674-8100
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
STATUS AND CONTROL REGISTER LIST
The 77V1253 has 28 registers that are accessible through the utility bus. Each of the three ports has 9 registers dedicated to that port. There is only one register (0x40) which
is not port specific.
For those register bits which control operation of the Utopia interface, the operation of the Utopia interface is determined by the registers corresponding to the port which is
selected at that particular time. For consistent operation, the Utopia control bits should be programmed the same for all three ports, except for the Utopia 2 port addresses in the
Enhanced Control Registers.
Register Address
Register Name
Port 0
Port 1
Port 2
Master Control Registers
0x00
0x10
0x20
Interrupt Status Registers
0x01
0x11
0x21
Diagnostic Control Registers
0x02
0x12
0x22
LED Driver and HEC Status/control
0x03
0x13
0x23
Low Byte Counter Register [7:0]
0x04
0x14
0x24
High Byte Counter Register [15:8]
0x05
0x15
0x25
Counter Registers Read Select
0x06
0x16
0x26
Interrupt Mask Registers
0x07
0x17
0x27
Enhanced Control Registers
0x08
0x18
0x28
RxREF and TxREF Control Register
All Ports
0x40
4781 tbl 14
Nomenclature
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
MASTER CONTROL REGISTERS
Addresses: 0x00, 0x10, 0x20
Bit
Type
Initial State
Function
7
R
0
6
R/W
1 = discard
errored cells
5
R/W
0 = all interrupts
4
R/W
0 = disabled
Transmit Data Parity Check
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
3
R/W
1 = discard
idle cells
Discard Received Idle Cells
Directs TC to discard received idle (GFC & VPI/VCI = 0) cells from PMD without signalling external systems.
2
R/W
0 = not halted
Halt Tx
Halts transmission of data from TC to PMD and forces both TxD signals low.
1
R/W
0 = cell mode
UTOPIA Level 1 mode select:
0 = ce ll mode, 1 = byte mode. Not applicable for Utopia 2 for DPI modes.
0
R/W
1 = enable
interrupts
Reserved
Discard Receive Error Cells
On re ceipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error
(if enabled)), this cell will be discarded and will not enter the receive FIFO.
Enable Cell Error Interrupts Only
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error"
(as defined in bit 6) to trigger interrupt line.
Enable Interrupt Pin (Interrupt Mask Bit)
Enables interrupt output pin (pin 85). If cleared, pin is always high and interrupt is masked. If set, an
interrupt will be signaled by setting the interrupt pin to "0".
4781 tbl 15
31
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
INTERRUPT STATUS REGISTERS
Addresses: 0x01, 0x11, 0x21
Bit
Type
Initial State
Function
7
R
0
6
R
0 = Bad Signal
5
sticky
0
HEC error cell received
4
sticky
0
"Short Cell" Received
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving
Start-of-Cell command bytes with fewer than 53 bytes between them.
3
sticky
0
Transmit Parity Error
If Bit 4 of Register 0x00 / 0x10 / 0x20 is set (Transmit Data Parity Check), this interrupt flags a transmit data
parity error condition. Odd parity is used.
2
sticky
0
Receive Signal Condition change
This interrupt is set when the received 'signal'
changes either from 'bad to good' or from 'good to bad'.
1
sticky
0
Received Symbol Error
Set when an undefined 5-bit symbol is received.
0
sticky
0
Receive FIFO Overflow
accept additional data.
Interrupt which indicates when the receive FIFO has filled and cannot
Reserved
Good Signal Bit
1 - Good Signal
0 - Bad Signal
See definitions on pages 14 and 15
Set when a HEC erro r is detected on received cell.
4781 tbl 16
DIAGNOSTIC CONTROL REGISTERS
Addresses: 0x02, 0x12, 0x22
Bit
Type
Initial State
Function
7
R/W
0 = normal
Force TxCLAV deassert (applicable only in Utop ia 1 and 2 modes)
Used during line loopback mode to prevent upstream system from continuing to send data to the
77V1253. Not applicable in DPI mode.
6
R/W
0 = UTOPIA
RxCLAV Operation Select (for Utopia 1 mode)
The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete
cell available for transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY
to the upstream system. With this bit set, early deassertion of this signal will o ccur coincident with the end of
Payload byte 44 (as in octet mode for TxCLAV). This provides early indication to the upstream system of this
impending condition.
0 = "Standard UTOPIA RxCLAV'
1 = "Cell mode = Byte mode"
5
R/W
1 = tri-state
Single/Multi-PHY configuration select (applicable and writable only in Utopia 1 mode)
0 = single:
Never tri-state RxDATA, RxPARITY and RxSOC
1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1
4
R/W
0 = normal
RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the re ceive FIFO. The TC signals this completion
by clearing this bit.
3
R/W
0 = normal
Insert Transmit Payload Error
Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and
recovery systems at destination station, or, under loopback control, at the local receiving station. This
payload error is accomplished by flipping bit 0 of the last cell payload byte.
2
R/W
0 = normal
Insert Transmit HEC Error
Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery
systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is
accomplished by flipping bit 0 of the HEC byte.
1,0
R/W
00 = normal
Loopback Control
bit # 1
0
0
0 Normal mode (receive from network)
1
0 PHY Loopback
1
1 Line Loopback
4781 tbl 17
32
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
LED DRIVER AND HEC STATUS/CONTROL REGISTERS
Addresses: 0x03, 0x13, 0x23
Bit
Type
Initial State
7
0
Function
Reserved
6
R/W
0 = enable
checking
Disable Receive HEC Checking (HEC Enable)
When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte.
When set (= 1), the HEC byte is not checked.
5
R/W
0 = enable
calculate &
replace
Disable Xmit HEC Calculate & Replace
When set, the 5th heade r byte of cells queued for transmit is not replaced with the HEC calculated across
the first four bytes of that cell.
4,3
R/W
00 = 1 cycle
2
R
1 = empty
1
R
0
R
RxREF Pulse Width Select
3 .
bit # 4
0
0 RxREF active for 1 OSC cycle
0
1 RxREF active for 2 OSC cycles
1
0 RxREF active for 4 OSC cycles
1
1 RxREF active for 8 OSC cycles
FIFO Status
1 = TxFIFO empty
0 = TxFIFO not empty
1
TxLED Status
0 = Cell Transmitted
1 = Cell not Transmitted
1
RxLED Status
0 = Cell Received
1 = Cell not Received
4781 tbl 18
LOW BYTE COUNTER REGISTERS [7:0]
Addresses: 0x04, 0x14, 0x24
Bit
Type
Initial State
[7:0]
R
0x00
Function
Provides low-byte of counter value selected via registers 0x06, 0x16 and 0x26.
4781 tbl 19
HIGH BYTE COUNTER REGISTERS [15:8]
Addresses: 0x05, 0x15, 0x25
Bit
Type
Initial State
[7:0]
R
0x00
Function
Provides high-byte of counter value selected via registers 0x06, 0x16 and 0x26.
4781 tbl 20
COUNTER SELECT REGISTERS
Addresses: 0x06, 0x16, 0x26
Bit
Type
Initial State
Function
7
____
0
Reserved.
6
____
0
Reserved.
5
____
0
Reserved.
4
____
0
Reserved.
3
W
0
Symbol Error Counter.
2
W
0
TxCell Counter.
1
W
0
RxCell Counter.
0
W
0
Receive HEC Error Counter.
4781 tbl 21
NOTE: Only one bit may set at any time for proper operation
33
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
INTERRUPT MASK REGISTERS
Addresses: 0x07, 0x17, 0x27
Bit
Type
Initial State
Function
7
0
Reserved.
6
0
Reserved.
5
R/W
0 = interrupt enabled HEC Error Cell.
4
R/W
0 = interrupt enabled Short Cell Error.
3
R/W
0 = interrupt enabled Transmit Parity Error.
2
R/W
0 = interrupt enabled Receive Signal Condition Change.
1
R/W
0 = interrupt enabled Received Cell Symbol Error.
0
R/W
0 = interrupt enabled Receive FIFO Overflow.
4781 tbl 22
NOTE: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are unmasked. These
interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
ENHANCED CONTROL REGISTERS
Addresses: 0x08, 0x18, 0x28
Bit
Type
Initial State
7
W
0 = not reset
6
R/W
0 = OSC
5
R/W
0 = no swap
4-0
R/W
Function
Individual Port Software Reset
1 = Reset. This bit is self clearing; It is not necessary to write "0" to exit reset.
Transmit Line Clock (or Loop Timing Mode)
When set to 0, the OSC input is used as the transmit line clock. When set to 1, the recovered
receive clock is used as the transmit line clock.
VPI/VCI Swap
DPI mode only. Receive direction only. See description on page 29.
Port 0 (Reg 0x08): 00000 Utopia 2 Port Address
Port 1 (Reg 0x18): 00001 When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address. These
Port 2 (Reg 0x28): 00010 bits are not affected by an Individual Port Software Reset.
4781 tbl 23
RXREF AND TXREF CONTROL REGISTER
Addresses: 0x40
Bit
Type
Initial State
7,6
R/W
00 = RxREF0 (Port 0)
5
W
0 = not reset
4-3
R/W
00
2-0
R/W
0000 = not looped
Function
RxREF Source Select
Selects which of the three ports (0 to 2) is the source of RxREF.
Master Software Reset
1 - Reset. This bit is self clearing; it is not necessary write "0" to exit reset.
Reserved.
RxREF to TxREF Loop Select
When set to 0, TxREF is used to generate X_8 timing marker commands.
When set to 1, TxREF input is ignored, and received X_8 timing commands
are looped back and added to the transmit stream of that same port. See Figure 6.
bit 2: port 2
bit 1: port 1
bit 0: port 0
4781 tbl 24
34
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Value
RECOMMENDED DC OPERATIONS
CONDITIONS
Unit
Symbol
VTERM
Terminal Voltage
with Respect to GND
-0.5 to +5.5
V
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-55 to +120
IOUT
DC Output Current
C
50
C
4781 tbl 25
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Grade
Commercial
Industrial
GND, AGND
3.3
3.6
V
3.0
GND
Digital Ground Voltage
0
0
0
V
2.0
____
5.25
V
Input Low Voltage
-0.3
____
0.8
V
AVDD
Analog Supply Voltage
3.0
3.3
3.6
V
AGND
Analog Ground Voltage
0
0
0
V
VDIF
VDD - AVDD
-0.5
0
0.5
V
Input High Voltage
Symbol
VDD, AVDD
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
O
Unit
CAPACITANCE (TA = +25°C, f = 1MHz)
0 C to +70 C
O
Max.
4781 tbl 26
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY
VOLTAGE
Ambient
Temperature
Typ.
Digital Supply Voltage
VIL
mA
Min.
VDD
VIH
o
Parameter
Parameter
CIN(1)
Input Capacitance
CIO(1)
I/O Capacitance
Conditions
Max.
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
4781 tbl 28
NOTES:
1. Characterized values, not currently tested.
4781 tbl 27
DC ELECTRICAL CHARACTERISTICS (ALL PINS EXCEPT TX+/- AND RX+/-)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
Gnd ≤ VIN ≤ VDD
-5
5
µA
ILO
I/O (as input) Leakage Current
Gnd ≤ VIN ≤ VDD
-10
10
µA
VOH1(1)
Output Logic "1" Voltage
IOH = -2mA, VDD = min.
2.4
___
V
VOH2(2)
Output Logic "1" Voltage
IOH = -8mA, VDD = min.
2.4
___
V
IOL = 8mA, VDD = min.
___
0.4
V
140
mA
140
mA
(3)
VOL
(4,5)
Output Logic "0" Voltage
IDD1
Digital Power Supply Current - VDD
OSC = 32 MHz, all outputs unloaded
___
IDD2(5)
Analog Power Supply Current - AVDD
OSC = 32 MHz, all outputs unloaded
___
4781 tbl 29
NOTES:
1. For AD[7:0] pins only.
2. For all output pins except AD[7:0], INT and TX+/-.
3. For all output pins except TX+/-.
4. Add 15mA for each TX+/- pair that is driving a load
5. Total supply current is the sum of IDD1 and IDD2.
DC ELECTRICAL CHARACTERISTICS (TX+/- OUTPUT PINS ONLY)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
VOH
Output High Voltage
IOH = -20mA
VDD - 0.5V
____
VOL
Output Low Voltage
IOL = 20mA
____
0.5
V
4781 tbl 30
35
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTOPIA LEVEL 2 BUS TIMING PARAMETERS
Symbol
Parameter
Min.
Max.
Unit
t1
TxCLK Frequency
0.2
50
MHz
t2
TxCLK Duty Cycle (% of t1)
40
60
%
t3
TxDATA[15:0], TxPARITY Setup Time to TxCLK
7
____
ns
t4
TxDATA[15:0], TxPARITY Hold Time to TxCLK
2
____
ns
7
____
ns
ns
t5
TxADDR[4:0], Setup Time to TxCLK
t6
TxADDR[4:0}, Hold Time to TxCLK
2
____
t7
TxSOC, TxEN Setup Time to TxCLK
7
____
ns
t8
TxSOC, TxEN Hold Time to TxCLK
2
____
ns
t9
TxCLK to TxCLAV High-Z
2
10
ns
t10
TxCLK to TxCLAV Low-Z (min) and Valid (max)
2
14
ns
t12
RxCLK Frequency
0.2
50
MHz
t13
RxCLK Duty Cycle (% of t12)
40
60
%
t14
RxEN Setup Time to RxCLK
7
____
ns
t15
RxEN Hold Time to RxCLK
2
____
ns
t16
RxADDR[4:0] Setup Time to RxCLK
7
____
ns
t17
RxADDR[4:0] Hold Time to RxCLK
2
____
ns
t18
RxCLK to RxCLAV High-Z
2
10
ns
t19
RxCLK to RxCLAV Low-Z (min) and Valid (max)
2
14
ns
t20
RxCLK to RxSOC High-Z
2
10
ns
t21
RxCLK to RxSOC Low-Z (min) and Valid (max)
2
14
ns
t22
RxCLK to RxDATA, RxPARITY High-Z
2
10
ns
t23
RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
2
14
ns
4781 tbl 31
t3
t4
t1
t2
TxCLK
TxDATA[15:0],
TxPARITY
Octets 1 &
2
t5
t6
Octet 3 & 4
TxADDR[4:0]
t7
t8
t10
t9
t10
TxSOC
TxEN
TxCLAV
High-Z
High-Z
4781 drw 37
Figure 36. UTOPIA Level 2 Transmit
36
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
t12
t13
RxCLK
t14
t15
t16
t17
RxEN
RxADDR[4:0]
t18
RxCLAV
High-Z
t21
t21
RxSOC
t20
High-Z
High-Z
t23
RxDATA[15:0],
RxPARITY
t19
t19
High-Z
t23
t22
High-Z
High-Z
4781 drw 38
Figure 37. UTOPIA Level 2 Receive
UTOPIA LEVEL 1 BUS TIMING PARAMETERS
Symbol
Parameter
Min.
Max.
Unit
t31
TxCLK Frequency
0.2
50
MHz
t32
TxCLK Duty Cycle (% of t31)
40
60
%
t33
TxDATA[7:0], TxPARITY Setup Time to TxCLK
7
____
ns
2
____
ns
ns
t34
TxDATA[7:0], TxPARITY Hold Time to TxCLK
t35
TxSOC, TxEN[2:0] Setup Time to TxCLK
7
____
t36
TxSOC, TxEN[2:0] Hold Time to TxCLK
2
____
ns
t37
TxCLK to TxCLAV[2:0] Invalid (min) and Valid (max)
2
14
ns
t39
RxCLK Frequency
0.2
50
MHz
t40
RxCLK Duty Cycle (% of t39)
40
60
%
t41
RxEN[2:0] Setup Time to RxCLK
7
____
ns
t42
RxEN[2:0] Hold Time to RxCLK
2
____
ns
t43
RxCLK to RxCLAV[2:0] Invalid (min) and Valid (max)
2
14
ns
t44
RxCLK to RxSOC High-Z
2
10
ns
t45
RxCLK to RxSOC Low-Z (min) and Valid (max)
2
14
ns
t46
RxCLK to RxDATA, RxPARITY High-Z
2
10
ns
t47
RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
2
14
ns
4781 tbl 32
37
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
t33
IDT77V1253
t31
t34
t32
TxCLK
TxDATA[7:0],
TxPARITY
Octet 1
t35
Octet 2
t36
t37
TxSOC
TxEN[2:0]
TxCLAV[2:0]
4781 drw 39
Figure 38. UTOPIA Level 1 Transmit
t39
t40
RxCLK
t41
t42
RxEN[2:0]
t43
RxCLAV[2:0]
t45
RxSOC
High-Z
RxDATA[7:0],
RxPARITY
High-Z
t45
t44
High-Z
t47
t47
t46
High-Z
4781 drw 40
Figure 39. UTOPIA Level 1 Receive
38
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
DPI BUS TIMING PARAMETERS
Symbol
Parameter
Min.
Max.
Unit
t51
DPICLK Frequency
0.2
50
MHz
t52
DPICLK Duty Cycle (% of t31)
40
60
%
t53
DPICLK to Pn_TCLK Propagation Delay
2
14
ns
t54
Pn_TFRM Setup Time to Pn_TCLK
11
____
ns
t55
Pn_TFRM Hold Time to Pn_TCLK
1
____
ns
t56
Pn_TD[3:0] Setup Time to Pn_TCLK
11
____
ns
1
____
ns
ns
t57
Pn_TD[3:0] Hold Time to Pn_TCLK
t61
Pn_RCLK Period
25
____
t62
Pn_RCLK High Time
10
____
ns
t63
Pn_RCLK Low Time
10
____
ns
t64
Pn_RCLK to Pn_RFRM Invalid (min) and Valid (max)
2
12
ns
t65
Pn_RCLK to Pn_RD Invalid (min) and Valid (max)
2
12
ns
4781 tbl 33
t51
t52
DPICLK
t53
Pn_TCLK
t54
t55
Pn_TFRM
t56
t57
Pn_TD[3:0]
4781 drw 41
Figure 40. DPI Transmit
t61
t62
t63
Pn_RCLK
t64
Pn_RFRM
t65
Pn_RD[3:0]
4781 drw 42
Figure 41. DPI Receive
39
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTILITY BUS READ CYCLE
Description
Name
Min
Max
Unit
ns
Address setup to ALE
Tapw
10
____
ns
ALE min pulse width
ns
Chip select to read enable
Tas
10
____
ns
Address set up to ALE
5
____
ns
Address hold time to ALE
0
____
ns
CS Assert to WR
ns
Min. WR pulse width
Name
Min
Max
Unit
Tas
10
____
Tcsrd
0
____
5
____
Tapw
10
____
Ttria
____
Trdpw
Tah
UTILITY BUS WRITE CYCLE
ns
Tah
Address hold to ALE
Tacswr
Description
ns
ALE min pulse width
0
ns
Address tri-state to RD assert
Twrpw
20
____
20
____
ns
Min. RD pulse width
Tdws
20
____
ns
Write Data set up
Tdh
0
____
ns
Data Valid hold time
Tdwh
10
____
ns
Write Data hold time
Tch
0
____
ns
RD deassert to CS deassert
Tch
0
____
ns
WR deassert to CS deassert
Ttrid
____
10
ns
RD deassert to data tri-state
20
____
ns
ALE low to end of write
Trd
5
18
ns
Read Data access
Tar
5
____
ns
ALE low to start of read
0
____
ns
Start of read to Data low-Z
Trdd
Taw
4781 tbl 35
4781 tbl 34
Tas
AD[7:0]
(input)
Tah
Address
Tapw
ALE
Tch
Tcsrd
CS
Tar
Trdpw
Ttrid
RD
Tdh
Trd
Trdd
AD[7:0]
(output)
Data
4781 drw 43
Figure 42. Utility Bus Read Cycle
Tas
AD[7:0]
Tah
Tdws
Tdwh
Data (input)
Address
Tapw
ALE
Taw
Tch
CS
Tcswr
Twrpw
WR
Figure 43. Utility Bus Write Cycle
40
4781 drw 44
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
OSC, RXREF, TXREF AND RESET TIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
Tcyc
OSC cycle period (25.6 Mbps)
(51.2 Mbps)
30
15
31.25
15.625
33
16.5
ns
ns
Tch
OSC high time
40
____
60
%
Tcl
OSC low time
40
____
60
%
OSC cycle to cycle period variation
____
____
1
%
1
____
30
ns
ns
Tcc
Trrpd
(1)
OSC to RXREF Propagation Delay
Ttrh
TXREF High Time
35
____
____
Ttrl
TXREF Low Time
35
____
____
ns
two OSC cycles
____
____
____
Trspw
Minimum RST Pulse Width
4781 tbl 36
NOTES:
1. The width of the RXREF pulse is programmable in the LED Driver and HEC Status/Control Registers.
2. The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, two DPICLK cycles or two OSC cycles, whichever is greater (and applicable).
Tch
Tcyc
Tcl
OSC
Trrpd
Trrpd
RxREF
Ttrl
Ttrh
TxREF
Trspw
RST
4781 drw 45
Figure 44. OSC, RXREF, TXREF and Reset Timing
1.5V
50Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
D.U.T.
GND to 3.0V
Zo = 50Ω
.
3ns
4781 drw 46
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 45
Figure 45. Output Load
4781 tbl 37
* Includes jig and scope capacitances.
41
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
A note about Figures 46 and 47: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical except
that transmit and receive are switched between the two. A Network device can be connected directly to a User device with a straight-through cable. Userto-User or Network-to-Network connections require a cable with 1-to-7 and 2-to-8 crossovers.
Note 3
Note 1
1
Rx 2
RJ45
Connector
Tx 7
8
Note 2
AGND
8 7 6 5 4 3 2 1
110 109
TX2+ TX2-
111
112
Rx
Filter
120 RX2121 RX2+
Magnetics
9 10 11 12 13 14 15 16
AGND
RJ45
Magnetics
RJ45
Magnetics
Tx
Filter
IDT
77V1253
141
142
4781 drw 47
Figure 46. PC Board Layout for ATM Network
NOTES:
1. No power or ground plane inside this area.
2. Analog power plane inside this area.
3. Digital power plane inside this area.
4. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.
5. All analog signal traces should avoid 90° corners.
Note 3
Note 1
1
Tx 2
RJ45
Connector
Rx 7
8
AGND
Note 2
8 7 6 5 4 3 2 1
111
112
110 109
TX2+ TX2-
Tx
Filter
Magnetics
9 10 11 12 13 14 15 16
AGND
RJ45
Magnetics
RJ45
Magnetics
120 RX2121 RX2+
Rx
Filter
IDT
77V1253
141
142
4781 drw 48
Figure 47. PC Board Layout for ATM User
NOTES:
1. No power or ground plane inside this area.
2. Analog power plane inside this area.
3. Digital power plane inside this area.
4. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.
5. All analog signal traces should avoid 90° corners.
42
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Package Dimensions
144
109
A2
1
A1
108
e
144-Lead
PQFP
PU-144
4.3514 '5.4035 '
E1 E
73
36
37
A
2.4792 '
72
D1
4.4319 '
D
5.5125 '
L
SYMBOL
A
A1
A2
D
D1
E
E1
L
e
b
MIN.
0.25
3.20
0.73
0.22
NOM.
3.70
0.33
3.37
31.20
28.00
31.20
28.00
0.88
0.65
-
Dimensions are in millimeters
b
MAX.
4.07
3.60
1.03
0.38
4781 drw 49
PSC-4053 is a more comprehensive package outline drawing which is available from the packaging section of the IDT
web site.
43
Ordering Information
IDT
NNNNN
Device Type
A
NNN
A
Power
Speed
Package
A
Process/
Temp. Range
I
Industrial (-40°C to +85°C)
PG
144-Pin PQFP (PU-144)
25
Speed in Mb/s
L
77V1253 Triple 25Mb/s ATM PHY
Transmission Convergence (TC)
and PMD Sublayers
4781 drw 50
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions for products soon to be, or recently released to production, including features, pinouts and block diagrams.
Timing data are based on simulation or initial characterization and are subject to change upon full characterization.
Datasheet Document History
11/30/98:
3/25/99:
12/08/2004
PRELIMINARY. Numerous minor edits. Corrections to Figures 25 and 29. Elimination of Line Rate Selection bit in the
Master Control Registers. IDD1 and IDD2 values updated. Addition of VPI/VCI Swap feature. Improvements to Utopia bus
timing parameters.
Update to new format
Removed Preliminary from datasheet and also removed Commercial Temperature range throughout Datasheet and in Ordering Information
drawing (pg 44) and updated datasheet to current template.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8694
44
for Tech Support:
408-330-1552
email:[email protected]