MTC20455 QUAD ADSL DMT TRANSCEIVER ■ ■ ■ ■ ■ ■ Quad DMT modem ATM framer Supports ANSI T1.413 issue 2, ITU G.992.1, and G.992.2 standards Low power consumption (1W for four lines) Standard Utopia level 2 ATM interface 160 PQFP Package 160 LFBGA Package PQFP160 LFBGA160 ORDERING NUMBERS: DESCRIPTION The MTC20455 is the DMT modem and ATM Framer of the MTK20450 Quad Rate adaptive ADSL DynaMiTe chipset. When used in conjunction with the MTC20454 or MTC20154 analog front-end, the product supports ANSI T1.413 release 2, ITU G.992.1 and G.992.2 (G.Lite) ADSL specifications through software configuration. It provides a cell based UTOPIA Level 2 ATM data interface. The MTC20455 performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and trellis coding for four ADSL modems. The ATM section provides framing functions for Part Numbers Package Temperature MTC20455PQ-I 160 pin PQFP -40 to +85°C MTC20455MB-I 160 pin LFBGA -40 to +85°C Can also be ordered using kit number MTK20450 the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed-Solomon error corrections, with and without interleaving. The MTC20455 is controlled and configured by the MTC20136 Transceiver Controller. All programmable coefficients and parameters are loaded by the Controller. The MTC20136 also controls the initialisation procedure and performs the monitoring and adaptive functions during operation. Figure 1. Block Diagram AFE Quad or Mux'd AFE Interface Reset JTAG DynaMiTe Core 0 DynaMiTe Core 1 Transceiver Controller Test DynaMiTe Core 2 DynaMiTe Core 3 Clocks Interface Module UTOPIA Interface February 2004 1/23 MTC20455 VSS 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VDD U_TXREFB U_TXDATA_7 U_TXDATA_6 U_TXDATA_5 U_TXDATA_4 U_TXDATA_3 U_TXDATA_2 U_TXDATA_1 U_TXDATA_0 VSS COMP_CELL VDD U_TXADDR_4 U_TXADDR_3 U_TXADDR_2 U_TXADDR_1 U_TXADDR_0 VSS U_TXCLAV U_TXENBB U_TXCLK VDDIO U_TXSOC AFTXD_3_3 AFTXD_3_2 AFTXD_3_1 AFTXD_3_0 VSSIO CTRLDATA_3 MCLK_3 CLWD_3 VDD AFRXD_3_3 AFRXD_3_2 AFRXD_3_1 AFRXD_3_0 PDOWN_3 AFRESET_3 Figure 2. PQF160 package pin out 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 UTOPIA TX AFE_1 AFE_0 OBC MTC20455 AFE_2 (PQFP160) UTOPIA RX TEST AFE_3 VDD TDO TDI TMS TCK TRSTB VSS TESTSE VSSIO U_RXDATA_0 U_RXDATA_1 U_RXDATA_2 U_RXDATA_3 U_RXDATA_4 U_RXDATA_5 U_RXDATA_6 U_RXDATA_7 VDDIO U_RXSOC U_RXCLK U_RXENBB U_RXCLAV VDD URXADDR_0 URXADDR_1 URXADDR _2 URXADDR_3 URXADDR_4 VSS AFRESET_0 PDOWN_0 AFRXD_0_0 AFRXD_0_1 AFRXD_0_2 AFRXD_0_3 VSSIO CLWD_0 MCLK_0 CTRLDATA_0 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS AD_00 AD_01 AD_02 AD_03 VDDIO AD_04 AD_05 AD_06 AD_07 VSSIO AD_08 AD_09 AD_10 AD_11 VDD AD_12 AD_13 AD_14 AD_15 VSS PCLK BE ALE CSB_0 VDD CSB_1 CSB_2 CSB_3 WR_RDB VSS RDYB OBC_TYPE INTB_0 INTB_1 VDD INTB_2 INTB_3 RESETB VSS Table 1. I/O types Type Function I Input I-PD Input with internal pull down resistor I-PU Input with internal pull up resistor O Output OZ Tri-state output B Bidirectional G Ground P Power 2/23 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 099 098 097 096 095 094 093 092 091 090 089 088 087 086 085 084 083 082 081 VDD AFTXD_2_3 AFTXD_2_2 AFTXD_2_1 AFTXD_2_0 VSS CTRLDATA_2 MCLK_2 CLWD_2 VDD AFRXD_2_3 AFRXD_2_2 AFRXD_2_1 AFRXD_2_0 VDDIO PDOWN_2 AFRESET_2 GP_IN VSS AFTXD_1_3 AFTXD_1_2 AFTXD_1_1 AFTXD_1_0 VSSIO CTRLDATA_1 MCLK_1 CLWD_1 VDD AFRXD_1_3 AFRXD_1_2 AFRXD_1_1 AFRXD_1_0 PDOWN_1 AFRESET_1 VDDIO AFTXD_0_3 AFTXD_0_2 AFTXD_0_1 AFTXD_0_0 VSS MTC20455 Table 2. I/O driver function Driver Function BD4STARP_TC CMOS bi-directional, 4mA, schmitt trigger on input, active slew rate control, 3.3V capable BD8STARP_TC CMOS bi-directional, 8mA, schmitt trigger on input, active slew rate control, 3.3V capable TLCHT_TC TTL input, 3.3V compatible TLCHTDQ_TC TTL input, 3.3V compatible, pull down, IDDq control TLCHTUQ_TC TTL input, 3.3V compatible, pull up, IDDq control Table 3. PQFP 160 pin list Signal Name Signal type 1 VSS G 2 AD_00 B BD8STARP_TC Address/Data Bus 3 AD_01 B BD8STARP_TC Address/Data Bus 4 AD_02 B BD8STARP_TC Address/Data Bus 5 AD_03 B BD8STARP_TC Address/Data Bus 6 VDDIO P 7 AD_04 B BD8STARP_TC Address/Data Bus 8 AD_05 B BD8STARP_TC Address/Data Bus 9 AD_06 B BD8STARP_TC Address/Data Bus 10 AD_07 B BD8STARP_TC Address/Data Bus 11 VSSIO G 12 AD_08 B BD8STARP_TC Address/Data Bus 13 AD_09 B BD8STARP_TC Address/Data Bus 14 AD_10 B BD8STARP_TC Address/Data Bus 15 AD_11 B BD8STARP_TC 16 VDD P 17 AD_12 B BD8STARP_TC Address/Data Bus 18 AD_13 B BD8STARP_TC Address/Data Bus 19 AD_14 B BD8STARP_TC Address/Data Bus 20 AD_15 B BD8STARP_TC Address/Data Bus 21 VSS G 22 PCLK I TLCHT_TC Processor Clock 23 BE I TLCHT_TC Address bit 1 Pin # Technology Description VSSIO+3.3V Address/Data Bus VSS+1.8V 24 ALE I TLCHT_TC Address Latch 25 CSB_0 I TLCHT_TC Chip select line 0 26 VDD P 27 CSB_1 I TLCHT_TC Chip select line 1 28 CSB_2 I TLCHT_TC Chip select line 2 29 CSB_3 I TLCHT_TC Chip select line 3 30 WR_RDB I TLCHT_TC Write/Not read BD4STARP_TC Ready indication VSS+1.8V 31 VSS G 32 RDYB OZ 33 OBC_TYPE I-PD TLCHTDQ_TC I960/Generic selection 34 INTB_0 O BD4STARP_TC Requests OBC interrupt service line 0 3/23 MTC20455 Table 3. PQFP 160 pin list (continued) Pin # Signal Name Signal type 35 INTB_1 O Technology BD4STARP_TC Description Requests OBC interrupt service line 1 36 VDD P 37 INTB_2 O BD4STARP_TC Requests OBC interrupt service line 2 38 INTB_3 O BD4STARP_TC Requests OBC interrupt service line 3 39 RESETB I TLCHT_TC Hard reset 40 VSS G BD4STARP_TC Boundary scan out 41 VDD P 42 TDO OZ VSS+1.8V VSS+1.8V 43 TDI I-PU TLCHTUQ_TC Boundary scan in 44 TMS I-PU TLCHTUQ_TC Tap controller signal 45 TCK I-PD TLCHTDQ_TC Boundary scan clock 46 TRSTB I-PD TLCHTDQ_TC Not reset of Tap controller 47 VSS G 48 TESTE I-PD TLCHTDQ_TC Enables scan test mode 49 VSSIO G 50 U_RXDATA_0 OZ BD8STARP_TC Utopia receive data bus 51 U_RXDATA_1 OZ BD8STARP_TC Utopia receive data bus 52 U_RXDATA_2 OZ BD8STARP_TC Utopia receive data bus 53 U_RXDATA_3 OZ BD8STARP_TC Utopia receive data bus 54 U_RXDATA_4 OZ BD8STARP_TC Utopia receive data bus 55 U_RXDATA_5 OZ BD8STARP_TC Utopia receive data bus 56 U_RXDATA_6 OZ BD8STARP_TC Utopia receive data bus 57 U_RXDATA_7 OZ BD8STARP_TC 58 VDDIO P 59 U_RXSOC OZ BD8STARP_TC Utopia receive start of cell 60 U_RXCLK I TLCHT_TC Utopia receive clock 61 U_RXENBB I TLCHT_TC 62 U_RXCLAV OZ 63 VDD P 64 U_RXADDR_0 I TLCHT_TC Utopia receive address 65 U_RXADDR_1 I TLCHT_TC Utopia receive address 66 U_RXADDR_2 I TLCHT_TC Utopia receive address 67 U_RXADDR_3 I TLCHT_TC Utopia receive address 68 U_RXADDR_4 I TLCHT_TC Utopia receive address 69 VSS G 70 AFRESET_0 O BD4STARP_TC MTC20455 Reset line 0 71 PDOWN_0 O BD4STARP_TC MTC20455 power down line 0 72 AFRXD_0_0 I TLCHT_TC Receive data nibble line 0 73 AFRXD_0_1 I TLCHT_TC Receive data nibble line 0 74 AFRXD_0_2 I TLCHT_TC Receive data nibble line 0 75 AFRXD_0_3 I TLCHT_TC Receive data nibble line 0 76 VSSIO G 77 CLWD_0 I TLCHT_TC Start of word indication line 0 4/23 Utopia receive data bus VSSIO+3.3V Utopia receive not enable Utopia receive cell available VSS+1.8V MTC20455 Table 3. PQFP 160 pin list (continued) Pin # Signal Name Signal type 78 MCLK_0 I TLCHT_TC Master clock line 0 79 CTRLDATA_0 O BD4STARP_TC Serial data transmit channel line 0 80 VDD P 81 VSS G 82 AFTXD_0_0 O BD4STARP_TC Transmit data nibble line 0 83 AFTXD_0_1 O BD4STARP_TC Transmit data nibble line 0 84 AFTXD_0_2 O BD4STARP_TC Transmit data nibble line 0 85 AFTXD_0_3 O BD4STARP_TC Transmit data nibble line 0 BD4STARP_TC MTC20455 Reset line 1 Technology Description VSS+1.8V 86 VDDIO P 87 AFRESET_1 O VSSIO+3.3V 88 PDOWN_1 O BD4STARP_TC MTC20455 power down line 1 89 AFRXD_1_0 I TLCHT_TC Receive data nibble line 1 90 AFRXD_1_1 I TLCHT_TC Receive data nibble line 1 91 AFRXD_1_2 I TLCHT_TC Receive data nibble line 1 92 AFRXD_1_3 I TLCHT_TC Receive data nibble line 1 93 VDD P 94 CLWD_1 I TLCHT_TC Start of word indication line 1 VSS+1.8V 95 MCLK_1 I TLCHT_TC Master clock line 1 96 CTRLDATA_1 O BD4STARP_TC Serial data transmit channel line 1 97 VSSIO G 98 AFTXD_1_0 O BD4STARP_TC Transmit data nibble line 1 99 AFTXD_1_1 O BD4STARP_TC Transmit data nibble line 1 100 AFTXD_1_2 O BD4STARP_TC Transmit data nibble line 1 101 AFTXD_1_3 O BD4STARP_TC Transmit data nibble line 1 102 VSS G 103 GP_IN I-PD TLCHTDQ_TC General purpose input for DspFe test 104 AFRESET_2 O BD4STARP_TC MTC20455 Reset line 2 105 PDOWN_2 O BD4STARP_TC MTC20455 power down line 2 106 VDDIO P 107 AFRXD_2_0 I TLCHT_TC Receive data nibble line 2 108 AFRXD_2_1 I TLCHT_TC Receive data nibble line 2 109 AFRXD_2_2 I TLCHT_TC Receive data nibble line 2 110 AFRXD_2_3 I TLCHT_TC Receive data nibble line 2 111 VDD P 112 CLWD_2 I TLCHT_TC Start of word indication line 2 113 MCLK_2 I TLCHT_TC Master clock line 2 114 CTRLDATA_2 O BD4STARP_TC Serial data transmit channel line 2 115 VSS G 116 AFTXD_2_0 O BD4STARP_TC Transmit data nibble line 2 117 AFTXD_2_1 O BD4STARP_TC Transmit data nibble line 2 118 AFTXD_2_2 O BD4STARP_TC Transmit data nibble line 2 119 AFTXD_2_3 O BD4STARP_TC Transmit data nibble line 2 120 VDD P VSSIO+3.3V VSS+1.8V VSS+1.8V 5/23 MTC20455 Table 3. PQFP 160 pin list (continued) Pin # Signal Name Signal type 121 VSS G 122 AFRESET_3 O BD4STARP_TC 123 PDOWN_3 O BD4STARP_TC MTC20455 power down line 3 124 AFRXD_3_0 I TLCHT_TC Receive data nibble line 3 125 AFRXD_3_1 I TLCHT_TC Receive data nibble line 3 126 AFRXD_3_2 I TLCHT_TC Receive data nibble line 3 127 AFRXD_3_3 I TLCHT_TC Receive data nibble line 3 128 VDD P 129 CLWD_3 I TLCHT_TC Start of word indication line 3 130 MCLK_3 I TLCHT_TC Master clock line 3 131 CTRLDATA_3 O BD4STARP_TC Serial data transmit channel line 3 132 VSSIO G 133 AFTXD_3_0 O BD4STARP_TC Transmit data nibble line 3 134 AFTXD_3_1 O BD4STARP_TC Transmit data nibble line 3 135 AFTXD_3_2 O BD4STARP_TC Transmit data nibble line 3 136 AFTXD_3_3 O BD4STARP_TC Transmit data nibble line 3 137 U_TXSOC I TLCHT_TC Utopia transmit start of cell 138 VDDIO P 139 U-TXCLK I 140 U_TXENBB I 141 U_TXCLAV OZ 142 VSS G 143 U_TXADDR_0 144 U_TXADDR_1 145 146 147 148 149 Technology Description MTC20455 Reset line 3 VSS+1.8V VSSIO+3.3V TLCHT_TC Utopia transmit clock TLCHT_TC Utopia transmit not enable BD8STARP_TC Utopia transmit cell available I TLCHT_TC Utopia transmit address I TLCHT_TC Utopia transmit address U_TXADDR_2 I TLCHT_TC Utopia transmit address U_TXADDR_3 I TLCHT_TC Utopia transmit address U_TXADDR_4 I TLCHT_TC Utopia transmit address VDD P COMP_CELL O COMPENSATION_VSS Resistance for compensation cell 150 VSS G 151 U_TXDATA_0 I TLCHT_TC Utopia transmit data bus 152 U_TXDATA_1 I TLCHT_TC Utopia transmit data bus 153 U_TXDATA_2 I TLCHT_TC Utopia transmit data bus 154 U_TXDATA_3 I TLCHT_TC Utopia transmit data bus 155 U_TXDATA_4 I TLCHT_TC Utopia transmit data bus 156 U_TXDATA_5 I TLCHT_TC Utopia transmit data bus 157 U_TXDATA_6 I TLCHT_TC Utopia transmit data bus 158 U-TXDATA_7 I TLCHT_TC Utopia transmit data bus 159 U_TXREFB I TLCHT_TC 160 VDD P 6/23 VSS+1.8V 8kHz from network VSS+1.8V MTC20455 Figure 3. LFBGA160 package pin out (Sachem4 top view) 1 2 AD_0 VDD_7 VSS_7 3 4 5 U_TXDATA_4 U_TXDATA_0 VDD_5 6 U_TXADDR_1 7 8 U_TXCLAV U_TXSOC U_TXREFB U_TXDATA_7 U_TXDATA_5 U_TXDATA_2 COMP_CELL U_TXADDR_2 U_TXENBB U_TXADDR_3 VSS_4 11 12 13 MCLK_3 AFRXD_3_3 AFRXD_3_0 VSS_2 CLWD_3 PDOWN_3 AFTXD_2_3 VDD_2 B VDD_3 AFRXD_3_2 AFTXD_2_2 VSS_1 C AFRXD_3_1 AFTXD_2_1 VDD_1 D VDDIO_4 AFTXD_3_0 A AD_7 AD_3 AD_5 AD_4 AD_10 AD_6 AD_11 VSS_8 open open open open open open MCLK_2 CTRLDATA_2 CLWD_2 AFRXD_2_1 E AD_12 AD_9 AD_8 VDD_9 open open open open open open AFRXD_2_0 AFRXD_2_3 AFRXD_2_2 AFRESET_2 F VSS_9 AD_13 AD_14 AD_15 open open open open open open GP_IN VDDIO_0 PDOWN_2 AFTXD_1_2 G ALE PCLK BE VDD_10 open open open open open open AFTXD_1_1 VSS_0 AFTXD_1_3 VSS_17 H CSB_2 CSB_0 CSB_1 WR_RDB open open open open open open MCLK_1 CTRLDATA_1 AFTXD_1_0 CLWD_1 J RDYB CSB_3 VSS_10 VDD_11 open open open open open open AFRXD_1_2 AFRXD_1_3 AFRXD_1_1 K INTB_0 TCK PDOWN_1 AFRESET_1 AFRXD_1_0 VDDIO_16 L AFRXD_0_0 AFTXD_0_2 AFTXD_0_3 AFTXD_0_1 M VSS_15 MCLK_0 AFTXD_0_0 VSS_16 N AFRXD_0_3 CLWD_0 VDD_15 U_RXDATA_0 U_RXDATA_4 VDDIO_13 U_TXCLK VSS_3 AFRESET_3 AD_1 U_TXDATA_1 U_TXADDR_4 U_TXADDR_0 AFTXD_3_3 14 AD_2 OBC_TYPE VSS_6 AFTXD_3_1 10 VDDIO_8 INTB_1 U_TXDATA_6 U_TXDATA_3 9 AFTXD_3_2 CTRLDATA_3 AFTXD_2_0 U_RXCLAV U_RXADDR_2AFRESET_0 INTB_3 INTB_2 TDI VSS_12 U_RXDATA_1 U_RXDATA_5 U_RXSOC U_RXADDR_1 VSS_14 AFRXD_0_2 VSS_11 RESETB TMS TESTSE U_RXDATA_2 U_RXDATA_6 U_RXCLK VDD_14 VDD_12 TDO TRSTB VSS_13 U_RXDATA_3 U_RXDATA_7 U_RXENBB U_RXADDR_0 U_RXADDR_3 PDOWN_0 U_RXADDR_4AFRXD_0_1 VDD_17 CTRLDATA_0 P Table 4. LFBGA 160 pin list Pin # Signal Name Signal type B1 VSS G Technology Description A1 AD_00 B BD8STARP_TC Address/Data Bus C3 AD_01 B BD8STARP_TC Address/Data Bus C2 AD_02 B BD8STARP_TC Address/Data Bus D2 AD_03 B BD8STARP_TC Address/Data Bus C1 VDDIO P D4 AD_04 B BD8STARP_TC Address/Data Bus D3 AD_05 B BD8STARP_TC Address/Data Bus VSSIO+3.3V E2 AD_06 B BD8STARP_TC Address/Data Bus D1 AD_07 B BD8STARP_TC Address/Data Bus E4 VSSIO G F3 AD_08 B BD8STARP_TC Address/Data Bus F2 AD_09 B BD8STARP_TC Address/Data Bus E1 AD_10 B BD8STARP_TC Address/Data Bus E3 AD_11 B BD8STARP_TC Address/Data Bus 7/23 MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # Signal Name Signal type F4 VDD P Technology Description VSS+1.8V F1 AD_12 B BD8STARP_TC Address/Data Bus G2 AD_13 B BD8STARP_TC Address/Data Bus G3 AD_14 B BD8STARP_TC Address/Data Bus G4 AD_15 B BD8STARP_TC Address/Data Bus G1 VSS G H2 PCLK I TLCHT_TC Processor Clock H3 BE I TLCHT_TC Address bit 1 H1 ALE I TLCHT_TC Address Latch J2 CSB_0 I TLCHT_TC Chip select line 0 H4 VDD P J3 CSB_1 I TLCHT_TC Chip select line 1 J1 CSB_2 I TLCHT_TC Chip select line 2 VSS+1.8V K2 CSB_3 I TLCHT_TC Chip select line 3 J4 WR_RDB I TLCHT_TC Write/Not read BD4STARP_TC Ready indication K3 VSS G K1 RDYB OZ L2 OBC_TYPE I-PD TLCHTDQ_TC I960/Generic selection L3 INTB_0 O BD4STARP_TC Requests OBC interrupt service line 0 BD4STARP_TC L1 INTB_1 O K4 VDD P Requests OBC interrupt service line 1 M2 INTB_2 O M1 INTB_3 O BD4STARP_TC Requests OBC interrupt service line 3 N2 RESETB I TLCHT_TC Hard reset N1 VSS G P1 VDD P VSS+1.8V BD4STARP_TC Requests OBC interrupt service line 2 VSS+1.8V P2 TDO OZ BD4STARP_TC Boundary scan out M3 TDI I-PU TLCHTUQ_TC Boundary scan in N3 TMS I-PU TLCHTUQ_TC Tap controller signal L4 TCK I-PD TLCHTDQ_TC Boundary scan clock P3 TRSTB I-PD TLCHTDQ_TC Not reset of Tap controller TLCHTDQ_TC Enables scan test mode M4 VSS G N4 TESTE I-PD P4 VSSIO G L5 U_RXDATA_0 OZ BD8STARP_TC Utopia receive data bus M5 U_RXDATA_1 OZ BD8STARP_TC Utopia receive data bus N5 U_RXDATA_2 OZ BD8STARP_TC Utopia receive data bus P5 U_RXDATA_3 OZ BD8STARP_TC Utopia receive data bus L6 U_RXDATA_4 OZ BD8STARP_TC Utopia receive data bus M6 U_RXDATA_5 OZ BD8STARP_TC Utopia receive data bus N6 U_RXDATA_6 OZ BD8STARP_TC Utopia receive data bus P6 U_RXDATA_7 OZ BD8STARP_TC Utopia receive data bus L7 VDDIO P 8/23 VSSIO+3.3V MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # Signal Name Signal type M7 U_RXSOC OZ N7 U_RXCLK I TLCHT_TC Utopia receive clock P7 U_RXENBB I TLCHT_TC Utopia receive not enable L8 U_RXCLAV OZ Technology BD8STARP_TC Description Utopia receive start of cell Utopia receive cell available N8 VDD P D11 AFTXD_2_0 O BD4STARP_TC VSS+1.8V Transmit data nibble line 2 D13 AFTXD_2_1 O BD4STARP_TC Transmit data nibble line 2 C13 AFTXD_2_2 O BD4STARP_TC Transmit data nibble line 2 B13 AFTXD_2_3 O BD4STARP_TC B14 VDD P Transmit data nibble line 2 VSS+1.8V A13 VSS G A14 AFRESET_3 O BD4STARP_TC MTC20455 Reset line 3 B12 PDOWN_3 O BD4STARP_TC MTC20455 power down line 3 A12 AFRXD_3_0 I TLCHT_TC Receive data nibble line 3 D12 AFRXD_3_1 I TLCHT_TC Receive data nibble line 3 C12 AFRXD_3_2 I TLCHT_TC Receive data nibble line 3 A11 AFRXD_3_3 I TLCHT_TC Receive data nibble line 3 C11 VDD P B11 CLWD_3 I TLCHT_TC Start of word indication line 3 VSS+1.8V A10 MCLK_3 I TLCHT_TC Master clock line 3 D10 CTRLDATA_3 O BD4STARP_TC Serial data transmit channel line 3 C10 VSSIO G B10 AFTXD_3_0 O BD4STARP_TC Transmit data nibble line 3 A9 AFTXD_3_1 O BD4STARP_TC Transmit data nibble line 3 D9 AFTXD_3_2 O BD4STARP_TC Transmit data nibble line 3 C9 AFTXD_3_3 O BD4STARP_TC Transmit data nibble line 3 A8 U_TXSOC I TLCHT_TC Utopia transmit start of cell B9 VDDIO P D8 U-TXCLK I TLCHT_TC Utopia transmit clock B8 U_TXENBB I A7 U_TXCLAV OZ C8 VSS G D7 U_TXADDR_0 A6 B7 VSSIO+3.3V TLCHT_TC Utopia transmit not enable BD8STARP_TC Utopia transmit cell available I TLCHT_TC Utopia transmit address U_TXADDR_1 I TLCHT_TC Utopia transmit address U_TXADDR_2 I TLCHT_TC Utopia transmit address C7 U_TXADDR_3 I TLCHT_TC Utopia transmit address D6 U_TXADDR_4 I TLCHT_TC Utopia transmit address A5 VDD P B6 COMP_CELL O C6 VSS G VSS+1.8V COMPENSATION_VSS Resistance for compensation cell A4 U_TXDATA_0 I TLCHT_TC Utopia transmit data bus D5 U_TXDATA_1 I TLCHT_TC Utopia transmit data bus B5 U_TXDATA_2 I TLCHT_TC Utopia transmit data bus 9/23 MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # Signal Name Signal type C5 U_TXDATA_3 I TLCHT_TC Utopia transmit data bus A3 U_TXDATA_4 I TLCHT_TC Utopia transmit data bus B4 U_TXDATA_5 I TLCHT_TC Utopia transmit data bus C4 U_TXDATA_6 I TLCHT_TC Utopia transmit data bus B3 U-TXDATA_7 I TLCHT_TC Utopia transmit data bus B2 U_TXREFB I TLCHT_TC 8kHz from network A2 VDD P Technology Description VSS+1.8V ELECTRICAL SPECIFICATIONS GENERIC The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels. Table 5. I/O Buffers generic DC Characteristics DC Electrical Characteristics All voltages are referenced to Vss, unless otherwise specified, positive current is towards the device Symbol Parameter IIN Input leakage current IOZ Tristate leakage current Test Conditions Min Typ Max Unit VIN = VSS, VDDIO, no pull up/pull down -1 1 µA VIN = VSS, VDDIO, -1 1 µA -100 µA no pull up/pull down IPU Pull up current VIN = VSS -15 -46.7 12.5 39.4 90 µA 35 70.5 200 kOhm 83.7 240 kOhm IPD Pull down current VIN = VDDIO Rpu Pull up resistance VIN = VSS RPD Pull down resistance VIN = VDDIO 40 IDC Static current fromVDDIO NORMAL MODE COREOFF MODE (no VDD) IDDQ MODE (VDDIO <2.5) 1.7 µA 11.6 µA - µA Table 6. IO buffers dynamic characteristic DC Electrical Characteristics, important for transient but measured at (near) DC. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions CIN Input capacitance @f = 1 MHz dl/dt Current derivative 8 mA driver, (active slew rate control) Ipeak Peak current 8 mA driver, (active slew rate control) COUT Output capacitance (also bidirectional and tristate drivers) @f = 1MHz 10/23 Min Typ 20 Max Unit 5 pF 50 mA/ns 85 mA 7 pF MTC20455 Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/ or outputs unless specified otherwise. Table 7. TTL IO buffers generic characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions VIL Low level input voltage VIH High level input voltage VHY Schmitt trigger hysteresis slow edge <1V/µs only for SCHMITT VOL Low level output voltage IOUT = XMa* VOH High level output voltage IOUT = -Xma* Min Typ Max 0.2*VDD Unit V 0.8*vDD V 0.8 V 0.4 0.85*vDD V V * The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 4 and 8mA. Input/Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise. Table 8. TTL IO buffers generic characteristics DC Electrical Characteristics, important for transient but measured at (near) DC. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter VIL Low level input voltage VIH High level input voltage Test Conditions Min Typ Max 0.8 2.0 Unit V V VILHY Low level threshold, falling slow edge < 1V/µs 0.9 1.35 V VIHHY High level threshold, rising slow edge < 1V/µs 1.3 1.9 V Schmitt trigger hysteresis slow edge <1V/µs 0.4 0.7 V VOL Low level output voltage IOUT = XMa* 0.4 V VOH High level output voltage IOUT = -Xma* VHY 2.4 V * The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 2,4, and 8mA. Operating Conditions Table 9. Operating Conditions Maximum ratings Symbol Min Typ Max Unit IO Supply voltage 3.0 3.3 3.6 V VDD Core Supply voltage 1.62 1.8 TA Ambient temperature 1m/s airflow -40 P Power dissipation VDDIO Parameter Test Conditions 2.0 V +85 °C 1000 mW 11/23 MTC20455 Functional Description Fig.4 shows the global block diagram of the MTC20455. The functions can be grouped into the following: ■ ■ ■ ■ ■ DMT modems Quad or single AFE interface Utopia interface Controller interface Miscellaneous DMT Modem Description The following section essentially describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equaliser. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End Interface transfers 1 6-bits word, multiplexed on 4 input/ output signals. As a result, 4 clock cycles are needed to transfer 1 word. The Decimator receives the 16bits samples at 8.8 MHz (as sent by the Analog Front-End chip) and reduces this rate to 2.2 MHz. The Time Equaliser (TEQ) module is an FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interference (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalisation and interpolation. The sidelobe filtering and delay equalisation are implemented by IIR filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimising the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. Figure 4. DSP Front-End Bypass Analog Interface IN select AFE I/F DEC TEQ To DMT modem DMT Modem This computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IFFT, Scaling, Rotor and Frequency Equali-sation (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent de-mapping stages. After the first stage time / domain equalisation and FFT block – an essentially ICI (InterCarrier Interference) – free carrier information stream has been obtained. This stream is still affected by carrier-specific channel distortion resulting in an attenuation of the signal 12/23 MTC20455 amplitude and a rotation of the signal phase. To compensate for these effects, the FFT is followed by a Frequency domain equaliser (FEQ) and a Rotor (phase shifter). In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper into a time domain representation. The IFFT block is preceded by a Fine Tune Gain and a Rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and communicates with the other blocks via buffers controlled by the DSTU (DMT Symbol Timing Unit)block. The DSP executes a program stored in a RAM area, a very flexible implementation open for future enhancements. Figure 5. DMT Modem Trellis coding From DSP PE FFT FEQ Rotor FEQ Coefficients Demapper Monitor FEQ Update Monitor Indications DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase errors can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This essentially consists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. 13/23 MTC20455 Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T1.413. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper is split into two paths, one dedicated to an interleaved data flow, the other one for a non-interleaved data flow. These data flows are also referred to as slow and fast data flows. The interleaving/-de-interleaving is used to increase the error correcting capabilityof block codes for error bursts. After de-interleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labelled them with an “erasure” indication. Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer. After leaving the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support physical layer-related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check) on the received frame and generates events in case of error detection. Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data stream. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module. Figure 6. Generic TC Layer Functions Indications bits AOC EOC AST F FAST From Demapper RS coding De-interleaver PMD descrambler Detramer I To ATM TC PMD descrambler ATM Specific TC Layer Functions The 2 byte streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronisa-tion, cell payload descrambling, idle/-unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. 14/23 MTC20455 Figure 7. ATM Specific TC Layer Functions BER FAST Cell Descrambler Synchronizer HEC Cell Descrambler Synchronizer HEC Cell filter To Interface Module From Generic TC Cell filter SLOW BER DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS, Monitor and Transceiver Controller. It consists of a real time and a scheduler module. The real time unit generates a time-base for the DMT symbols (sample counter), superframes (symbol counter) and hyperframes (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. Interface Module The interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). Cells are stored in FIFO’s (424 bytes or 8 cells wide, transmit buffers have the same size), from which they are extracted by the interface submodule, providing an Utopia level 2 interface. Analog Front-End Control Interface The Analog Front-End Interface is designed to be connected to the MTC20154 or MTC20454 Analog Front-End component Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 10 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal (Fig.7). The Analog Front-End fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Table 10. Bits assigned to pins/time slot for single line interface Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFRXD_i[0] b0 b4 b8 b12 AFRXD_i[1] b1 b5 b9 b13 AFRXD_i[2] b2 b6 b10 b14 AFRXD_i[3] b3 b7 b11 b15 GP_IN t0 t1 t2 t3 15/23 MTC20455 Table 11. Bits assigned to pins/time slot for muxed-line interface 0 Cycles 1 2 line 0 3 4 line 1 5 6 line 2 7 8 line 3 AFRXD_1[0] b0 b4 b0 b4 b0 b4 B0 b4 AFRXD_1[1] b1 b5 b1 b5 b1 b5 b1 AFRXD_1[2] b2 b6 b2 b6 b2 b6 b2 AFRXD_1[3] b3 b7 b3 b7 b3 b7 b3 9 10 line 0 11 12 line 1 b8 b12 b5 b9 b6 b10 b7 b11 13 14 line 2 b8 b12 b13 b9 b14 b10 b15 b11 15 line 3 b8 b12 b8 b12 b13 b9 b14 b10 b13 b9 b13 b14 b10 b15 b11 b14 b15 b11 b15 Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 11 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. (Fig.9). The CLWD must repeat after 4 MCLK cycles. Figure 8. Receive word timing diagram for single line Interface MCLK_i CLWD_i AFRXD_i Cycle0 Cycle1 Cycle2 test0 test1 test Cycle3 GP_IN test3 Figure 9. Receive word timing diagram for muxed line interface MCLK_1 CLWD_1 AFRXD_1 Cycle 0 1 line 0 2 3 line 1 4 5 line 2 6 7 line 3 8 9 line 0 10 111 12 line 1 13 line 2 14 15 line 3 Table 12. Transmitted bits assigned to signal/time slot for single-line interface Cycle 0 Cycle 1 Cycle 2 Cycle 3 AFTXD_I[0] b0 b4 b8 b12 AFTXD_I[1] b1 b5 b9 b13 AFTXD_I[2] b2 b6 b10 b14 AFTXD_I[3] b3 b7 b11 b15 POWER_DOWN_i t0 t1 t2 t3 16/23 MTC20455 Table 13. Transmitted bits assigned to signal/time slot for muxed-line interface 0 Cycles 1 2 b8 b0 line 0 3 4 b8 b0 line 1 5 6 b8 b0 line 2 7 line 3 AFTXD_1[0] b0 b8 AFTXD_1[1] b1 b9 b1 b9 b1 b9 b1 b9 AFTXD_1[2] b2 b10 b2 b10 b2 b10 b2 b10 AFTXD_1[3] b3 b11 b3 b11 b3 b11 b3 b11 AFTXD_2[0] b4 b12 b4 b12 b4 b12 b4 b12 AFTXD_2[1] b5 b13 b5 b13 b5 b13 b5 b13 AFTXD_2[2] b6 b14 b6 b14 b6 b14 b6 b14 AFTXD_2[3] b7 b15 b7 b15 b7 b15 b7 b15 Table 14. MCLK, AC Electrical Characteristics AC Electrical Characteristics for MCLK_i Symbol F Tper Th Parameter Test Conditions Min Clock Frequency Clock Period Clock duty cycle Typ Max Unit 35.328 MHz 28.3 ns 40 60 % Max Unit 16 ns Table 15. AFTXD AC Electrical Characteristics AC Electrical Characteristics for AFTXD_i Symbol Parameter Test Conditions Tva Data valid time 20 pF load Tha Data hold time 20 pF load Min Typ 4 ns Table 16. CTRLDATA AC Electrical Characteristics AC Electrical Characteristics for CTRLDATA_i Symbol Parameter Test Conditions Tvb Data valid time 20 pF load Thb Data hold time 20 pF load Min Typ Max 20 4 Unit ns ns Figure 10. Analog front end receive interface timing diagram MCLK_i Ts Th AFRXD_i CLWD_i 17/23 MTC20455 Table 17. AFRXD AC Electrical Characteristics AC Electrical Characteristics for AFRXD Symbol Parameter Test Conditions Min Typ Max Unit Ts Data setup time 5 ns Th Data setup time 1 ns Digital Interface With a Utopia Level 2 Interface the ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM direction is referred to as the receive direction. Fig.9 shows the interconnection between ATM and PHY layer devices. Tx reference and Rx reference are supported for network timing. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles. Both transmit and receive interfaces are synchronised on clocks generated by the ATM layer chip, and as no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multi-point configurations by introducing an addressing capability and by making a distinction between polling and selecting a device: – the ATM chip polls a specific physical layer chip by putting its address on the address bus when the enable (notTxEnb/notRxEnb) line is asserted. The addressed physical layer answers the next cycle via a cell available line (TxClav/RxClav) reflecting its status at that time. – the ATM chip selects a specific physical layer chip by putting its address on the address bus when the enable line is deasserted and asserting the enable line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer. Figure 11. Signals at Utopia Level 2 Interface PH Y A TM RxAddr 1 PHY Receive 5 RxClav notRxEnb RxClk 8 ATM Receive RxData RxSOC TxAddr 1 PHY Transmit TxClav notTxEnb TxClk TxData TxSOC 18/23 5 8 ATM Transmit MTC20455 Utopia Level 2 Signals The physical layer chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the FIFO of the physical layer chip. Refer to Table 6 for a list of interface signals. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting notRxEnb. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled notRxEnb active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. MTC20455 Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The MTC20455 supports only the required mode, this mode is referred to as «operation with 1 TxClav and 1 RxClav.» PHY Device Identification The MTC20455 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts. MTC20136 Transceiver Controller Interface Table 18. All signals Symbol tr, tf Parameter Min Typ Rise and Fall time (10% - 90%) Max Unit 3 ns Ci Input load 10 pF Co Output load 20 pF Max Unit 33 MHz Max Unit 4 ns Figure 12. PCLK Clock frequency Symbol f Parameter PCLK clock frequency Min Typ 8 Table 19. Address with respect to ALE Symbol tr,tf Parameter Min Rise and Fall time (10% - 90%) 12 Typ Talew ALE pulse width ns Tavs Address valid setup time 7 ns Tavh Address valid hold time 8 ns 19/23 MTC20455 Figure 13. Address and ALE timing diagram Talew ALE Tavs AD [15:0] Tavh Table 20. Data input with respect to clock Symbol Parameter Min Max Unit Tdh Data write hold time 3 ns Tds Data write setup time 10 ns Table 21. Data output with respect to clock Symbol Min Max Unit Tzd Data active delay from clock, Z to data Parameter 3 20 ns Tdz Data inactive delay from clock, data to Z 3 20 ns Min Max Unit Table 22. WR_RDB input specification with respect to PCLK Symbol Parameter Twrs setup WR_RDB to clock 10 ns Twrh hold WR_RDB to clock 3 ns Table 23. CSB input specification with respect to PCLK Symbol Parameter Min Max Unit Twrs setup CSB to clock 10 ns Twrh hold CSB to clock 3 ns Table 24. RDYB output with respect to PCLK Symbol 20/23 Parameter Min Max Unit Tzrd RDYB active delay from clock, Z to 0 3 19 ns Trdz RDYB inactive delay from clock, 0 to Z 3 19 ns MTC20455 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 4.07 A1 0.25 A2 3.17 B MAX. 0.160 0.010 3.67 0.125 0.22 0.38 0.009 0.015 C 0.13 0.23 0.005 0.009 D 30.95 31.20 31.45 1.219 1.228 1.238 D1 27.90 28.00 28.10 1.098 1.102 1.106 3.42 0.135 D3 25.35 0.998 e 0.65 0.026 0.144 E 30.95 31.20 31.45 1.219 1.228 1.238 E1 27.90 28.00 28.10 1.098 1.102 1.106 E3 L L1 K 25.35 0.65 OUTLINE AND MECHANICAL DATA 0.80 0.998 0.95 0.026 1.60 0.031 0.063 0°(min.), 7°(max.) 0.037 PQFP160 21/23 MTC20455 mm inch DIM. MIN. A 1.210 A1 0.270 A2 TYP. MAX. MIN. 1.700 0.047 TYP. MAX. 0.067 0.010 1.120 0.044 b 0.450 0.500 0.550 0.018 0.02 0.021 D 11.85 12.00 12.15 0.466 0.472 0.478 D1 E 10.40 11.85 E1 12.00 0.409 12.15 0.466 10.40 0.472 0.478 Body: 12 x 12 x 1.7mm 0.409 e 0.720 0.800 0.880 0.028 0.031 0.034 f 0.650 0.800 0.950 0.025 0.031 0.037 ddd OUTLINE AND MECHANICAL DATA 0.120 LFBGA160 Low Profile Fine Pitch Ball Grid Array 0.004 7254214 A 22/23 MTC20455 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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