MS82C55A, MQ82C55A, MP82C55A ® Data Sheet June 15, 2006 FN6140.2 CMOS Programmable Peripheral Interface Features The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The MX82C55A has identical features as the X82C55 with the exception of no bus hold devices on the port pins. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in two groups of 12 and used in three major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. • Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info) Static CMOS circuit design insures low operating power. The Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power. • Pin Compatible with OKI MSM82C55A - No Bus Hold Devices on any Port Pins • 24 Programmable I/O Pins • Fully TTL Compatible • High Speed, No “Wait State” Operation with 8MHz 80C86 and 80C88 • Direct Bit Set/Reset Capability • Enhanced Control Word Read Capability • L7 Process • 2.5mA Drive Capability on All I/O Ports • Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10µA Ordering Information PART NUMBERS* (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # CMP82C55AZ CMP82C55AZ 0 to 70 40 Ld PDIP** E40.6 CMS82C55AZ CMS82C55AZ 0 to 70 44 Ld PLCC IMS82C55AZ IMS82C55AZ N44.65 -40 to 85 CMQ82C55AZ CMQ82C55AZ 0 to 70 IMQ82C55AZ IMQ82C55AZ -40 to 85 44 Ld MQFP Q44.10x10 *Add “96” suffix to part number for tape and reel packaging. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. MS82C55A, MQ82C55A, MP82C55A Pinouts WR PA7 PA6 PA5 PA4 NC PA3 PA2 PA1 RD PA0 MQ82C55A (MQFP) TOP VIEW RD PA0 PA1 PA2 PA3 NC PA4 PA5 PA6 PA7 WR MS82C55A (PLCC) TOP VIEW 6 5 4 3 2 1 44 43 42 41 40 RESET A1 3 31 D1 A0 4 30 D2 PC7 5 29 D3 PC6 6 28 D4 PC5 7 27 D5 PC4 8 26 D6 PC0 9 25 D7 PC1 10 24 VCC PC2 11 23 12 13 14 15 16 17 18 19 20 21 22 PB7 D0 NC PB6 PB5 PB4 PB3 NC PB2 GND NC PB2 NC PB3 PB4 PB5 PB6 PB7 18 1920 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 33 2 32 1 CS PB1 RESET D0 D1 D2 D3 NC D4 D5 D6 D7 VCC PB0 39 38 37 36 35 34 33 32 31 30 29 PC3 7 8 9 10 11 12 13 14 15 16 17 PC2 PC3 PB0 PB1 CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1 CMP82C55A (PDIP) TOP VIEW 2 PA3 1 40 PA4 PA2 2 39 PA5 PA1 3 38 PA6 PA0 4 37 PA7 RD 5 36 WR CS 6 35 RESET GND 7 34 D0 A1 8 33 D1 A0 9 32 D2 PC7 10 31 D3 PC6 11 30 D4 PC5 12 29 D5 PC4 13 28 D6 PC0 14 27 D7 PC1 15 26 VCC PC2 16 25 PB7 PC3 17 24 PB6 PB0 18 23 PB5 PB1 19 22 PB4 PB2 20 21 PB3 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: The +5V power supply pin. A 0.1µF capacitor between VCC and GND is recommended for decoupling. GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode. CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. A0-A1 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 I/O PORT A: 8-bit input and output port. PB0-PB7 I/O PORT B: 8-bit input and output port. PC0-PC7 I/O PORT C: 8-bit input and output port. Functional Diagram +5V POWER SUPPLIES GND GROUP A PORT A (8) GROUP A CONTROL GROUP A PORT C UPPER (4) BIDIRECTIONAL DATA BUS DATA BUS BUFFER D7-D0 8-BIT INTERNAL DATA BUS RD READ WRITE CONTROL LOGIC WR A1 GROUP B CONTROL A0 GROUP B PORT C LOWER (4) GROUP B PORT B (8) I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 RESET CS FIGURE 1. FUNCTIONAL DIAGRAM 3 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Functional Description Data Bus Buffer This three-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A “low” on this input pin enables the communication between the 82C55A and the CPU. (RD) Read. A “low” on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A. (WR) Write. A “low” on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). 82C55A BASIC OPERATION INPUT OPERATION (READ) A1 A0 RD WR CS 0 0 0 1 0 Port A → Data Bus 0 1 0 1 0 Port B → Data Bus 1 0 0 1 0 Port C → Data Bus 1 1 0 1 0 Control Word → Data Bus OUTPUT OPERATION (WRITE) POWER SUPPLIES +5V GND BIDIRECTIONAL DATA BUS DATA BUS D7-D0 BUFFER RD WR A1 A0 RESET READ WRITE CONTROL LOGIC GROUP A CONTROL GROUP A PORT A (8) GROUP A PORT C UPPER (4) 8-BIT INTERNAL DATA BUS GROUP B CONTROL GROUP B PORT C LOWER (4) GROUP B PORT B (8) I/O PA7PA0 I/O PC7PC4 I/O PC3PC0 I/O PB7PB0 CS FIGURE 2. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 82C55A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information. 0 0 1 0 0 Data Bus → Port A 0 1 1 0 0 Data Bus → Port B Ports A, B, and C 1 0 1 0 0 Data Bus → Port C 1 1 1 0 0 Data Bus → Control The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 82C55A. DISABLE FUNCTION X X X X 1 Data Bus → Three-State X X 1 1 0 Data Bus → Three-State (RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. 4 Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Operational Description CONTROL WORD Mode Selection D7 D6 D5 D4 D3 D2 D1 D0 There are three basic modes of operation than can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the reset input goes “high”, all ports will be set to the input mode. After the reset is removed, the 82C55A can remain in the input mode with no additional initialization required. The control word register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written. ADDRESS BUS CONTROL BUS GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 GROUP A PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE DATA BUS FIGURE 4. MODE DEFINITION FORMAT RD, WR D7-D0 A0-A1 CS 82C55A MODE 0 C B 8 A I/O PB7-PB0 MODE 1 I/O PC3-PC0 4 I/O PC7-PC4 8 I/O PA7-PA0 C B 8 A I/O PB7-PB0 MODE 2 4 CONTROL CONTROL OR I/O OR I/O C B 8 8 PA7-PA0 A BIDIRECTIONAL I/O PB7-PB0 I/O CONTROL The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis. PA7-PA0 FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE The mode definitions and possible mode combinations may seem confusing at first, but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature (Figure 5) Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports. 5 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A three ports. No handshaking is required, data is simply written to or read from a specific port. CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 X X Mode 0 Basic Functional Definitions: BIT SET/RESET 1 = SET 0 = RESET X DON’T CARE • Two 8-bit ports and two 4-bit ports • Any Port can be input or output BIT SELECT 0 1 2 3 4 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 5 1 0 1 6 0 1 1 • Outputs are latched 7 1 B0 1 B1 1 B2 • Inputs are not latched • 16 different Input/Output configurations possible MODE 0 PORT DEFINITION BIT SET/RESET FLAG 0 = ACTIVE A FIGURE 5. BIT SET/RESET FORMAT B GROUP A PORT C PORT A (Upper) GROUP B D3 D1 D0 Interrupt Control Functions 0 0 0 0 Output Output 0 Output Output When the 82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input INTE Flip-Flop Definition (BIT-SET)-INTE is SET - Interrupt Enable (BIT-RESET)-INTE is Reset - Interrupt Disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the # PORT C PORT B (Lower) D4 Mode 0 (Basic Input) tRR RD tIR tHR INPUT tAR tRA CS, A1, A0 D7-D0 tRD 6 tDF FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Mode 0 (Basic Output) tWW WR tWD tDW D7-D0 tAW tWA CS, A1, A0 OUTPUT tWB Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A 4 4 8 B 0 0 0 0 0 82C55A D7 - D0 4 PA7 - PA0 PC7 - PC4 C 4 8 PB7 - PB0 B 1 4 8 B 0 0 0 0 0 1 PC3 - PC0 PB7 - PB0 1 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 CONTROL WORD #4 B PC3 - PC0 PB7 - PB0 CONTROL WORD #8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A D7 - D0 8 D7 D6 D5 D4 D3 D2 D1 D0 4 0 0 A D7 - D0 C 0 1 PC3 - PC0 1 8 0 0 CONTROL WORD #3 A 1 0 PC7 - PC4 D7 D6 D5 D4 D3 D2 D1 D0 0 0 82C55A CONTROL WORD #1 1 0 PA7 - PA0 C D7 - D0 0 4 8 B 7 0 1 0 0 0 0 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 D7 - D0 PC7 - PC4 C 4 PC3 - PC0 PB7 - PB0 PA7 - PA0 8 B PC3 - PC0 PB7 - PB0 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Mode 0 Configurations (Continued) CONTROL WORD #5 CONTROL WORD #9 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 A 82C55A 4 4 8 B 0 0 1 0 1 82C55A D7 - D0 4 8 1 0 1 0 0 1 0 0 1 PC3 - PC0 PB7 - PB0 0 8 A 4 PC7 - PC4 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 B PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 82C55A 4 4 8 B 0 0 1 0 0 1 1 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C D7 - D0 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 CONTROL WORD #12 B PC3 - PC0 PB7 - PB0 CONTROL WORD #14 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A D7 - D0 PC7 - PC4 CONTROL WORD #11 A 1 8 B 82C55A D7 D6 D5 D4 D3 D2 D1 D0 0 4 PA7 - PA0 CONTROL WORD #7 0 4 PA7 - PA0 C PB7 - PB0 1 B 1 8 D7 D6 D5 D4 D3 D2 D1 D0 4 0 1 A D7 - D0 C 0 0 PC3 - PC0 0 8 0 0 CONTROL WORD #10 A 1 0 PC7 - PC4 D7 D6 D5 D4 D3 D2 D1 D0 0 1 82C55A CONTROL WORD #6 1 0 PA7 - PA0 C D7 - D0 0 4 8 B 8 0 1 1 0 1 0 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 D7 - D0 PC7 - PC4 C 4 PC3 - PC0 PB7 - PB0 PA7 - PA0 8 B PC3 - PC0 PB7 - PB0 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Mode 0 Configurations (Continued) CONTROL WORD #13 CONTROL WORD #15 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 A 82C55A D7 - D0 4 8 B 0 1 1 0 1 1 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 D7 - D0 4 8 B Operating Modes Output Control Signal Definition Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals. (Figure 8 and 9) Mode 1 Basic Function Definitions: • Two Groups (Group A and Group B) PC7 - PC4 C PC3 - PC0 PB7 - PB0 PA7 - PA0 PC3 - PC0 PB7 - PB0 OBF - (Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF, (See Note 1). The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. • Each group contains one 8-bit port and one 4-bit control/data port • The 8-bit data port can be either input or output. Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit port. Input Control Signal Definition (Figures 6 and 7) STB (Strobe Input) A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by bit set/reset of PC4. INTE B Controlled by bit set/reset of PC2. 9 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A MODE 1 (PORT A) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 PC6, PC7 1 = INPUT 0 = OUTPUT MODE 1 (PORT B) 8 PA7-PA0 INTE A STBA PC4 1 PC5 PC3 RD PC6, PC7 2 1 8 PB7-PB0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 INTE B 1 PC2 STBB IBFA PC1 IBFB INTRA PC0 INTRB RD I/O FIGURE 6. MODE 1 INPUT tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH INPUT FROM PERIPHERAL tPS FIGURE 7. MODE 1 (STROBED INPUT) ACK - (Acknowledge Input). A “low” on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data, (See Note 1). INTR - (Interrupt Request). A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”. It is reset by the falling edge of WR. MODE 1 (PORT A) PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 PC4, PC5 1 = INPUT 0 = OUTPUT INTE A 8 PC7 OBFA PC6 ACKA INTRA PC3 WR PC4, PC5 2 INTE A Controlled by Bit Set/Reset of PC6. INTE B Controlled by Bit Set/Reset of PC2. MODE 1 (PORT B) 1 NOTE: 1. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generates an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF. PB7-PB0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 8 PC1 OBFB PC2 ACKB PC0 INTRB 0 INTE B WR FIGURE 8. MODE 1 OUTPUT 10 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A tWOB WR tAOB OBF INTR tWIT ACK tAK tAIT OUTPUT tWB FIGURE 9. MODE 1 (STROBED OUTPUT) 8 PA7-PA0 RD CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 PC4 STBA PC5 IIBFA INTRA PC3 0 PC6, PC7 1 = INPUT 0 = OUTPUT PC6, PC7 2 PB7, PB0 WR PA7-PA0 WR CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 I/O 1 PC7 OBFA PC6 ACKA INTRA PC3 1 PC4, PC5 1 = INPUT 0 = OUTPUT 8 8 PC4, PC5 PB7, PB0 2 I/O 8 PC1 OBFB PC2 STBB PC2 ACKB PC1 IBFB PC0 INTRB PC0 INTRB RD PORT A - (STROBED INPUT) PORT B - (STROBED OUTPUT) PORT A - (STROBED OUTPUT) PORT B - (STROBED INPUT) Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. FIGURE 10. COMBINATIONS OF MODE 1 Operating Modes Output Operations Mode 2 (Strobed Bidirectional Bus I/O) OBF - (Output Buffer Full). The OBF output will go “low” to indicate that the CPU has written data out to port A. This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). “Hand shaking” signals are provided to maintain proper bus flow discipline similar to Mode 1. Interrupt generation and enable/disable functions are also available. ACK - (Acknowledge). A “low” on this input enables the threestate output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 - (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4. Mode 2 Basic Functional Definitions: Input Operations • Used in Group A only STB - (Strobe Input). A “low” on this input loads data into the input latch. • One 8-bit, bidirectional bus Port (Port A) and a 5-bit control Port (Port C) • Both inputs and outputs are latched • The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A) Bidirectional Bus I/O Control Signal Definition IBF - (Input Buffer Full F/F). A “high” on this output indicates that data has been loaded into the input latch. INTE 2 - (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4. (Figures 11, 12, 13, 14) INTR - (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. 11 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 INTRA PC3 1/0 1/0 1/0 PA7-PA0 PC2-PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT 8 PC7 OBFA INTE 1 PC6 ACKA INTE 2 PC4 STBA PC5 IBFA WR GROUP B MODE 0 = MODE 0 1 = MODE 1 PC2-PC0 RD FIGURE 11. MODE CONTROL WORD 3 I/O FIGURE 12. MODE 2 DATA FROM CPU TO 82C55A WR tAOB OBF tWOB INTR tAK ACK tST STB tSIB IBF tAD tPS tKD PERIPHERAL BUS tRIB tPH RD DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD + OBF • MASK • ACK • WR) FIGURE 13. MODE 2 (BIDIRECTIONAL) 12 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC3 PA7-PA0 1 1 0 1 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT PA7-PA0 8 OBFA PC7 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 PC6 ACKA PC4 STBA PC5 IBFA PC2-PC0 PC3 INTRA 3 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 PC7 OBFA PC6 ACKA PC4 STBA IBFA PC5 PC2-PC0 3 I/O RD PB7-PB0 PB7, PB0 8 8 WR MODE 2 AND MODE 1 (OUTPUT) MODE 2 AND MODE 1 (INPUT) PC3 PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1/0 I/O WR 1 0 PC2-PC0 1 = INPUT 0 = OUTPUT RD 1 0 INTRA 0 PC7 OBFA ACKA PC4 STBA PC5 IBFA PC1 RD WR PA7-PA0 8 PC6 PB7-PB0 PC3 INTRA CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 OBFB PC2 ACKB PC0 INTRB RD WR 8 PC7 OBFA PC6 ACKA PC4 STBA PC5 IBFA PB7-PB0 8 INTRA 8 PC2 STBB PC1 IBFB PC0 INTRB FIGURE 14. MODE 2 COMBINATIONS 13 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A MODE DEFINITION SUMMARY MODE 0 MODE 1 MODE 2 IN OUT IN OUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In Out Out Out Out Out Out Out Out INTRB IBFB STBB INTRA STBA IBFA I/O I/O INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a “Set Mode” command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 17. Through a “Write Port C” command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a “Write Port C” command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in Mode 1 group or to change an interrupt enable flag, the “Set/Reset Port C Bit” command must be used. With a “Set/Reset Port C Bit” command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C are not affected by a “Set/Reset Port C Bit” command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the “Set Reset Port C Bit” command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 17. 14 GROUP A ONLY Mode 0 or Mode 1 Only I/O I/O I/O INTRA STBA IBFA ACKA OBFA INPUT CONFIGURATION D7 D6 D5 I/O I/O IBFA D4 D3 D2 INTEA INTRA INTEB GROUP A D1 D0 IBFB INTRB GROUP B OUTPUT CONFIGURATION D7 D6 OBFA INTEA D5 D4 I/O I/O D3 D2 D1 D0 INTRA INTEB OBFB INTRB GROUP A GROUP B FIGURE 15. MODE 1 STATUS WORD FORMAT D7 D6 OBFA INTE1 D5 IBFA D4 D3 INTE2 INTRA GROUP A D2 D1 D0 X X X GROUP B (Defined by Mode 0 or Mode 1 Selection) FIGURE 16. MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Reading Port C Status (Figures 15 and 16) Applications of the 82C55A In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes 1 or 2, Port C generates or accepts “hand shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow accordingly. The 82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system. It represents the optimum use of available pins and is flexible enough to interface almost any I/O device without the need for additional external logic. There is not a special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. INTERRUPT ENABLE FLAG POSITION ALTERNATE PORT C PIN SIGNAL (MODE) INTE B PC2 ACKB (Output Mode 1) or STBB (Input Mode 1) INTE A2 PC4 STBA (Input Mode 1 or Mode 2) INTE A1 PC6 ACKA (Output Mode 1 or Mode 2) Each peripheral device in a microcomputer system usually has a “service routine” associated with it. The routine manages the software interface between the device and the CPU. The functional definition of the 82C55A is programmed by the I/O service routine and becomes an extension of the system software. By examining the I/O devices interface characteristics for both data transfer and timing, and matching this information to the examples and tables in the detailed operational description, a control word can easily be developed to initialize the 82C55A to exactly “fit” the application. Figures 18 through 24 present a few examples of typical applications of the 82C55A. FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 INTERRUPT REQUEST PC3 MODE 1 (OUTPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC7 PC6 PC5 PC4 HIGH SPEED PRINTER HAMMER RELAYS DATA READY ACK PAPER FEED FORWARD/REV. 82C55A PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 PC1 PC2 PAPER FEED FORWARD/REV. RIBBON CARRIAGE SEN. DATA READY ACK PC0 INTERRUPT REQUEST CONTROL LOGIC AND DRIVERS FIGURE 18. PRINTER INTERFACE 15 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A INTERRUPT REQUEST PC3 MODE 1 (INPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL PC4 PC5 STROBE ACK INTERRUPT REQUEST PC3 MODE 1 (INPUT) 82C55A PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 B0 B1 B2 BURROUGHS SELF-SCAN B3 DISPLAY B4 B5 BACKSPACE CLEAR MODE 0 (INPUT) DATA READY ACK BLANKING CANCEL WORD PC1 PC2 PC6 PC7 82C55A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL PC4 PC5 PC6 PC7 STROBE ACK BUST LT TEST LT TERMINAL ADDRESS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 INTERRUPT REQUEST FIGURE 19. KEYBOARD AND DISPLAY INTERFACE FIGURE 20. KEYBOARD AND TERMINAL ADDRESS INTERFACE INTERRUPT REQUEST PA0 PA1 PA2 PA3 PA4 MODE 0 PA5 (OUTPUT) PA6 PA7 PC4 PC5 PC6 PC7 82C55A PC0 PC1 BIT SET/RESET PC2 PC3 PB0 PB1 PB2 MODE 0 (INPUT) PB3 PB4 PB5 PB6 PB7 LSB PC3 12-BIT D/A CONVERTER (DAC) ANALOG OUTPUT PA0 PA1 PA2 PA3 PA4 PA5 MODE 1 PA6 (OUTPUT) PA7 MSB SAMPLE EN STB LSB ANALOG INPUT MSB FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL 16 PC7 PC6 PC5 PC4 DATA READY ACK BLANKED BLACK/WHITE PC2 PC1 PC0 ROW STB COLUMN STB CURSOR H/V STB 82C55A STB DATA 8-BIT A/D CONVERTER (ADC) R0 R1 R2 CRT CONTROLLER R3 ² CHARACTER GEN. ² REFRESH BUFFER R4 ² CURSOR CONTROL R5 SHIFT CONTROL PB0 MODE 0 PB1 (OUTPUT) PB2 PB3 PB4 PB5 PB6 PB7 CURSOR/ROW/COLUMN ADDRESS H&V FIGURE 22. BASIC CRT CONTROLLER INTERFACE FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A INTERRUPT REQUEST INTERRUPT REQUEST PC3 MODE 2 PC3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D0 D1 D2 D3 D4 D5 D6 D7 PC4 PC5 PC7 PC6 DATA STB ACK (IN) DATA READY ACK (OUT) PC2 PC1 PC0 TRACK “0” SENSOR SYNC READY INDEX FLOPPY DISK CONTROLLER AND DRIVE 82C55A MODE 1 (INPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 R3 R4 R5 R6 R7 PC4 PC5 PC6 STB ACK STOP/GO PC0 PC1 PC2 START/STOP LIMIT SENSOR (H/V) OUT OF FLUID MACHINE TOOL 82C55A PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 ENGAGE HEAD FORWARD/REV. READ ENABLE WRITE ENABLE DISC SELECT ENABLE CRC TEST BUSY LT FIGURE 23. BASIC FLOPPY DISC INTERFACE 17 MODE 0 (INPUT) B LEVEL PAPER TAPE READER PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 CHANGE TOOL LEFT/RIGHT UP/DOWN HOR. STEP STROBE VERT. STEP STROBE SLEW/STEP FLUID ENABLE EMERGENCY STOP FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Absolute Maximum Ratings TA = 25°C Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC+0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (°C/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Operating Temperature Range CMX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C IMX82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications SYMBOL VCC = 5.0V± 10%; TA = Operating Temperature Range PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIH Logical One Input Voltage 2.0 2.2 - - V VIL Logical Zero Input Voltage - - 0.8 V VOH Logical One Output Voltage IOH = -2.5mA, IOH = -100µA 3.0 VCC -0.4 - - V VOL Logical Zero Output Voltage IOL +2.5mA - - 0.4 V II Input Leakage Current VIN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 - +1.0 µA IO I/O Pin Leakage Current VO = VCC or GND, D0 - D7 -10 - +10 µA IDAR Darlington Drive Current Ports A, B, C. Test Condition 3 -2.5 - Notes 2, 4 mA ICCSB Standby Power Supply Current VCC = 5.5V, VIN = VCC or GND. Output Open - - 10 µA ICCOP Operating Power Supply Current TA = +25°C, VCC = 5.0V, Typical (See Note 3) - 1 - mA/MHz NOTES: 3. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 4. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA). 5. Tested as VOH at -2.5mA. Capacitance TA = 25°C SYMBOL PARAMETER TYPICAL UNITS CIN Input Capacitance 10 pF CI/O I/O Capacitance 20 pF 18 TEST CONDITIONS FREQ = 1MHz, All Measurements are referenced to device GND FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A AC Electrical Specifications VCC = +5V± 10%, GND = 0V; TA = Operating Temperature Range SYMBOL PARAMETER TEST CONDITIONS 82C55A MIN MAX UNITS READ TIMING (1) tAR Address Stable Before RD 0 - ns (2) tRA Address Stable After RD 0 - ns (3) tRR RD Pulse Width 150 - ns (4) tRD Data Valid From RD 1 - 120 ns (5) tDF Data Float After RD 2 10 75 ns (6) tRV Time Between RDs and/or WRs 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0 - ns (8) tWA Address Stable After WR 20 - ns (9) tWW WR Pulse Width 100 - ns (10) tDW Data Valid to WR High 100 - ns (11) tWD Data Valid After WR High 30 - ns - 350 ns OTHER TIMING (12) tWB WR = 1 to Output (13) tIR Peripheral Data Before RD 0 - ns (14) tHR Peripheral Data After RD 0 - ns (15) tAK ACK Pulse Width 200 - ns (16) tST STB Pulse Width 100 - ns (17) tPS Peripheral Data Before STB High 20 - ns (18) tPH Peripheral Data After STB High 50 - ns (19) tAD ACK = 0 to Output 1 - 175 ns (20) tKD ACK = 1 to Output Float 2 20 250 ns (21) tWOB WR = 1 to OBF = 0 1 - 150 ns (22) tAOB ACK = 0 to OBF = 1 1 - 150 ns (23) tSIB STB = 0 to IBF = 1 1 - 150 ns (24) tRIB RD = 1 to IBF = 0 1 - 150 ns (25) tRIT RD = 0 to INTR = 0 1 - 200 ns (26) tSIT STB = 1 to INTR = 1 1 - 150 ns (27) tAIT ACK = 1 to INTR = 1 1 - 150 ns (28) tWIT WR = 0 to INTR = 0 1 - 200 ns (29) tRES Reset Pulse Width 1, (Note) 500 - ns 1 NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum. 19 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Timing Waveforms tRR (3) RD tIR (13) tHR (14) INPUT tAR (1) tRA (2) CS, A1, A0 D7-D0 tRD (4) tDF (5) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) WR tDW (10) tWD (11) D7-D0 tAW (7) tWA (8) CS, A1, A0 OUTPUT tWS (12) FIGURE 26. MODE 0 (BASIC OUTPUT) tST (16) STB tSIB (23) IBF tSIT (26) tRIB (24) tRIT (25) INTR RD tPH (18) INPUT FROM PERIPHERAL tPS (17) FIGURE 27. MODE 1 (STROBED INPUT) 20 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Timing Waveforms (Continued) tWOB (21) WR tAOB (22) OBF tWIT (28) INTR ACK tAK (15) tAIT (27) OUTPUT tWB (12) FIGURE 28. MODE 1 (STROBED OUTPUT) DATA FROM CPU TO 82C55A WR (NOTE) tAOB (22) OBF tWOB (21) INTR tAK (15) ACK tST (16) STB (NOTE) tSIB (23) IBF tAD (19) tPS (17) tKD (20) PERIPHERAL BUS tRIB (24) tPH (18) RD DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU FIGURE 29. MODE 2 (BIDIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD + OBF • MASK • ACK • WR) 21 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Timing Waveforms (Continued) A0-A1, CS tWA (8) tAW (7) A0-A1, CS tRA (2) tAR (1) DATA BUS tRR (3) tDW (10) tWD (11) RD (4) tRD WR tDF (5) DATA BUS VALID tWW (9) HIGH IMPEDANCE FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING AC Test Circuit AC Testing Input, Output Waveforms V1 INPUT OUTPUT VIH + 0.4V VOH 1.5V R1 OUTPUT FROM DEVICE UNDER TEST TEST POINT R2 C1 (SEE NOTE) 1.5V VIL - 0.4V VOL AC Testing: All AC Parameters tested as per test circuits. Input RISE and FALL times are driven at 1ns/V. TEST CONDITION DEFINITION TABLE NOTE: Includes STRAY and JIG Capacitance 22 TEST CONDITION V1 R1 R2 C1 1 1.7V 523Ω Open 150pF 2 VCC 2kΩ 1.7kΩ 50pF 3 1.5V 750Ω Open 50pF FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Die Characteristics GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ ±1kÅ Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR RESET CS D0 GND D1 A1 D2 A0 D3 PC7 D4 PC6 D5 PC5 D6 PC4 D7 PC0 VCC PC1 PC2 23 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 24 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N44.65 (JEDEC MS-018AC ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N 44 44 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 25 FN6140.2 June 15, 2006 MS82C55A, MQ82C55A, MP82C55A Metric Plastic Quad Flatpack Packages (MQFP) Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D D1 -D- INCHES -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M 0.008 C A-B S 0o MIN A2 A1 0o-7o L MIN MAX MIN MAX NOTES A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 N 44 44 e 0.032 BSC 0.80 BSC 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . b 4. Dimensions D1 and E1 to be determined at datum plane -H- . b1 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. BASE METAL WITH PLATING SYMBOL D S 0.13/0.17 0.005/0.007 12o-16o MILLIMETERS 0.13/0.23 0.005/0.009 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 FN6140.2 June 15, 2006