e~.National
~ Semiconcluctor
~rRIL
1118
CD
....
CIl
~
.
INS&154 N.ChanRel 12&.by.& Bit
RAM Input/Outriit (RAM 1/0)
Z
0
::r
m
General Description
Features
The RAM Input/Output
Chip if'.'
LSI device wh/ch
provides random access memor'
Peripheral interfacing for microcomputer
syste
he RAM portion
contains 1024 bits of static R
anized as 128x8,
The 1/0 portion consists of t
ripheral ports of
eight bits each. Each of the 1/0 im ln the two ports
may be defined as an input or': -output to provide
maximum flexibility. Each port
iv be read from or
written to in a parallel (8-bit b ' (mode. To improve
efficiency and simplify programrijing in control-based
applications, a single bit of 1/0 II\' either port may be
Set, cleared or read with a single rrilcTOprocessor instruction. ,ln addition to basic 1/0, one\of the ports, port A,
may be programmed to operate!1 in several types of
strobed mode with handshake. St(obed mode together
with optional interrupt operation permit both high
speed parallel data transfers and:, interface to a wide
variety of peripherals with no external logic.
0
128x8RAM
0
Single +5-volt power s' plV
0
Low power dissipatio
~
~
0
0
1/0 port A has TRI-S
0
-....
CD
Fully static operation
Completely TTL com
Two 8-bit programma
0
.
~
CD
ibl~Î"
c::r
'1/0 ports
ji
;J'El!!>capability
0
Handshake controls
strobed mode of operation
0
Single bit 1/0 operati
with single instruction
0
Reduces system packs
cou nt
0
Direct interface with
Independent
::a
»
i:
JMP
operatio"
f RAM and 1/0
"
-~
"g
C
-.......
0'
C
'tJ
C
-::a
»
s:
MICROBUS"TM* comfible
,
,
,
MICROBUSTM
Configuration
ADDRESS
BUS
CPU'
GRO~
DATA
BUS
CONTRDl
BUS
M
1
C
:::
0
-
PORT BUS
'1'
cs
~
B MEMR
INS8154
PORT.
,BUS
U
S MEMW
RUET
INRI
NOTE
Th,INTR.g",,1 be.oma_o.ly
"'ob,d mod, wh,. 0 do" "0
"..n,d,
*Trademark, National Semlconductor
197BNotlonal
Semiconductor
Corp,
0.
'<
ëo
tU
_0
-
The RAM 1/0 is an n-channe! silicon gate device
packaged in a 40-pin dual-in-li". package. It operates
',y and is fully TTL
~th a single 5.volt power SUItP
c<Jmpatible.
INS8154
-z
en
1. th,
hu
Corp,
DA,B15M4B/Printad
in U.s.A.
c'c.,
Absoll'te
Mr~imum
Ratlngs*
-0.5V to +7.0V
Voltage at Any Pin
OoC to +70°C
Operating Temperature Range
-65°C to +150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 seconds)
.
Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. Continuous operation
at these limits is net intended; operation should be limited to those
conditions specified under Electrical Characteristics.
DC Electrlcal Characteristics
(T A within operating temperature
range, VCC = 5 V:t 5% unless otherwise specified.)
VIH
Logical 'T'Input
-0.5
Logical "0" Input Voltage
VOH
Logical "1" Output Voltage
lU
ILO
ICCI
Logical "0" Output Voltage
Units
Max
2.0
Voltage
VIL
VOL
Typ
Min
Conditions
Parameter
VCC+0.5
V
0.8
V
V
2.4
IOH = -1 00 !lA
V
0.4
IOL = 2.0 mA
Input Load Current
VIN = OV to 5.25V
:tl0
Output Leakage Current
High Impedance State
:tl0
!lA
60
mA
45
Ail Outputs Open, TA = 25°C,
NRST';;; 0.8V
Power Supply Current
!lA
AC Electrical Characteristics
(TA within operating temperature
seo Notl1.)
range, VCC = 5V :t 5% unless otherwise specified Min
Conditions
Parameter
Typ
Max
Units
1
\.
READ CYCLE
tsw
tSI
STB .j.to IBF t Delay (Mode 2 Only)
tps
Peripheral Setup
tpH
Peripheral Hold
tAH
Address Hold
tCH
CS Hold
tRD
NRDS.j. to Data Valid
tA
Access
tco
Chip Select to Output
tOH
Data Valid After NRDS t
ns
300
STB Pulse Width (Mode 2 Only)
250
ns
50
ns
120
ns
50
ns
ns
50
0
350
ns
560
ns
520
ns
ns
125
75
Output Load Capacitance
pF
WRITE CYCLE
twc
Write Cycle (for RAM)
tAS
Address Setup
tAH
Address Hold
tcs
CS Setup
tCH
CS Hold
tDS
Data Setup
tDH;
Data Hold
700
ns
50
ns
0
ns
50
ns
0
ns
ns
50
l
'
2
50
'l
" ns
.
,AC Electrical Characteristics (cont'd)
Min
Conditions
Parameter
WRITE
,
(,,"
Typ
Max
Units
CYCLE
twp
NWDS Pulse Width
tAO
ACK t ta OBF t (Modes
tACW
ACK Pulse Width (Modes 3 & 4 Only)
ns
300
250
3 & 4 Only)
ns
ns
300
tWD
Port Data Val id After NWDS t
300
ns
tpE
ACK t ta Valid Output (Mode 4 Only)
300
ns
tPD
ACK t ta Hi-Z (Mode 4 Only)
0
Output Load Capaeitanee
tWRST
ns
125
75
300
Master Reset Pulse Width
Note 1: Ail tlmes measured Irom a valid logie
2.0 V.
"0" leve! = 0.8 V or a valid logie "1" level =
Read Cycle
1-""1
m"'.-",~
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l
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I~M'",2
--y-
I~
1
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1-'" -1 ""1"""',:';;i~~1 l
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1=- ',+ i --1
1
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CS" CS,
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1-ti:Y=-
"OS
--1
'eo
"'1'
1-
1- -1"'1,
BUS
- - - - - - - - - - _H~
- - - - - - - - - -~~---,
Write Cycle
I-owcyc
'",-'OO.MIIO
mm ffi
IF"'
1-"'---1
RAMI--
"-1
[-'" 1
;"'DA~
==>EI=:Ir
X-
,ATABOS
1
,,;
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,wos
I~~
,"HI"""
",-
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I~~
I-,wo~
nH"'::P::~
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pF
ns
INS81$4 Blofk Diagram
116-19,21-241
PA7-PAD
READ
WRITE
CONTROl
lOGIC
OUTPUT
DEFINITION
REGISTER
A
INTR
DATA
BUS
8UFFER
18-15)
D87-DBD
OUTPUT
DEFINITION
REGISTER
B
139,1-7)
PB7-PBD
12B.8
RAM
~VCC
..Jlli-GRD
132.261
A06-AO
-.......
Pin Configuration
PB8
'"PB4
P83
PB2
40
39
31
37
35
J5
34
33
32
Vcc
PB7
...S
DB'
DB5
3
4
S
6
7
B
9
10
11
31
3D
AD5
054
OB3
082
12
29
AD3
13
AD2
OBI
14
2B
27
080
15
26
AD'
AOO
PA7
16
25
INTR
17
24
PAO
18
19
20
23
22
PAl
PA2
27
PA3
PB'
P80
08)
PA'
PAS
PA4
GND
INS8154
NRDS
NRST
ëSii
CSI
MliO
A06
AD4
Pin Names
DBU
AD'-AOO
NRST
DATA
MilO
CSU, CSI
MEMORYIID
NWOS
WRITESTROBE
NRDS
REAOSTROBE
PA7-PAO
PORT A
PB7-P80
PORT B
INTR
INTERRUPT
Vcc
GNO
"VOLTS
OB7
BUS
ADDRESS
INPUT
RESET INPUT
SElECT
CHIP SElECTS
O"'OlTS
4
REOUEST
Basic Functional
Description
~
The RAM 110 performs two separate but important
functions
in microcomputer
systems. The first is data storage
provided by the 128 x 8 RAM. The second function
is peripheral interfacing
provided by the two 8-bit 110 ports. The
ability to program the configuration
and operating modes of the 110 ports allows interfacing a microcomputer
to a wide
varity of peripherals with minimum external logic. Major functional
blocks of the chip are shown in the block diagram;
an operational
summary of the chip is provided in figure 1. A description
of the chip pinouts and a summary of the
internai chip registers is given below.
(DB7 - DBO) Data Bus Buffers
and readout
six-transistor
RAM.
The data bus buffer is a TR I-ST A TE, bidirectional,
8-bit
buffer that is used to interface the RAM 110 to a microcomputer data bus. Data, control, and status information
is transmitted
to and received from the RAM 110 via the
data bus buffers. Execution of a STORE instruction
by
the microprocessor
may be used to transmit
data and
control
information
trom the CPU to the RAM 110.
Execution
of a LOAD instruction
may be used to transmit data and status information
trom the RAM 110 to
the CPU.
(MDR)
is nondestructive.
The RAM is a standard
cell similar in design to the 2102A static
Mode Definition
Register
The Mode Definition
Register is an internai control
register that determines the operating mode of port A.
This register is write on/y. If a read operation
is performed with the address set to that of the MDR, the
data bus will remain in the high Impedance state.
(CSO and CS1) Chip Select 1nputs
(PA7 - PAO, PB7 - PBO) Peripheral
The combination
of a low on CSO and a high on CS1
input pins enables communication
between the RAM
110 and the microprocessor.
The RAM 110 contains two eight bit 110 ports: port A
and port B. Each port consists of an eight-bit output
data latch with buffer and an eight-bit input data latch.
(MilO)
Memory
1/0 Select
~_I
Ports A and B
flexibility
is provided with the ability to define any
bit -ô1' the two ports either as an input or as an output.
Bit set, clear and read of ail 110 pins are also provided.
Moreover, port A may be aperated in strabed input or
strobed output modes.
The state of the MilO input pin determines whether
communication
between the CPU and RAM 110 chip
will in~
RAM portion of the RAM 110 or the 110
portion.
A high on M/iO selects the RAM while a low
selects the 110.
Output
Definition
Registers - ODRA
and ODRB
Associated with each port is an output definition regist'
(NRDS)
NRDS is an active-Iow
enables data or status
RAM 110.
read strobe. A low on this
information
to be read trom
pin
the
(NWDS) Write Strobe
NWDS is an active-Iow
enables data or contrai
the RAM 110.
{
(ODR).
Each ODR is an eight-bit
latch that defines
which of the 110 pins in the respective port are to be
used as outputs. ODRA contrais the direction of port
A and ODRB contrais the direction
of port B. Both
ODRs are write on/y registers. If a read operation
is
performed
with the address set to that of an ODR, the
data bus will remain in the high Impedance state.
Read Strobe
write strobe. A low on this pin
information
to be written into
(lNTR)
Interrupt
Request
The interrupt
request (lNTR) output is an active high
signal used to interrupt
the microprocessor
when a
strobed mode data transaction
has occured. This signal
is active only when port Ais in the strobed mode. INTR
will be set to a low when a master reset is applied (N RST
set low).
(AD6 - ADO) Address Inputs
The address input bus determines where in the RAM 110
communication
will take place. When the RAM is
selected, the address bus determines which of the 128
bytes of RAM will be read trom or written into. When
(NRST)
110 is selected, the address determines
which 110 or
control register will be enabled for communication
with
the CPU. These pins are normally connected to the seven
low address lines of the microprocessor.
Master Reset
NRST is the master reset input for the RAM 110 chip.
A low on this pin clears ail registers in the 110 portion
of the chip (MDR, ODRA, ODRB, and the port output
data latches) and places the data bus in the high impedance state independent
of any other control
strobes.
After a master reset, the 110 ports will both be in the
basic 110 mode and configured
as inputs. The master
reset does not change any data previously stored in the
RAM and does not allow data to be written into or read
from the RAM while NRST is low.
RAM
The RAM contained on the RAM 110 chip consists of
1024 bits organized as 128 eight-bit
bytes. Since the
RAM is fully static, no refresh or clocks are required.
Data out ,of the RAM is of the same polarity as data in,
5
Operation
NRST NRDS NWDS eso
eS1
MIlO
AG A5
A3
A4
A2
A1
AO
X
X
X
X
RAM OPERATIONS
X
X
X
X
X
X
Data Bus -->RAM
1
1
0
0
1
1
X
X
RAM -->Data Bus
1
0
1
0
1
1
X
X
Set Bit Port A
1
1
0
0
1
0
0
0
1
0
B2
B1
BO
Clear Bit Port A
1
1
0
0
1
0
0
0
0
0
B2
B1
BO
Read Bit Port A
1
0
1
0
1
0
0
0
X
0
B2
B1
BO
Set Bit Port B
1
1
0
0
1
0
0
0
1
1
B2
B1
BO
Clear Bit Port B
1
1
0
0
1
0
0
0
0
1
B2
B1
BO
Read Bit Port B
1
0
1
0
1
0
0
0
X
1
B2
B1
BO
1
1
1
1
1
1
BIT OPERATIONS
.
PORT OPERATIONS
PortA
1
0
1
0
1
0
0
1
0
0
0
0
0
Data Bus -->Port A
1
1
0
0
1
0
0
1
0
0
0
0
0
Port B -->Data Bus
1
0
1
0
1
0
0
1
0
0
0
0
1
Data Bus -->Port B
1
1
0
0
1
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
X
--> Data
CONTROL
Bus
OPERATIONS
Data Bus -+ Output
Definition
A
1
1
0
el
1
0
0
1
0
1
1
r:J
0
1
0
Ir
1
0
0
Master Reset
0
X
X
X
X
X
X
X
X
X
X
X
Data Bus -+ Hi-Z
1
1
1
0
1
X
X
X
X
X
X
Ir x
Data Bus -+ Hi-Z
1
X
X
1
X
X
X
X
X
X
X
X
X
Data Bus -+ Hi-Z
1
X
X
X
0
X
X
X
X
X
X
X
X
Data Bus -+ Output
Definition
Data Bus -+ Mode Definition
B
Register
D!SABLE FUNCTION
Figure 1. Tmth Table
G
Detailed Operation
~
'f"
RAM
The internai organization of the RAM and a typical RAM memory coli are shawn in figure 2; the 1024-bit memory is
structured in a 32-column by 32.row matrix. The proper row is selected by the five higher-order address (AD6-AD2)
inputs; the 8-bit byte ln this row is selected by eight 1-of-4 column decoders controlled by the two lower-order address
(AD l-ADO) inputs. A timing diagram of RAM read/write operations is shawn in figure 3. While RAM cannot be read
from or written into during a master reset (NRST), the reset signal does not affect the data ln RAM,
r---;D;
1
SelECT
ADG
ADS
AAM
ADO
AAAAY
J2 ADWS
J2 CDlUMNS
ADW SelECT
j DATA
1
1
ADJ
1
;;O;---'
SelECT 1
!.?~{.l
-p~-
L
ADZ
-
TYPICAl MEMDAY CEll
AOI
COlUMN DECODEAS
AOO
NAST
NADS
NWDS
M/iii
cso
CSI
-~~~iEAS
A"O/WAITE
DATA BUS
Figure 2. RAM Organization
RAM Read Operation
AD6
-
i==tA---j
1
CSOAND
XII
CSI
l-tcD
1
NADS
DATA
BUS
C
VALIDADOAESS
':
X
ADO, M/iii
l
C~
--1tCH
J:=j tDHr-
i=tAD-1
~~
HI,Z
I-tAH=i
~~-----
RAM Write Operation
AO6-ADO,M/iii
x
VAllD~:DDAESS
i==tAS--I
CSOAND
CSI
cr::=D<.
i=tcs~
DATA
BUS
>tG~
=.jtDSI-NWDS
l-tAH==!
!.=
-1 tCH
I--tDH=i
t=:~-
Figure 3. RAM R...d/Write
Timing
x=
DATA
i
1
1
1
J
Mode D..finition
i
1(egister
the data on the data bus is latched in the output
latch
on the leading edge of the write strobe. The data will
remain valid until another write ta the port with new
data occurs.
If the new data written
is the same as the
old data, then no change will occur sa long as the
proper data and strobe timing is maintained.
The mode definition
register defines the operating mode
for port A. Port B is always in the basic 1/0 mode. There
are four operating modes for port A:
Mode 1 - basic 1/0
Figure
Mode2 - strobed input
7 shows a timing diagram for basic input. Wh en
the microprocessor
reads the port, the peripheral data is
latched in the input latch on the leading edge of the read
strobe. The data bus buffers are enabled sa the contents
of the latch are gated on ta the system data bus. The
data remains latched until the end of the read cycle
(i.e., until the trailing edge of the read strobe). Latching
Mode 3 - strobed output
Mode 4 - strobed output with TRI-STATE contrai
ln mode l, basic 1/0, there is no handshaking and data
is simply written
ta or read from the specified port.
Port B is always in this mode. When NRST goes low,
bath port A and port B are set ta the basic 1/0 mode
with
ail bits set ta input.
Mode 2, strobed input,
provides a means for transferring
data !rom the peripheral into port A in response ta handshake or strobe
signais. Mode 3, strobed output,
provides a means for
transferring
data from
port A ta the peripheral
in
response ta strobes or handshake
signais. Mode 4,
strobed output with TR I-ST A TE contrai is similar ta
mode 3 ex ce pt that port A is in the high impedance
state until the handshake signal goes active. Figure 4
summarizes what data should be written into the MDR
ta place port A in the desired mode. Whenmode~ay
port A is
operated in any one of the three strobed
pins of port B are used for handshake contrai ftt11ctions;
accordingly.
only six of the eight port B pins are
available for data input/output
bits.
the input data in this manner allows the chip ta synchranize asynchronous peripheral signais with slow rise and
fall times ta the micropracessor.
.
A port Gan have some .'IOput plOS and some output plOS,
each bit in the port. A
sinGe there is an ODR latch .for
Wrlte ta a pin deflOed as an IOput will load a new value
IOta the output
data .Iatch, but sinGe the output data
buffer IS dlsabled, It will have no effect on the 1/0 plO.
A data read fram 1/0 pins defined as outputs will read
the data from the output data .Iatch. The data will be
ta be
read properly only If the 1/0 IlOes are permltted
greater th an VIH for a logic 1 output and lessthan VIL
for a logic 0 output. If the 1/0 pins are loaded in such a
the!
eli~ lo"ol.,-"re not reached, the data read will
not always agree wlth the data stored 10 the output data
latch.
Bit Set, Clear and Read
Output
Definition
Although
addressed separately from the ports, the
definition
registers are an integral part of the 1/0
ports as shawn in figure 5. This figure shows the input
data latch and output data latch/buffer of a bit in a port
and the bit of the ODR associated with it. Thus there is
one bit of an ODR associated with each peripheral 1/0
pin in port A and port B. If a low or "0" is written into
output
the ODR, the output data buffer
be disabled,
and the
high or "1" is written
output
mode. When
through 4) is defined
necessary
ta set up
ODRA
ta reading and writing each port as an eightbit parallel byte. it is also possible ta set, clear or read
any individual
bit in either port. Bit set or clear is perln addition
Registers
associated with it will
1/0 bit is in the input mode. If a
into the ODR, the 1/0 bit is in.the
strobed
mode operation
(modes 2
for port A via the MDR, it is also
proper
input/output
definition
in
formed by doing a write operation with the chip selected
and the proper address. SinGe the address determines
which bit is operated on and whether it is set or cleared,
the eight data bus lines are ail don't-care for a bit set or
clear. This permits the microprocessor ta do a bit set
or clear with a single instruction
without initially setting
up the accumulator.
The three low order bits of the
address determine which bit of the port is set or cleared
~ 0 would indicate
(e.g., AD2 ~ 0, ADl ~ 1 and ADO
(AD3) determines if port A or port
bit 2). Address bit 3
B is acted upon. Address bit 4 (AD4) determines if the
operation is a bit set or clear.
for port A.
Basic 1/0
- Mode
When a bit read is performed, the selected bit is placed
on data bus bit 7 (DB7) and ail other by
bitsreading
of the !rom
data
bus are set ta zero. The bit is selected
the chip with the same addresses described for bit set
and clear. Ali bit operations are summarized in figure 8.
1
ln the basic 1/0 mode of operation data is simply
written ta or read fram a port without handshake
signais; the interrupt request (INTR) is always low when
Besides simplifying programming in contrai
B is always in the
(M in figure 4)
basic 1/0 mode, whereas the MDR bit 5
must be set ta zero ta define port A in the basic 1/0
mode. SinGe the MDR, ODRA and ODRB are ail cleared
by a master reset, bath port A and port B will be in the
(N RST set low).
basic input mode after a master reset
port
A is operated
in this mode.
Figure 6 shows a timing
the micraprocessor
Port
diagram for basic output.
performs
a write
operation
bit operations
are used ta contrai interrupt
port A is in the strobed
mode. The timing
applications,
enable when
for bit opera-
tions is the same as that for basic input/output except
that, for bit set and bit clear operations, the data bus is a
"don't
care."
A bit set ta a pin whose
previous
value was
a "1" or a bit clear ta a pin whose previous value was a
"0" will not cause that pin ta leave its previous value,
When
even momentarily.
ta a port,
8
.\
--
DB7
DB6
DB5
TS
OUT
M
X
X
0
X
X
X
X
X
Basic 1/0
X
0
1
X
X
X
X
X
Strobed
0
1
X
X
X
X
X
Strobed Output
1
1
X
X
X
X
X
Strobed Output with TRI-STATE
DB4
DB3
DB2
DB1
DBO
Bit Location
MOR
4.
Figure
Bit Name
Input
Contrai
Mode Definition of Port A with MDR
0
SET
D
INPUT
DATA
LATCH
INTERNAL
DATA
BUS
PER!PHERAL
I/D PIN
D
0
DUTPUT
DEFINITIDN
REGISTER
Figure 5. Internai
:
1
AD'-ADD.M/iD
=xi=tAS--j
Logic of One Bit of an 1/0 Port with ODR
1
C
VALIDADDRESS
~tAH=i
PERIPHE~~\=:Y
-=:x
rnANDCS1=xt~
=-i
DATA BUS
AD'-ADD.M/iD
tcs 1--
1
~
1
DLD DATA
~
)(
C
VtALIDADD~,~SS
---j
6.
i-=
DH
NRDS~§-
-!
DATABUS
VALID NEW DATA
tRD
1-
=1
<1~LlDDATA
1
Figure
tAH
CS!! AND CS1
1-
'WD
k
tPH
~
I-'A+--I
=xTI:=IX:==
---+cHI-
===>tc:3S11-
tDs-1
~1.-tWP
NWDS
PERIPHE~~\
VALIDDATA
I-t,,-\
Figure 7. Basic Input Timing
Basic Output Timing
NRDS NWDS
A4 A3 A2 A1 AO
BIT SET & CLEAR
Bit Set, PortA
1
0
1
0
B2 B1 BO
Bit Clear, Port A
1
0
0
0
B2 B1 BO
Bit Set, Port B
1
0
1
1
B2 B1 BO
Bit Clear, Port B
1
0
0
1
B2 B1 BO
Bit Read, Port A
0
1
X
0
B2 B11 BO
Bit Read, Port B
0
1
X
1
B2 Bl
BIT READ
Selected Bit->DB7
0->DB6-DBO
BO
0, A6 0,
When CSO 0, CS1
= 1. M/iO =
=
=
&A5=0
B2, B1, & Ba select whieh bit is seleeted IBO is least signifieant bit),
1
1
Figure 8. Bit Operations
Bit Operations
Enabled
9
rtDH
r----
Strobed,lnput
(Po~ A)
-
Mode 2
This mode allows data to be read from a peripheral in a
two-step transaction. First, the peripheral strobes data
into the RAM 1/0 input latch and notifies the microprocessor that data is ready to be read. Second, the
processor reads the contents of the RAM 1/0 input latch
and resets the handshake control signais for the next
transaction to take place. Transferring data in two steps
frees the microprocessor to undertake other tasks in
between data transfers from the port A peripheral.
Figure 9 shows the signal timing and figure 10 shows a
logic diagram for the handshake signais. The handshake
control signais are as follows;
the next transaction can now take place. The microprocessor can override 1BF by doing a bit set or bit clear
to PB6.
STB (Strobe)
When enabled by lE, INTR is an output that is set on
the trailing edge of STB, requesting the microprocessor
to read the data in the port A input data latch. When
the microprocessor responds to read port A, the trailing
edge of NRDS resets INTR. Should lE notbe set, INTR
will remain low.
1E (1nterrupt Enable)
lE is the output data latch of pal, whose output is
AN Ded with the interrupt request latch to produce the
INTR signal. lE is zero after a master reset (NRST) but
may be written into trom the microprocessor by doing a
bit set/clear to PBl.
INTR (lnterrupt
The STB signal is an active-Iow strobe generated by
a peripheral to signify that data is valid at the peripheral
bus on the trailing edge of this strobe. This signal is fed
into pin PBl of the RAM 1/0. STB latches peripheral
bus data into the RAM 1/0 input data latch on its
trailing edge. This does net require the RAM 1/0 to be
selected. Should STB pulse low more than once before
the arrivai of NRDS, the data stored in the RAM 1/0
input data latch will be the fast stored data.
Reques!)
ln a multiple-interrupt
application, the microprocessor
can poil the RAM 1/0 for the existence of an interrupt
request by doing a bit read of PBl. Being able to read
the INTR status on. the microprocessor system bus is
useful in multi-interrupt schemes to find the originator
of an interrupt.
IBF (Input Butfer Full)
The IBF signal is an output from the RAM 1/0 driven
Parallel write operations to port B while port Ais in any
by pin PB6; IBF is set by the leading edge of STB and
/2f1e of its strobed modes will leave bits PB6 and PBl
is reset by the trailing edge of NRDS when the m,j.ÇII-'/
unatfected.
mus, "'"]Jort B now has 6 data 1/0 bits
processor is performing a byte-read trom pOTt A. IBF
associated with it and the handshake bits PB6 and PBl
high tells the peripheral that data is latched in the port A
respond only to valid changes in handshake status or to
input data !atch. IBF goe5 low on the traillng edge of the
bit set/bit clear operations.
microprocessor NRDS strobe to notify the peripheral
that data has been read ln the microprocessor and that
-tswSTB(lNI'PB7~'
I
~tSIC
1
~
PEAIPHEAAl
INPUT
ADO.
~
y-'
INTA (OUT)
-
:1
fi
IBF(OUT)'PB6
AD6
/
I:tPS~1 tPHr-:
VALID DATA
1
C
1
~
M/I1!
VALIDADDA~ETIc
~tA~
-1 t~HI~
r:=ex
){
CSiiANO CS1
l
-1
!=tco
I~
tCH-1
\-LY-
NADS
tAD
DATA BUS
I~
<:2ALlD
Figure 9. Strobed
Input, Mode 2 Timing
10
=1toHI~
DATA
r----
Initializing Strobed Input - Mode 2
1
Prior to operation, an initialization procedure must be
undertaken. The MDR must have a "1" written into bit
5 and a "0" written into bit 6. The ODRA must have
"Os" written into it to identify the pins in port A which
will function in mode 2. The ODRB must have a "0"
written into PB7 in order to make it an input which will
receive STB trom the peripheral. Also, PB6 must be
defined as an output so that it can drive the 1BF signal.
The remaining six lower bits of ODRB are configured as
needed for the basic input/output transactions occuring
in port B.
TS OUT
~
07
Handshake Status
Handshake status control signais IBF and INTR will be
reset by a microprocessor LOAD instruction only if it
is addressed to port A as a byte read. A parallel write or
bit write or bit read to port A will not affect handshake
status. A byte read or write to port B will not affect
handshake status either, since PB6 and PB7 are masked
from byte writes to port B wh en port A is in any of its
strobed modes. It is possible, however, to override IBF
or lE by an appropriate bit write to PB6 or PB7, respectively.
M
MOR
06
05
DO
Mode 2
OORE>
10111-1-1-1-1-1-1
07
1
Writing to the MDR to define mode 2 operation will
automatically initialize both 1BF and 1NTR in such a
manner that they will be expecting the peripheral to
begin the first 1/0 transaction with a STB strobe, i.e.,
both 1NTR and 1BF will initialize low when the abave
write to the MDR takes place.
06
DO
ODRA
= "Os" at mode
2 pins.
Mo'
MoO
PB'
INPUT
DATA
LATeH
BIT SET
PB'
INTERNAl
D~
PIN
"'INPUT
(STBI
PB'
DUTPUT
DATA
lATeH
IIEI
BITClEAR
PB'
0
0
11IIIJJIJ:..
DEFINITIDN
REGISTER
INTR
DUTPUT PIN
D
D
INTERRUPT
REDUEST
lATeH
HANDSHAKE
lDGle
PB6
INPUT
DATA
lATCH
BITSET
PB6
PB6
DUTPUT PIN
(lBF)
./
BIT CLEAR
PB6
D
D
DUTPUT
DEFINITIDN
REGISTER
Figure 10. Strobed Input: Mode 2 Handshake
11
Logic
Strobed
/Jutput
(l'çrt
A) -- Mode
OBF (Output
3
This mode allows
outputting
data trom the CPU to an
asynehronous
peripheral.
The
CPU
writes
into
the
output
latch of the RAM 1/0; in turn this ereates a handshake signal whieh notifies
the peripheral
that its bus has
new data on it. The peripheral
reads the port A bus and
returns
the handshake
signais
to their
previous
state,
awaiting
the next
CPU write.
The peripheral
bus is
always being driven
by the port A butters
in this mode.
Pertinent
timing
a logie diagram
jn figure 12.
relationships
showing
the
The handshake
following:
signais
ACK
are shown
handshake
assoeiated
with
lE (lnterrupt
in figure 11 and
signais is shown
mode
This
3 are the
-+CH[-
-! 'DHr-
ŒS~
1
,-b
l
,-rI
~'--
:~M'
1
PB&
1
ACO IINI'
---1
--t:J
INTR (OUT)
DBF (OUTI'
Request)
Ea==J<
1
NWDS
(lnterrupt
L
PB)
~
:
OlD DATA
1
:"\{
-'~CW
I
){
V;"D
NEWDATA
1
Figure Il.
l;
1
'
tWD::1
PERIPHERAl BUS
2.
l-'AH-1
CSO
AND
CS,
=x=c=o<,
-l'DS!-DATABUS
Enable)
Strobed
edge of
when a
The value of INTR
Gan be read from the CPU data bus
side by means
of a bit read to PB7. This is useful
in
locating
the originator
of an interrupt
in a multi.interrupt
seheme.
t='AS--j
j-'CS.J
j
is the sa me as for mode
INTR
ACK is an aetive-Iow
strobe
generated
by peripheral
to
read the data present
on its bus. ACK drives the RAM
1/0 PB7 input and it sets the OBF signal on its leading
edge and sets the INTR
on its trailing
edge; for this to
happen,
the RAM 1/0 need not be selected.
=x
Full)
When enabled
by lE, INTR is set on the trailing
ACK
and reset on the trailing
edge of NWDS
byte write to port A occurs.
(Acknowledge)
AD&-ADO;M/fII
Butter
OBF is an active-Iow
signal generated
by RAM 1/0 PB6
output.
OBF goes low in response to the trailing edge of
NWDS for a parallel
write to port A and returns
high on
the leading
edge of ACK. OBF being low signais to the
peripheral
that valid data is now ready to be read on the
peripheral
bus.
Output,
12
Mode
3 Timing
Initializing Strobed Output
-
Mode 3
Writing ta the MDR ta define mode 3 operation will
automatically initialize bath OBF and 1NTR such that
the RAM 1/0 will be expecting the first strobed operation ta take place. Bath 1NTR and OBF are initialized
high for mode 3, provided lE is set ta a "1." If lE is
set ta "0," INTR will not initialize high.
Ta initialize for mode 3 operation, the MDR must have
"1s" written into bits 5 and 6. A "0" must alla be
written into bit 7.
The ODRA must have "1s" written into it ta identify
the bits of port A which will function in mode 3. The
ODRB must have a "0" in PB7 in order ta make it an
input which will receive ACK from the peripheral. Also,
PB6 must be defined as an output sa that it can drive
the OBF signal. The remaining 6 lower order bits of port
B are configured as needed for the basic 1/0 transactions
occurring in port B.
Handshake Status - Mode 3
Handshake status contrai signais OBF and INTR will be
reset low by a CPU STOR E instruction only if it is
addressed ta port A as a paraI/el write. A parai le! read or
any bit operation ta port A will net affect handshake
status. A ward read or write ta port B will not affect
handshake status either, since PB6 and PB7 are masked
from ward writes ta port B when port A is in any of its
strobed modes. It is possible, however, ta override OBF
or 1E by an appropriate bit write ta PB6 or PB7, respectively.
TS OUT M
MDR
1011111-1-1-1-1-1
DO
Dl
~Dl
Mode 3
ODRB
DO
ODRA = "15" at mode 3 pins.
M'1
M'B
BIT SET
PB7
INPUT
OATA
LATCH
PB'
INTERNAL
OATA
BUS
0
PB'
OUTPUT
OATA
LATCH
(lE)
0
PB'
INPUT
PIN
(ACK)
BITeLEAR
'"
0
0
OUTPUT
OEFINITION
REGISTER
0INTERRUPT0
.
INTR
OUTPUT
PIN
PB'
OUTPUT
PIN
REaUEST
LATCH
HANOSHAKE
LOGIe
PB'
INPUT
OATA
LATCH
BIT SET
PB'
10B'I
BIT CLEAR
PB'
0
0
OUTPUT
OEFINITION
REGISTER
,
Figure 12. Strobed Output, Mode 3 Handshake
13
Logie
Strobed I)utput witl1 TRI-STATE Contrai -- Mode 4
. TS OUT
07
E~
"1s" at mode 4 pins.
Writing to the MDR to defi~ode
4 operation will
automatically initialize both OBF and 1NTR high such
that the RAM 1/0 will be expecting the first strobed
operation to take place, provided 1E is set to a "1."
If not, INTR will not be initialized high.
Handshake Status - Mode 4
Handshake status contrai signais OBF and 1NTR will be
reset low by a cru STORE instruction only if it is
addressed to port A as a parallel write. A parallel read or
any bit operation to port A will not affect handshake
status. A word read or write to port B will not affect
handshake status either, since PB6 and PB7 are masked
from word writes to port B wh en port A is ln any of its
strobed modes. It is possible, however. to override OBF
or 1E by an appropriate bit write to PB6 or PB7, respectively.
j-tAH--j
-+cHI-
ëSiiANOCS1~=c)<
-1 tOHr--
=1tosr--
~8
DATABUS
Nwos~J
.~
.~ r
INTR (DUT)
DB'
(DUT)'
PB6
1
~"
,-/
.
1
hAO1
,~
-tACW
..
(lN) , PB7
AC'
l~
l
HI.Z
tpo
r-
HI.Z
-<} VAlIOOATA ---1
Figure 13. Strobed Output wit'h TRI-STATE Mode 4 Timing
14
~Y
--1 1:= =1
tPE
PERIPHERAlBUS
Mode 4
DO
ODRA;
Initializing Strobed Output -- Mode 4
I:tcs-J
DO
10111-1-1-1-1-1-loDRB
To initialize for mode 4 operation, the MDR must have
"1s" written into bits 5, 6, and 7. The ODRA must have
"1s" written into it to identify the bits of port A which
will function in mode 4. The ODRB must have a "0" in
bit 7 and a "1" in bit 6.
I:=tAS--j
MDR
07
The cru writes into the output latch of the RAM 1/0;
this resets INTR and OBF but the peripheral bus remains
in TRI-STATE until the peripheral responds with a lowgoing ACK strobe. The ACK strobe enables the RAM
1/0 port output buffers to drive the peripheral bus active
during this strobe time. The leading edge of ACK sets
the OBF and the trailing edge of ACK sets 1NTR. The
trailing edge of NWDS for a byte write to port A resets
both OBF and 1NTR the same as in mode 3.
AO6-AOO;M/ii!~
M
1111111-1-1-1-1-1
This mode is similar to mode 3 in that It uses the same
handshake signais and transfers data in the same direction. A timing diagram for mode 4 is shown in figure 13.
Handshake logic is shown in figure 12. The main
difference from mode 3 is the fact that the peripheral
bus is in the TRI-STATE condition at ail times except
when ACK is low, enabling the RAM 1/0 to drive the
peripheral bus to its valid state.
1
SC!MP
RAM-IIO
ADOD ADO6
-
ADOO-ADI0
ADO -AD6
+5V
M/rn
CS,
SIN
sour
ëSO
S8
INS8060
FO
INS8154
-=
NRDS
NRDS
FI
F2
NWDS
NWDS
SENSE A
INTR
D8 10 - 71
D810- 71
NRST
NRST
RESET
OUT 10- 7)
AD 10-101
256
TO
2048
8YTE ROM
A 10-10)
AD11
CSI
"
NRDS
Figure 14,
Three-Chip
Typical
Application
and up to 2048 Bytes of ROM
A'5-AO
-
SC/MP System with 128 Bytes of RAM, 22 Bits of 1/0
"\..
AI5-AO
CSI
'1'>CS'
.
D81N
D7-00
MEMR
MEMW
I/DR
I/OW
INS8228
. .
ST518
>--
PORTS 8US
M/fii
INT
02
M
1
C
~R
8
~0
U
5
CSO
MEMR
.
RESET
Io..RESET
MEMW
NW05
RESET
NR5T
INTR
INTR
D7-DO
TV
A11
MEMR
INS8154
NROS
OUT
AI0-AO
INS8224
+-+
D87-D80
ffi
CS"
07-DO
AffiN
AD5-AOO
07-DOI
ëSii
~CHIP
SELECT
WR
01
PORTA 8US
A6-AO
~lOGIC
(lNS82l504)
INS8080A
ëS2
:
A
CS,
255
TD
2048
8YTE ROM
CS2
4D~
Figure 15,
Application
2048 Bytes of ROM
Typical
-
INS8080 System with 128 8ytes of RAM, 16 Bits of 1/0 and up to
15
-
0
::::
Physical Dimensions
'"
::!:
'
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a:
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0-
0.0J2
1D.8111
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1D.45HOS1} If--
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131151
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40-lead
Ceramic Dual-in-line Package (0)
Order Number INS8154D
ex)
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.:-:~
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C'i
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0.062
T""
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0.050
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Information
N"""'s.m""'"""
",',,","
2900
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005
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Plastic Dual-in-line Package (N)
Order Number INS8154N
For "N" Package:
For "0" Package:
737.5000
TWX(910)
"I;
'"
The RAM 1/0 device may be ordered through the local National Semiconductor
our world or international headquarters listed below,
~
~0'0,
11.27"
"'9240
N""", S.m""'"",,
8000
21
61/2 Mu"h"
GmbH NS
"'""'",,",,
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M'y"'8",",,0
'~9YoI;oy,
160
Toky,J4Pôo Sh"IO"" '0
)031355.3711
T" 2322015 NSC;IJ
TWX
sales representative
or by contacting
INS8154N
INS8154D
NS
00 a,,;JI
,H", a"DI Lld NS
L,m, B44
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8thf'",
A",
B"o;O""
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341124J.B
73866 NSEH'
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T"..32O96
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