INTEL 82C55

82C55A
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y
Compatible with all Intel and Most
Other Microprocessors
Y
High Speed, ‘‘Zero Wait State’’
Operation with 8 MHz 8086/88 and
80186/188
Y
24 Programmable I/O Pins
Y
Low Power CHMOS
Y
Completely TTL Compatible
Y
Control Word Read-Back Capability
Y
Direct Bit Set/Reset Capability
Y
2.5 mA DC Drive Capability on all I/O
Port Outputs
Y
Available in 40-Pin DIP and 44-Pin PLCC
Y
Available in EXPRESS
Ð Standard Temperature Range
Ð Extended Temperature Range
The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose
programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In
MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used
for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.
The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin
DIP and 44-pin plastic leaded chip carrier (PLCC) packages.
231256 – 31
231256 – 1
Figure 1. 82C55A Block Diagram
231256 – 2
Figure 2. 82C55A Pinout
Diagrams are for pin reference only. Package
sizes are not to scale.
October 1995
Order Number: 231256-004
82C55A
Table 1. Pin Description
Symbol
PA3–0
Pin Number
Dip
PLCC
Type
Name and Function
1–4
2–5
I/O
PORT A, PINS 0 – 3: Lower nibble of an 8-bit data output latch/
buffer and an 8-bit data input latch.
RD
5
6
I
READ CONTROL: This input is low during CPU read operations.
CS
6
7
I
CHIP SELECT: A low on this input enables the 82C55A to
respond to RD and WR signals. RD and WR are ignored
otherwise.
GND
7
8
A1–0
8–9
9–10
System Ground
I
ADDRESS: These input signals, in conjunction RD and WR,
control the selection of one of the three ports or the control
word registers.
A1
A0
RD
WR
CS
Input Operation (Read)
0
0
0
1
0
Port A - Data Bus
0
1
0
1
0
Port B - Data Bus
1
0
0
1
0
Port C - Data Bus
1
1
0
1
0
Control Word - Data Bus
0
0
1
0
0
0
1
1
0
0
Data Bus - Port B
1
0
1
0
0
Data Bus - Port C
1
1
1
0
0
Data Bus - Control
X
X
X
X
1
Data Bus - 3 - State
X
X
1
1
0
Data Bus - 3 - State
Output Operation (Write)
Data Bus - Port A
Disable Function
PC7–4
10–13
11,13–15
I/O
PORT C, PINS 4 – 7: Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input buffer (no latch for input). This port
can be divided into two 4-bit ports under the mode control. Each
4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports
A and B.
PC0–3
PB0-7
14–17
16–19
I/O
PORT C, PINS 0 – 3: Lower nibble of Port C.
18–25
20–22,
24–28
I/O
PORT B, PINS 0 – 7: An 8-bit data output latch/buffer and an 8bit data input buffer.
VCC
26
29
D7–0
27–34
30–33,
35–38
I/O
RESET
35
39
I
RESET: A high on this input clears the control register and all
ports are set to the input mode.
WR
36
40
I
WRITE CONTROL: This input is low during CPU write
operations.
37–40
41–44
I/O
PA7–4
NC
2
1, 12,
23, 34
SYSTEM POWER: a 5V Power Supply.
DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus.
PORT A, PINS 4 – 7: Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input latch.
No Connect
82C55A
82C55A FUNCTIONAL DESCRIPTION
General
The 82C55A is a programmable peripheral interface
device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the 82C55A is programmed by the system
software so that normally no external logic is necessary to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is
transmitted or received by the buffer upon execution
of input or output instructions by the CPU. Control
words and status information are also transferred
through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the
internal and external transfers of both Data and
Control or Status words. It accepts inputs from the
CPU Address and Control busses and in turn, issues
commands to both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the
CPU ‘‘outputs’’ a control word to the 82C55A. The
control word contains information such as ‘‘mode’’,
‘‘bit set’’, ‘‘bit reset’’, etc., that initializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B)
accepts ‘‘commands’’ from the Read/Write Control
Logic, receives ‘‘control words’’ from the internal
data bus and issues the proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 – C4)
Control Group B - Port B and Port C lower (C3 – C0)
The control word register can be both written and
read as shown in the address decode table in the
pin descriptions. Figure 6 shows the control word
format for both Read and Write operations. When
the control word is read, bit D7 will always be a logic
‘‘1’’, as this implies control word mode information.
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C).
All can be configured in a wide variety of functional
characteristics by the system software but each has
its own special features or ‘‘personality’’ to further
enhance the power and flexibility of the 82C55A.
Port A. One 8-bit data output latch/buffer and one
8-bit input latch buffer. Both ‘‘pull-up’’ and ‘‘pulldown’’ bus hold devices are present on Port A.
Port B. One 8-bit data input/output latch/buffer.
Only ‘‘pull-up’’ bus hold devices are present on Port
B.
Port C. One 8-bit data output latch/buffer and one
8-bit data input buffer (no latch for input). This port
can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4-bit latch and it
can be used for the control signal outputs and status
signal inputs in conjunction with ports A and B. Only
‘‘pull-up’’ bus hold devices are present on Port C.
See Figure 4 for the bus-hold circuit configuration for
Port A, B, and C.
3
82C55A
231256 – 3
Figure 3. 82C55A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
*NOTE:
231256 – 4
Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset.
Figure 4. Port A, B, C, Bus-hold Configuration
4
82C55A
82C55A OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation that can
be selected by the system software:
Mode 0 Ð Basic input/output
Mode 1 Ð Strobed Input/output
Mode 2 Ð Bi-directional Bus
When the reset input goes ‘‘high’’ all ports will be set
to the input mode with all 24 port lines held at a logic
‘‘one’’ level by the internal bus hold devices (see
Figure 4 Note). After the reset is removed the
82C55A can remain in the input mode with no additional initialization required. This eliminates the need
for pullup or pulldown devices in ‘‘all CMOS’’ designs. During the execution of the system program,
any of the other modes may be selected by using a
single output instruction. This allows a single
82C55A to service a variety of peripheral devices
with a simple software maintenance routine.
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as
required by the Port A and Port B definitions. All of
the output registers, including the status flip-flops,
will be reset whenever the mode is changed. Modes
may be combined so that their functional definition
can be ‘‘tailored’’ to almost any I/O structure. For
instance; Group B can be programmed in Mode 0 to
monitor simple switch closings or display computational results, Group A could be programmed in
Mode 1 to monitor a keyboard or tape reader on an
interrupt-driven basis.
231256 – 6
Figure 6. Mode Definition Format
The mode definitions and possible mode combinations may seem confusing at first but after a cursory
review of the complete device operation a simple,
logical I/O approach will surface. The design of the
82C55A has taken into account things such as efficient PC board layout, control signal definition vs PC
layout and complete functional flexibility to support
almost any peripheral device with no external logic.
Such design represents the maximum use of the
available pins.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset
using a single OUTput instruction. This feature reduces software requirements in Control-based applications.
231256 – 5
Figure 5. Basic Mode Definitions and Bus
Interface
When Port C is being used as status/control for Port
A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were data output
ports.
5
82C55A
Interrupt Control Functions
When the 82C55A is programmed to operate in
mode 1 or mode 2, control signals are provided that
can be used as interrupt request inputs to the CPU.
The interrupt request signals, generated from port C,
can be inhibited or enabled by setting or resetting
the associated INTE flip-flop, using the bit set/reset
function of port C.
This function allows the Programmer to disallow or
allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure.
INTE flip-flop definition:
231256 – 7
Figure 7. Bit Set/Reset Format
(BIT-SET)ÐINTE is SETÐInterrupt enable
(BIT-RESET)ÐINTE is RESETÐInterrupt disable
Note:
All Mask flip-flops are automatically reset during
mode selection and device Reset.
6
82C55A
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No ‘‘handshaking’’
is required, data is simply written to or read from a
specified port.
Mode 0 Basic Functional Definitions:
# Two 8-bit ports and two 4-bit ports.
#
#
#
#
Any port can be input or output.
Outputs are latched.
Inputs are not latched.
16 different Input/Output configurations are possible in this Mode.
MODE 0 (BASIC INPUT)
231256 – 8
MODE 0 (BASIC OUTPUT)
231256 – 9
7
82C55A
MODE 0 Port Definition
A
B
GROUP A
D4
D3
D1
D0
PORT A
0
0
0
0
OUTPUT
PORT C
(UPPER)
OUTPUT
0
0
0
1
OUTPUT
OUTPUT
0
0
1
0
OUTPUT
0
0
0
1
1
0
1
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
GROUP B
Ý
PORT B
0
OUTPUT
PORT C
(LOWER)
OUTPUT
1
OUTPUT
INPUT
OUTPUT
2
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
3
4
INPUT
OUTPUT
INPUT
OUTPUT
1
OUTPUT
INPUT
5
OUTPUT
INPUT
0
1
OUTPUT
OUTPUT
INPUT
INPUT
6
7
INPUT
INPUT
OUTPUT
INPUT
0
0
0
1
INPUT
INPUT
OUTPUT
OUTPUT
8
9
OUTPUT
OUTPUT
OUTPUT
INPUT
0
0
1
1
1
1
0
0
0
1
0
1
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
10
11
12
13
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
1
1
1
1
0
1
INPUT
INPUT
INPUT
INPUT
14
15
INPUT
INPUT
OUTPUT
INPUT
MODE 0 Configurations
231256 – 10
8
82C55A
MODE 0 Configurations (Continued)
231256 – 11
9
82C55A
MODE 0 Configurations (Continued)
231256 – 12
Operating Modes
MODE 1 (Strobed Input/Output). This functional
configuration provides a means for transferring I/O
data to or from a specified port in conjunction with
strobes or ‘‘handshaking’’ signals. In mode 1, Port A
and Port B use the lines on Port C to generate or
accept these ‘‘handshaking’’ signals.
Mode 1 Basic functional Definitions:
# Two Groups (Group A and Group B).
# Each group contains one 8-bit data port and one
4-bit control/data port.
# The 8-bit data port can be either input or output
Both inputs and outputs are latched.
# The 4-bit port is used for control and status of the
8-bit data port.
10
82C55A
Input Control Signal Definition
STB (Strobe Input). A ‘‘low’’ on this input loads
data into the input latch.
IBF (Input Buffer Full F/F)
A ‘‘high’’ on this output indicates that the data has
been loaded into the input latch; in essence, an acknowledgement. IBF is set by STB input being low
and is reset by the rising edge of the RD input.
INTR (Interrupt Request)
A ‘‘high’’ on this output can be used to interrupt the
CPU when an input device is requesting service.
INTR is set by the STB is a ‘‘one’’, IBF is a ‘‘one’’
and INTE is a ‘‘one’’. It is reset by the falling edge of
RD. This procedure allows an input device to request service from the CPU by simply strobing its
data into the port.
INTE A
Controlled by bit set/reset of PC4.
INTE B
231256 – 13
Controlled by bit set/reset of PC2.
Figure 8. MODE 1 Input
231256 – 14
Figure 9. MODE 1 (Strobed Input)
11
82C55A
Output Control Signal Definition
OBF (Output Buffer Full F/F). The OBF output will
go ‘‘low’’ to indicate that the CPU has written data
out to the specified port. The OBF F/F will be set by
the rising edge of the WR input and reset by ACK
Input being low.
ACK (Acknowledge Input). A ‘‘low’’ on this input
informs the 82C55A that the data from Port A or Port
B has been accepted. In essence, a response from
the peripheral device indicating that it has received
the data output by the CPU.
INTR (Interrupt Request). A ‘‘high’’ on this output
can be used to interrupt the CPU when an output
device has accepted data transmitted by the CPU.
INTR is set when ACK is a ‘‘one’’, OBF is a ‘‘one’’
and INTE is a ‘‘one’’. It is reset by the falling edge of
WR.
INTE A
Controlled by bit set/reset of PC6.
INTE B
Controlled by bit set/reset of PC2.
231256 – 15
Figure 10. MODE 1 Output
231256 – 16
Figure 11. MODE 1 (Strobed Output)
12
82C55A
Combinations of MODE 1
Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed
I/O applications.
231256 – 17
Figure 12. Combinations of MODE 1
Operating Modes
Output Operations
MODE 2 (Strobed Bidirectional Bus I/O).This
functional configuration provides a means for communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving
data (bidirectional bus I/O). ‘‘Handshaking’’ signals
are provided to maintain proper bus flow discipline in
a similar manner to MODE 1. Interrupt generation
and enable/disable functions are also available.
OBF (Output Buffer Full). The OBF output will go
‘‘low’’ to indicate that the CPU has written data out
to port A.
MODE 2 Basic Functional Definitions:
INTE 1 (The INTE Flip-Flop Associated with
OBF). Controlled by bit set/reset of PC6.
# Used in Group A only.
# One 8-bit, bi-directional bus port (Port A) and a 5bit control port (Port C).
# Both inputs and outputs are latched.
# The 5-bit control port (Port C) is used for control
and status for the 8-bit, bi-directional bus port
(Port A).
Bidirectional Bus I/O Control Signal Definition
INTR (Interrupt Request). A high on this output can
be used to interrupt the CPU for input or output operations.
ACK (Acknowledge). A ‘‘low’’ on this input enables
the tri-state output buffer of Port A to send out the
data. Otherwise, the output buffer will be in the high
impedance state.
Input Operations
STB (Strobe Input). A ‘‘low’’ on this input loads
data into the input latch.
IBF (Input Buffer Full F/F). A ‘‘high’’ on this output
indicates that data has been loaded into the input
latch.
INTE 2 (The INTE Flip-Flop Associated with IBF).
Controlled by bit set/reset of PC4.
13
82C55A
231256 – 18
Figure 13. MODE Control Word
231256 – 19
Figure 14. MODE 2
231256 – 20
Figure 15. MODE 2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK, and STB occurs before RD is permissible.
(INTR e IBF # MASK # STB # RD a OBF # MASK # ACK # WR)
14
82C55A
231256 – 21
Figure 16. MODE (/4 Combinations
15
82C55A
Mode Definition Summary
MODE 0
MODE 1
OUT
IN
OUT
GROUP A ONLY
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Ý
Ý
Ý
Ý
Ý
Ý
Ý
Ý
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Ð
Ð
Ð
Ð
Ð
Ð
Ð
Ð
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
INTRB INTRB
IBFB OBFB
STBB ACKB
INTRA INTRA
STBA
I/O
IBFA
I/O
I/O
ACKA
I/O
OBFA
Special Mode Combination Considerations
There are several combinations of modes possible.
For any combination, some or all of the Port C lines
are used for control or status. The remaining bits are
either inputs or outputs as defined by a ‘‘Set Mode’’
command.
During a read of Port C, the state of all the Port C
lines, except the ACK and STB lines, will be placed
on the data bus. In place of the ACK and STB line
states, flag status will appear on the data bus in the
PC2, PC4, and PC6 bit positions as illustrated by
Figure 18.
Through a ‘‘Write Port C’’ command, only the Port C
pins programmed as outputs in a Mode 0 group can
be written. No other pins can be affected by a ‘‘Write
Port C’’ command, nor can the interrupt enable flags
be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to
16
MODE 2
IN
MODE 0
OR MODE 1
ONLY
I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA
change an interrupt enable flag, the ‘‘Set/Reset Port
C Bit’’ command must be used.
With a ‘‘Set/Reset Port C Bit’’ command, any Port C
line programmed as an output (including INTR, IBF
and OBF) can be written, or an interrupt enable flag
can be either set or reset. Port C lines programmed
as inputs, including ACK and STB lines, associated
with Port C are not affected by a ‘‘Set/Reset Port C
Bit’’ command. Writing to the corresponding Port C
bit positions of the ACK and STB lines with the
‘‘Set/Reset Port C Bit’’ command will affect the
Group A and Group B interrupt enable flags, as illustrated in Figure 18.
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5
mA. This feature allows the 82C55A to directly drive
Darlington type drivers and high-voltage displays
that require such sink or source current.
82C55A
INPUT CONFIGURATION
D5
D4
D3
D2
D1
Reading Port C Status
D6
D7
In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to
function in Modes 1 or 2, Port C generates or accepts ‘‘hand-shaking’’ signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the ‘‘status’’ of each peripheral device and change the program flow accordingly.
There is no special instruction to read the status information from Port C. A normal read operation of
Port C is executed to perform this function.
D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
GROUP A
D7
D6
GROUP B
OUTPUT CONFIGURATIONS
D5 D4
D3
D2
D1
D0
OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
GROUP A
GROUP B
Figure 17a. MODE 1 Status Word Format
D7
D6
D5
D4
D3
D2
D1
D0
OBFA INTE1 IBFA INTE2 INTRA
GROUP A
GROUP B
(Defined By Mode 0 or Mode 1 Selection)
Figure 17b. MODE 2 Status Word Format
Interrupt Enable Flag
INTE B
INTE A2
INTE A1
Position
Alternate Port C Pin Signal (Mode)
PC2
PC4
PC6
ACKB (Output Mode 1) or STBB (Input Mode 1)
STBA (Input Mode 1 or Mode 2)
ACKA (Output Mode 1 or Mode 2
Figure 18. Interrupt Enable Flags in Modes 1 and 2
17
82C55A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under BiasÀÀÀÀ0§ C to a 70§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Supply Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5 to a 8.0V
Operating Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ a 4V to a 7V
Voltage on any InputÀÀÀÀÀÀÀÀÀÀGND b 2V to a 6.5V
Voltage on any Output ÀÀGND b 0.5V to VCC a 0.5V
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1 Watt
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
D.C. CHARACTERISTICS
TA e 0§ C to 70§ C, VCC e a 5V g 10%, GND e 0V (TA e b 40§ C to a 85§ C for Extended Temperture)
Min
Max
Units
VIL
Symbol
Input Low Voltage
Parameter
b 0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
V
VOL
Output Low Voltage
0.4
V
IOL e 2.5 mA
VOH
Output High Voltage
V
V
IOH e b 2.5 mA
IOH e b 100 mA
IIL
Input Leakage Current
g1
mA
VIN e VCC to 0V
(Note 1)
IOFL
Output Float Leakage Current
g 10
mA
VIN e VCC to 0V
(Note 2)
IDAR
Darlington Drive Current
g 2.5
(Note 4)
mA
Ports A, B, C
Rext e 500X
Vext e 1.7V
IPHL
Port Hold Low Leakage Current
a 50
a 300
mA
VOUT e 1.0V
Port A only
IPHH
Port Hold High Leakage Current
b 50
b 300
mA
VOUT e 3.0V
Ports A, B, C
IPHLO
Port Hold Low Overdrive Current
b 350
mA
VOUT e 0.8V
IPHHO
Port Hold High Overdrive Current
a 350
mA
VOUT e 3.0V
ICC
VCC Supply Current
10
mA
(Note 3)
ICCSB
VCC Supply Current-Standby
10
mA
VCC e 5.5V
VIN e VCC or GND
Port Conditions
If I/P e Open/High
O/P e Open Only
With Data Bus e
High/Low
CS e High
Reset e Low
Pure Inputs e
Low/High
NOTES:
1. Pins A1, A0, CS, WR, RD, Reset.
2. Data Bus; Ports B, C.
3. Outputs open.
4. Limit output current to 4.0 mA.
18
3.0
VCC b 0.4
Test Conditions
82C55A
CAPACITANCE
TA e 25§ C, VCC e GND e 0V
Symbol
Parameter
Min
Max
Units
Test Conditions
Unmeasured plns
returned to GND
fc e 1 MHz(5)
CIN
Input Capacitance
10
pF
CI/O
I/O Capacitance
20
pF
NOTE:
5. Sampled not 100% tested.
A.C. CHARACTERISTICS
TA e 0§ to 70§ C, VCC e a 5V g 10%, GND e 0V
TA e b 40§ C to a 85§ C for Extended Temperature
BUS PARAMETERS
READ CYCLE
Symbol
82C55A-2
Parameter
Min
tRA
v
Address Hold Time After RDu
tRR
RD Pulse Width
tRD
Data Delay from RD
tDF
RD
tRV
Recovery Time between RD/WR
tAR
Address Stable Before RD
v
u to Data Floating
Units
Max
0
ns
0
ns
150
ns
10
Test
Conditions
120
ns
75
ns
200
ns
WRITE CYCLE
Symbol
82C55A-2
Parameter
Min
v
u
Units
Max
Test
Conditions
tAW
Address Stable Before WR
0
ns
tWA
Address Hold Time After WR
20
ns
Ports A & B
20
ns
Port C
tWW
WR Pulse Width
100
ns
tDW
Data Setup Time Before WR
100
ns
tWD
Data Hold Time After WR
30
ns
Ports A & B
30
ns
Port C
u
u
19
82C55A
OTHER TIMINGS
Symbol
82C55A-2
Parameter
Min
Max
350
Units
Conditions
tWB
WR e 1 to Output
tlR
Peripheral Data Before RD
0
ns
tHR
Peripheral Data After RD
0
ns
tAK
ACK Pulse Width
200
ns
tST
STB Pulse Width
100
ns
tPS
Per. Data Before STB High
20
ns
tPH
Per. Data After STB High
50
ns
tAD
ACK e 0 to Output
tKD
ACK e 1 to Output Float
tWOB
WR e 1 to OBF e 0
tAOB
ACK e 0 to OBF e 1
150
ns
tSIB
STB e 0 to IBF e 1
150
ns
tRIB
RD e 1 to IBF e 0
150
ns
tRIT
RD e 0 to INTR e 0
200
ns
tSIT
STB e 1 to INTR e 1
150
ns
tAIT
ACK e 1 to INTR e 1
150
ns
tWIT
WR e 0 to INTR e 0
tRES
Reset Pulse Width
20
ns
175
ns
250
ns
150
ns
200
500
Test
ns
see note 1
ns
see note 2
NOTE:
1. INTRu may occur as early as WRv.
2. Pulse width of initial Reset pulse after power on must be at least 50 mSec. Subsequent Reset pulses may be 500 ns
minimum. The output Ports A, B, or C may glitch low during the reset pulse but all port pins will be held at a logic ‘‘one’’ level
after the reset pulse.
20
82C55A
WAVEFORMS
MODE 0 (BASIC INPUT)
231256 – 22
MODE 0 (BASIC OUTPUT)
231256 – 23
21
82C55A
WAVEFORMS (Continued)
MODE 1 (STROBED INPUT)
231256 – 24
MODE 1 (STROBED OUTPUT)
231256 – 25
22
82C55A
WAVEFORMS (Continued)
MODE 2 (BIDIRECTIONAL)
231256 – 26
Note:
Any sequence where WR occurs before ACK AND STB occurs before RD is permissible.
(INTR e IBF # MASK # STB # RD a OBF # MASK # ACK # WR)
WRITE TIMING
READ TIMING
231256 – 28
231256 – 27
A.C. TESTING INPUT, OUTPUT WAVEFORM
231256 – 29
A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V
For A Logic 0 Timing Measurements Are Made At 2.0V For A
Logic 1 And 0.8 For A Logic 0.
A.C. TESTING LOAD CIRCUIT
231256 – 30
*VEXT Is Set At Various Voltages During Testing To Guarantee
The Specification. CL Includes Jig Capacitance.
23