ISL6336, ISL6336A ® Data Sheet March 3, 2008 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring The ISL6336, ISL6336A controls microprocessor core voltage regulation by driving up to 6 interleaved synchronous-rectified buck channels in parallel. Multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. Lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. Microprocessor loads can generate load transients with extremely fast edge rates and require high efficiency over the full load range. The ISL6336, ISL6336A utilizes Intersil’s proprietary Active Pulse Positioning (APP) and Adaptive Phase Alignment (APA) modulation scheme and a proprietary active phase dropping/adding and diode emulation scheme to achieve extremely fast transient response with fewer output capacitors and high efficiency from light load to full load. The ISL6336, ISL6336A is compliant with Intel’s VR11.1 specification. Features include a pin (IMON) for current monitoring and a Power State Indicator (PSI#) input pin to initiate a proprietary phase dropping and diode emulation scheme for higher efficiency at light load by dropping to 1- or 2-phase operation with optional diode emulation (ISL6336) to reduce switching and core losses in the converter. After the PSI# signal is de-asserted, the dropped phase(s) are added back to sustain heavy load transient and efficiency. Today’s microprocessors require a tightly regulated output voltage position versus load current (droop). The ISL6336, ISL6336A senses the output current continuously by utilizing patented techniques to measure the voltage across a dedicated current sense resistor or the DCR of the output inductor. Current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. A programmable integrated temperature compensation function is implemented to effectively compensate the temperature variation of the current sense element. A current limit function provides overcurrent protection for the individual phase. FN6504.0 Features • Intel VR11.1 Compliant • Proprietary Active Pulse Positioning and Pin Adaptive Phase Alignment Modulation Scheme • Proprietary Active Phase Adding and Dropping with Diode Emulation for High Efficiency at Light Load • Precision Multiphase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy Over Life, Load, Line and Temperature - Bi-directional Adjustable Reference-Voltage Offset • Precision Resistor or DCR Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Accurate Current Monitoring Output Pin (IMON) • Microprocessor Voltage Identification Input - Dynamic VID™ Technology - 8-Bit VID Input With VR11 Code • Thermal Monitor and OV Protection with OVP Output • Average Overcurrent Protection and Channel Current Limit • Precision Overcurrent Protection on IMON pin • Integrated Open Sense Line Protection • Integrated Programmable Temperature Compensation • 1- to 6-Phase Operation; Coupled Inductor Compatible • Adjustable Switching Frequency up to 1MHz Per Phase • Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline • Pb-Free (RoHS Compliant) A unity gain, differential amplifier is provided for remote voltage sensing and eliminates any potential difference between remote and local grounds. This improves regulation and protection accuracy. The threshold-sensitive enable input is available to accurately coordinate the start up of the ISL6336, ISL6336A with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6336, ISL6336A Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL6336CRZ* ISL6336 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7 ISL6336IRZ* ISL6336 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL6336ACRZ* ISL6336A CRZ 0 to+70 48 Ld 7x7 QFN L48.7x7 ISL6336AIRZ * ISL6336A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 *Add “-T” for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout TM VR_HOT VR_FAN VR_RDY OVP SS FS EN_VTT EN_PWR ISEN6+ ISEN6- PWM6 ISL6336, ISL6336A (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VID7 1 36 PWM3 VID6 2 35 ISEN3- VID5 3 34 ISEN3+ VID4 4 33 ISEN1+ VID3 5 32 ISEN1- VID2 6 31 PWM1 GND 2 13 14 15 16 17 18 19 20 21 22 23 24 PWM5 25 PWM2 ISEN5- 26 ISEN2- DAC 12 ISEN5+ IMON 11 VCC 27 ISEN2+ VSEN OFS 10 TCOMP 28 ISEN4+ RGND 29 ISEN4- 9 VDIFF 8 PSI# FB VID0 COMP 30 PWM4 REF 7 APA VID1 FN6504.0 March 3, 2008 ISL6336, ISL6336A Controller and Driver Recommendations CONTROLLER COMMENTS ISL6336 When PSI# is asserted (LOW), the controller generates a 3-level PWM pattern on the phases that are active in PSI# mode. The active phases in PSI# mode must use VR11.1 drivers, ISL6622, ISL6620 for diode emulation. ISL6336A When PSI# is asserted (LOW), the PWM pattern has only high and low states except for fault modes. The controller can be used with any Intersil driver such as ISL6612, ISL6614, ISL6609, ISL6610. ISL6622, ISL6620 can also be used. DRIVER GATE DRIVE VOLTAGE # OF GATE DRIVES DIODE EMULATION (DE) GATE DRIVE OPTIMIZATIO N (GVOT) COMMENTS ISL6622 12V Dual Output (Single Phase) Yes Yes Use for phases that are active in PSI# mode and its coupled channel in coupled inductor applications. Can also be used on all channels. ISL6620 5V Dual Output (Single Phase) Yes No Use for phases that are active in PSI# mode and its coupled channel in coupled inductor applications. Can also be used on all channels. ISL6612, ISL6612A 12V Dual Output (Single Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6596 5V Dual Output (Single Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6614, ISL6614A 12V Quad Output (Two Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A ISL6610 5V Quad Output (Two Phase) No No Can be used with phases that are inactive in PSI# mode or with all channels when using the ISL6336A NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous channels. 3 FN6504.0 March 3, 2008 ISL6336, ISL6336A ISL6336, ISL6336A Block Diagram VDIFF VR_RDY OVP PSI# APA VCC 0.875V RGND POWER-ON x1 VSEN S OVP DRIVE EN_VTT RESET (POR) R 0.875V Q EN_PWR OVP TRI-STATE SOFT-START AND FAULT LOGIC +175mV CLOCK, RAMP GENERATOR, APA CONTROL SS OFS OFFSET FS APP AND APA MODULATOR PWM1 APP AND APA MODULATOR PWM2 APP AND APA MODULATOR PWM3 APP AND APA MODULATOR PWM4 APP AND APA MODULATOR PWM5 APP AND APA MODULATOR PWM6 REF DAC VID7 VID6 VID5 DYNAMIC VID DAC VID4 VID3 VID2 E/A VID1 VID0 CHANNEL CURRENT BALANCE AND CURRENT LIMIT COMP CHANNEL DETECT ISEN1+ FB ISEN1I_TRIP 1.12V OC2 OC1 1 N ISEN2+ ∑ TEMPERATURE COMPENSATION IMON 1.12V CHANNEL ISEN2- CURRENT ISEN3+ SENSE ISEN3ISEN4+ I_TOT ISEN4ISEN5+ THERMAL MONITORING TEMPERATURE COMPENSATION GAIN ISEN5ISEN6+ ISEN6- GND 4 TM VR_FAN VR_HOT TCOMP FN6504.0 March 3, 2008 ISL6336, ISL6336A Typical Application - 5-Phase Buck Converter with DCR Sensing and Integrated TCOMP +5V ISL6620 VCC BOOT UGATE EN PHASE PWM +5V GND LGATE +5V ISL6596 FB COMP APA REF BOOT UGATE EN PHASE GND VSEN GND EN_VTT LGATE +5V ISL6596 VR_RDY ISL6336 VID7 VCC BOOT UGATE EN PHASE PWM1 VID6 ISEN1ISEN1+ VID5 VID4 VID3 VID2 PWM4 ISEN4ISEN4+ VID1 VID0 PSI# OVP PWM GND PWM2 ISEN2ISEN2+ ISL6596 VCC BOOT UGATE EN PHASE ISEN5ISEN5+ VR_FAN PWM3 ISEN3- PWM ISEN3+ GND PWM6 ISEN6ISEN6+ VR_HOT EN_PWR TCOMP OFS FS +5V +5V R OFS RT ISL6596 VCC BOOT UGATE EN PHASE SS VIN µP LOAD LGATE +5V +5V VIN LGATE +5V PWM5 IMON TM VIN VCC RGND VTT VCC PWM DAC VDIFF VIN VIN R SS VIN PWM GND LGATE NTC 5 FN6504.0 March 3, 2008 ISL6336, ISL6336A Typical Application - 4-Phase Buck Converter with coupled inductors +5V ISL6620 VCC BOOT UGATE EN PHASE PWM +5V GND +5V FB COMP APA REF VDIFF VSEN EN PHASE LGATE GND EN_VTT VR_RDY BOOT UGATE VIN VCC RGND VTT VCC GND DAC LGATE ISL6620 PWM VIN ISL6336 VID7 PWM1 VID6 ISEN1ISEN1+ VID5 VID4 VID3 VID2 +5V ISL6596 PWM3 ISEN3ISEN3+ VID1 VID0 PSI# OVP PWM2 ISEN2ISEN2+ ISEN4- +5V PWM5 ISEN5ISEN5+ PWM6 ISEN6ISEN6+ VR_HOT TM PHASE +5V LGATE ISL6596 VCC BOOT UGATE EN PHASE PWM GND µP LOAD VIN LGATE EN_PWR TCOMP OFS FS +5V EN GND ISEN4+ VR_FAN BOOT UGATE PWM PWM4 IMON VCC VIN SS +5V R OFS RT R SS VIN NTC +5V +5V 6 FN6504.0 March 3, 2008 ISL6336, ISL6336A Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 48 Ld QFN Package. . . . . . . . . . . . . . . 29 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature ISL6336ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6336CRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6336AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C ISL6336IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS VCC SUPPLY CURRENT Nominal Supply VCC = 5VDC; EN_PWR = 5VDC; RT = 100kΩ, ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 80µA - 16 20 mA Shutdown Supply VCC = 5VDC; EN_PWR = 0VDC; RT = 100kΩ - 14 17 mA VCC Rising 4.3 4.4 4.5 V VCC Falling 3.75 3.88 4.0 V Rising 0.875 0.897 0.920 V Falling 0.735 0.752 0.770 V Rising 0.875 0.897 0.920 V Falling 0.735 0.752 0.770 V POWER-ON RESET AND ENABLE POR Threshold EN_PWR Threshold EN_VTT Threshold REFERENCE VOLTAGE AND DAC System Accuracy of ISL6336ACRZ, ISL6336CRZ (VID = 1V to 1.6V), TJ = 0°C to +70°C (Note 3) -0.5 - 0.5 %VID System Accuracy of ISL6336ACRZ, ISL6336CRZ (VID = 0.5V to 1V), TJ = 0°C to +70°C (Note 3) -5 - 5 mV System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 1V to1.6V), TJ = -40°C to +85°C (Note 3) -0.6 - 0.6 %VID System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 0.8V to 1V), TJ = -40°C to +85°C (Note 3) -0.7 - 0.7 %VID System Accuracy of ISL6336AIRZ, ISL6336IRZ (VID = 0.5V to 0.8V), TJ = -40°C to +85°C (Note 3) -1 - 1 %VID VID Pull-up After tD3 (see “Soft-Start” on page 19) 30 40 50 µA VID Input Low Level - - 0.4 V VID Input High Level 0.8 - - V Maximum DAC Source Current 3.5 - - mA Maximum DAC Sink Current 100 - - µA 50 - - µA Maximum REF Source/Sink Current (Note 4) PIN-ADJUSTABLE OFFSET 7 FN6504.0 March 3, 2008 ISL6336, ISL6336A Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS Voltage at OFS Pin Offset resistor connected to ground Voltage below VCC, offset resistor connected to VCC MIN (Note 7) TYP MAX (Note 7) UNITS 390 400 415 mV 1.574 1.60 1.635 V OSCILLATORS Accuracy of Switching Frequency Setting RT = 100kΩ 225 250 275 kHz Adjustment Range of Switching Frequency (Note 4) 0.08 - 1.0 MHz Soft-Start Ramp Rate RSS = 100kΩ (Notes 4, 5 , 6) - 1.563 - mV/µs Adjustment Range of Soft-Start Ramp Rate (Note 4) 0.625 - 6.25 mV/µs (Note 4) - 1.5 - V Open-Loop Gain RL = 10kΩ to ground (Note 4) - 96 - dB Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground (Note 4) - 80 - MHz Slew Rate CL = 100pF (Note 4) - 25 - V/µs Maximum Output Voltage 3.8 4.4 4.9 V Output High Voltage @ 2mA 3.6 - - V Output Low Voltage @ 2mA - - 1.6 V - 20 - MHz PWM GENERATOR Sawtooth Amplitude ERROR AMPLIFIER REMOTE-SENSE AMPLIFIER Bandwidth (Note 4) Output High Current VSEN - RGND = 2.5V -500 - 500 µA Output High Current VSEN - RGND = 0.6V -500 - 500 µA - 50 - µA APA INPUT APA Sink Current PWM OUTPUT Sink Impedance PWM = LOW with 1mA load 100 220 300 Ω Source Impedance PWM = HIGH, forced to 3.7V 200 320 400 Ω Threshold HIGH - - 0.8 V Threshold LOW 0.4 - - V ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 40µA; Offset and Mirror Error Included, RISENx = 200Ω 36.5 - 42 µA ISEN1 = ISEN2 = ISEN3 = ISEN4 = ISEN5 = ISEN6 = 80µA; Offset and Mirror Error Included, RISENx = 200Ω 74 - 83 µA 96 105 117 µA - 135 - µA Peak Current Limit for Individual Channel 115 129 146 µA IMON Voltage Clamp and OCP Trip Level 1.085 1.11 1.14 V TM Input Voltage for VR_FAN Trip 38.7 39.1 39.6 %VCC TM Input Voltage for VR_FAN Reset 44.6 45.1 45.5 %VCC TM Input Voltage for VR_HOT Trip 32.9 33.3 33.7 %VCC PSI# INPUT CURRENT SENSE AND OVERCURRENT PROTECTION Sensed Current Tolerance Overcurrent Trip Level for Average Current (PSI# = 1) Offset and Mirror Error Included, RISENx = 200Ω Overcurrent Trip Level for Average Current (PSI# = 0) Number of Phases = 6, Drop to 1-Phase THERMAL MONITORING AND FAN CONTROL 8 FN6504.0 March 3, 2008 ISL6336, ISL6336A Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS TM Input Voltage for VR_HOT Reset MIN (Note 7) TYP MAX (Note 7) UNITS 38.7 39.1 39.6 %VCC Leakage Current of VR_FAN With external pull-up resistor connected to VCC - - 5 µA VR_FAN Low Voltage With 1.24kΩ resistor pull-up to VCC, IVR_FAN = 4mA - - 0.3 V Leakage Current of VR_HOT With external pull-up resistor connected to VCC - - 5 µA VR_HOT Low Voltage With 1.24kΩ resistor pull-up to VCC, IVR_HOT = 4mA - - 0.3 V Leakage Current of VR_RDY With external pull-up resistor connected to VCC - - 5 µA VR_RDY Low Voltage IVR_RDY = 4mA - - 0.3 V Undervoltage Threshold VDIFF Falling 48 50 52 %VID VR_RDY Reset Voltage VDIFF Rising 57 59.6 62 %VID Overvoltage Protection Threshold Before valid VID 1.250 1.273 1.300 V 138 170 195 mV - 100 - mV - 0.106 0.16 V VR READY AND PROTECTION MONITORS After valid VID, the voltage above VID Overvoltage Protection Reset Hysteresis OVP Output Low Voltage IOVP = 4mA NOTES: 3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 4. Limits should be considered typical and are not production tested. 5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input. 6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle. 7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 9 FN6504.0 March 3, 2008 ISL6336, ISL6336A Functional Pin Description VCC - Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply. Place a R/C filter right next to this pin for noise decoupling. The resistor and capacitor should be placed right next to the VCC pin to GND. GND - Bias and reference ground for the IC. The exposed metal pad on the bottom of the package of the ISL6336, ISL6336A is GND. EN_PWR - This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.875V, the ISL6336, ISL6336A is active depending on status of the EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime the ISL6336, ISL6336A to soft-start when re-enabled. EN_VTT - This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6336, ISL6336A is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the ISL6336, ISL6336A to soft-start when re-enabled. FS - Use this pin to set up the desired switching frequency. A resistor, placed from FS to GND or VCC will set the switching frequency. The relationship between the value of the resistor and the switching frequency is shown in Equation 3. This pin is also used in combination with SS and PSI# to determine phase dropping operation. See Table 1. SS - Use this pin to set up the desired start-up oscillator frequency. A resistor, placed from SS to GND or VCC will set up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp up time is described in Equations 15 and 16. This pin is also used with FS and PSI# pins to determine phase dropping operation. See Table 1. VID[7:0] - These are the inputs to the internal DAC that generates the reference voltage for output regulation. The pins have a minimum 30µA pull-up to about 1V after tD3. There is no internal pull-up before tD3. Connect these pins to open-drain outputs with external pull-up resistors or to active pull-up outputs. The VID pins can be pulled as high as VCC plus 0.3V. VDIFF, VSEN, and RGND - VSEN and RGND form the precision differential remote-sense amplifier. This amplifier converts the differential voltage of the remote output to a singleended voltage referenced to local ground. VDIFF is the 10 amplifier’s output and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote load. VDIFF is connected to FB through a resistor. FB and COMP - The inverting input and the output of the error amplifier respectively. FB can be connected to VDIFF through a resistor. A properly chosen resistor between VDIFF and FB can set the load line (droop). The droop scale factor is set by the ratio of the ISEN resistors and the inductor DCR or the dedicated current sense resistor. COMP is tied back to FB through an external R-C network to compensate the regulator. DAC and REF - The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error Amplifier. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™ operations. PWM[6:1] - Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3, PWM4, PWM5, and PWM6. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. Tie PWM5 to VCC to configure for 4-phase operation. Tie PWM6 to VCC to configure for 5-phase operation. PWM firing order is sequential from 1 to n with n being the number of active phases. ISEN[6:1]+, ISEN[6:1]- - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs left open (for example, open ISEN6+ and ISEN6- for 5-phase operation). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sense current is proportional to the inductor current, and scaled by the DCR of the inductor and RISEN. To match the time delay of the internal circuit, a capacitor is needed between each ISEN+ pin and GND as described in “Current Sensing” on page 13. VR_RDY - VR_RDY indicates that the soft-start is completed and the output voltage is within the regulated range around VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also be pulled low if the output voltage is below the undervoltage threshold. FN6504.0 March 3, 2008 ISL6336, ISL6336A OFS - The OFS pin provides a means to program a DC offset current for generating a DC offset voltage at the REF input. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unterminated. TCOMP - Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to adjust IDROOP and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation. When integrated temperature compensation function is not used, connect TCOMP to GND. OVP - The overvoltage protection output indication pin. This pin can be pulled to VCC and is latched when an overvoltage condition is detected. When the OVP indication is not used, keep this pin open. IMON - IMON is a current output of the average of the sum of each phase’s sensed current. A resistor connected from IMON to GND will produce a voltage that is proportional to the regulator current. The voltage at this pin is internally clamped to 1.12V. If the voltage reaches 1.12V the clamp is activated an overcurrent shutdown will be initiated. Place a resistor from this pin to GND. A capacitor in parallel with this resistor is required. The capacitor should be sized for a minimum time constant of 300µs. TM - TM is an input pin for VR temperature measurement. Connect this pin through NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. ISL6336, ISL6336A monitors the VR temperature based on the voltage at the TM pin and the output signals at VR_HOT and VR_FAN. VR_HOT - VR_HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be open when the measured VR temperature reaches a certain level. VR_FAN - VR_FAN is an output pin with open-drain logic output. It will be open when the measured VR temperature reaches a certain level. PSI# - The PSI# pin is used to change the state of the controller. When PSI# is asserted the controller will change the operating state to improve light load efficiency. The controller drops the number of active phases to 1-phase or 2-phase operation with diode emulation according to the logic shown in Table 1. The FS and SS pins are used to optimize light load efficiency for non-coupled inductor, 2-phase coupled inductor, and (n-x)-phase coupled inductor applications. The 11 controller resumes normal operation when this pin is pulled HIGH. This pin has a 40µA internal pull-up to about 1V. APA - The APA pin is used to adjust the Adaptive Phase Alignment trip level. A 50µA current source flows into this pin. A resistor connected from this pin to COMP sets the voltage trip level. A small decoupling capacitor should be placed in parallel with the resistor for high frequency decoupling. Operation Multiphase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable, have forced a change to the cost-saving approach of multiphase. The ISL6336, ISL6336A controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on page 5 and 6 provide top level views of multiphase power conversion using the ISL6336, ISL6336A controller. Interleaving The switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter for example, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-to-peak amplitude of the combined inductor current is reduced in proportion to the number of phases (see Equations 1 and 2). The increased ripple frequency and the lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is triggered 1/3 of a cycle after the start of the PWM pulse of the previous phase. The DC components of the inductor currents combine to feed the load. To understand the reduction of the ripple current amplitude in the multiphase circuit, examine Equation 1, which represents an individual channel’s peak-to-peak inductor current. ( V IN – V OUT ) ⋅ V OUT I PP = --------------------------------------------------------L ⋅ fS ⋅ V (EQ. 1) IN In Equation 1, VIN and VOUT are the input and the output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency. FN6504.0 March 3, 2008 ISL6336, ISL6336A The converter depicted in Figure 2 delivers 36A to a 1.5V load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9ARMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter. IL1 + IL2 + IL3, 7A/DIV IL3, 7A/DIV PWM3, 5V/DIV IL2, 7A/DIV PWM2, 5V/DIV IL1, 7A/DIV PWM1, 5V/DIV 1µs/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER CHANNEL 3 INPUT CHANNEL 2 INPUT To further improve the transient response, the ISL6336, ISL6336A also implements Intersil's proprietary Adaptive Phase Alignment (APA) technique. The APA, with sufficiently large load step currents, can turn on all phases simultaneously. CHANNEL 1 INPUT 1µs/DIV FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER The output capacitors conduct the ripple component of the inductor current. In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output-voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. (EQ. 2) IN Another benefit of interleaving is to reduce the input ripple current. The input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve the overall system cost and size by lowering the input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates the input currents from a three-phase converter combining to reduce the total input ripple current. 12 PWM Modulation Scheme The ISL6336, ISL6336A adopts Intersil's proprietary Active Pulse Positioning (APP) modulation scheme to improve the transient performance. APP control is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to provide the best response to the transient loads. The PWM frequency, however, is constant and set by the external resistor between the FS pin and GND. INPUT-CAPACITOR CURRENT ( V IN – ( N ⋅ V OUT ) ) ⋅ V OUT I C, PP = -----------------------------------------------------------------------L ⋅ fS ⋅ V Figures 21, 22 and 23 in the section entitled “Input Capacitor Selection” on page 29 can be used to determine the input capacitor RMS current based on the load current, the duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. Figure 24 shows the single phase input-capacitor RMS current for comparison. With both APP and APA control, ISL6336, ISL6336A can achieve excellent transient performance and reduce the demand on the output capacitors. Under steady state conditions the operation of the ISL6336, ISL6336A PWM modulator appears to be that of a conventional trailing edge modulator. Conventional analysis and design methods can therefore be used for steady state and small signal operation. PWM and PSI# Operation The timing of each converter is set by the number of active channels. The default channel setting for the ISL6336, ISL6336A is six. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. The PWM signals command the MOSFET drivers to turn on/off the channel MOSFETs. In the default 6-phase operation, the PWM2 pulse happens 1/6 of a cycle after PWM1, the PWM3 pulse happens 1/6 of a cycle after PWM2, etc. The ISL6336, ISL6336A works in a 1- to 6-phase configuration. Connecting the PWM6 pin to VCC selects 5-phase operation and the pulse times are spaced in 1/5 cycle increments. FN6504.0 March 3, 2008 ISL6336, ISL6336A Connecting the PWM5 pin to VCC selects 4-phase operation and the pulse times are spaced in 1/4 cycle increments, etc. VR11.1 drivers (ISL6622/ISL6620) can decode and then enter diode emulation mode. When PSI# is pulled LOW, indicating low power operation of the processor, the controller reduces the number of active phases and operates 1- or 2-phases to improve efficiency based on the logic in Table 2. Table 1 shows which phases will be active when PSI# = 0 based on the phase count of the application. For example, If operating in a 6-phase configuration, phase 1 will be active if dropping to 1-phase and phases 1 and 4 will be active if dropping to 2-phases. The ISL6336A only generates the standard 2-level PWM signal except in FAULT conditions. The dedicated VR11.1 drivers do not need to be used with the ISL6336A. See “Controller and Driver Recommendations” on page 3 for more details. TABLE 1. NUMBER OF ACTIVE PHASES AND PWM FIRING SEQUENCE PHASE COUNT PHASE SEQUENCE NORMAL OPERATION PWM/VCC ACTIVE PHASES PSI# = 0 6-Phase 1-2-3-4-5-6 - Phase 1/4 5-Phase 1-2-3-4-5 PWM6 = VCC Phase 1/3 4-Phase 1 - 2 - 3- 4 PWM5:6 = VCC Phase 1/3 3-Phase 1-2-3 PWM4:6 = VCC Phase 1/2 2-Phase 1-2 PWM3:6 = VCC Phase 1/2 1-Phase 1 PWM2:6 = VCC - A high PSI# input signal will force the controller back into CCM normal operation and all phases will be activated to sustain a heavy load transient and to increase efficiency at higher loads. Switching Frequency The switching frequency is determined by the selection of the frequency-setting resistor, RT, which is connected from FS pin to GND or VCC (see “Typical Application - 5-Phase Buck Converter with DCR Sensing and Integrated TCOMP” on page 5 and “Typical Application - 4-Phase Buck Converter with coupled inductors” on page 6). Equation 3 is provided to assist in selecting the correct resistor value. 10 2.5X10 R T = -------------------------F SW TABLE 2. PHASE DROPPING BEHAVIOR FS SS PSI# RESISTOR RESISTOR CONFIGURATION During soft-start or overcurrent hiccup mode all phases will be operating despite the state of the PSI# pin. Once VR_RDY is asserted the state of the PSI# pin is considered. where FSW is the switching frequency of each phase. Equation 3 also applies for connecting FS to VCC or GND. Figure 3 shows the relationship between RT and FSW, according to Equation 3. Non-CI or (N - 1 ) - CI Drops to 1-Phase 0 GND GND Non-CI or (N - 2) - CI Drops to 2-Phase 0 GND VCC 2-Phase CI Drops to 1-Phase 0 VCC GND 2-Phase CI Drops to 2-Phase 0 VCC VCC 800 Normal 1 x x 700 When PSI# goes LOW, the dropped phase’s PWM signal is forced LOW for a minimum time and then is driven to 1/2*VCC while the remaining active phase PWM(s) sends out a repetitive 3-level PWM pattern that the dedicated 13 1000 900 FSW (kHz) The SS and FS pins are used to program the controllers PWM behavior in configurations using standard inductors, 2-phase coupled inductors or (N - 1)/(N - 2)-phase coupled inductors when PSI# goes LOW. 2-phase coupled inductors refer to inductor structures that magnetically couple 2-phases together. (N - 1) and (N - 2) coupled inductors refer to structures that couple all phases together except for the 1- or 2-phases that remain active in PSI# mode. N refers to the programmed number of active phases in normal operation, PSI# = 1 (Table 1). Each case yields different PWM output behavior on both the dropped phase(s) and active phases as PSI# is asserted and de-asserted. In Table 2, ‘VCC’ means that the resistor is connected from the respective pin to VCC and ‘GND’ means the resistor is connected from the respective pin to GND. (EQ. 3) 600 500 400 300 200 100 20 30 40 50 60 RT (kΩ) 70 80 90 100 FIGURE 3. SWITCHING FREQUENCY vs RT Current Sensing The ISL6336, ISL6336A senses current continuously for fast response. The ISL6336, ISL6336A supports inductor DCR sensing, or resistor sensing techniques. The associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. The sensed current, ISEN, is used for current balance, load-line regulation, and the overcurrent protection. The internal circuitry, shown in Figures 3 and 4, represents one channel of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be FN6504.0 March 3, 2008 ISL6336, ISL6336A active depending on the status of the PWM2, PWM3, PWM4, PWM5, PWM6 pins, “PWM and PSI# Operation” on page 12. The input bias current of the current sensing amplifier is typically 60nA; less than 5kΩ input impedance is preferred to minimize the offset error. INDUCTOR DCR SENSING An inductor’s winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 4. The channel current IL, flowing through the inductor, will also pass through the DCR. Equation 4 shows the s-domain equivalent voltage across the inductor VL. V L = I L ⋅ ( s ⋅ L + DCR ) (EQ. 4) A simple R-C network across the inductor extracts the DCR voltage, as shown in Figure 4. IL ( s ) VIN L ISL6609 DCR VOUT + VC(s) R - VL COUT - + INDUCTOR Because of the internal filter at the ISEN- pin, a capacitor, CT, is needed to match the time delay between the ISENand ISEN+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT) close to 27ns. Equation 6 shows that the ratio of the channel current to the sensed current ISEN is driven by the value of the sense resistor and the DCR of the inductor. DCR I SEN = I L ⋅ -----------------R ISEN (EQ. 6) RESISTIVE SENSING For accurate current sense, a dedicated current-sense resistor RSENSE in series with each output inductor can serve as the current sense element (see Figure 5). This technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element RSENSE. The same capacitor CT is needed to match the time delay between ISEN- and ISEN+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT) close to 27ns. Equation 7 shows the ratio of the channel current to the sensed current ISEN. C PWM(n) R SENSE I SEN = I L ⋅ ----------------------R ISEN ISL6336, ISL6336A INTERNAL CIRCUIT RISEN(n) (PTC) In With the internal low-offset current amplifier, the capacitor voltage VC is replicated across the sense resistor RISEN. Therefore the current out of ISEN+ pin, ISEN, is proportional to the inductor current. (EQ. 7) I L CURRENT L RSENSE VOUT COUT ISEN-(n) SENSE ISL6336, ISL6336A INTERNAL CIRCUIT + - ISEN+(n) RISEN(n) In CT DCR I SEN = I ----------------LR ISEN CURRENT SENSE ISEN-(n) + - FIGURE 4. DCR SENSING CONFIGURATION ISEN+(n) The voltage on the capacitor VC, can be shown to be proportional to the channel current IL; see Equation 5. L ⎛ s ⋅ ------------+ 1⎞ ⋅ ( DCR ⋅ I L ) ⎝ DCR ⎠ V C = --------------------------------------------------------------------( s ⋅ RC + 1 ) (EQ. 5) If the R-C network components are selected such that the RC time constant (= R*C) matches the inductor time constant (= L/DCR), the voltage across the capacitor VC is equal to the voltage drop across the DCR, i.e., proportional to the channel current. 14 I CT R SENSE SEN = I L ------------------------R ISEN FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS The inductor DCR value will increase as the temperature increases. Therefore the sensed current will increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the sensed current signal, a Positive Temperature Coefficient (PTC) resistor can be selected for the sense resistor RISEN, or the integrated FN6504.0 March 3, 2008 ISL6336, ISL6336A temperature compensation function of ISL6336, ISL6336A should be utilized instead. The integrated temperature compensation function is described in “External Temperature Compensation” on page 24. EXTERNAL CIRCUIT R C CC COMP ISL6336, ISL6336A INTERNAL CIRCUIT DAC Channel-Current Balance The sensed current In from each active channel are summed together and divided by the number of active channels. The resulting average current IAVG provides a measure of the total load current. Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method. RREF REF CREF + - FB RFB ERROR AMPLIFIER + VDROOP - IAVG VDIFF VSEN VOUT+ Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area. + - RGND VOUT- DIFFERENTIAL REMOTE-SENSE AMPLIFIER Voltage Regulation The compensation network shown in Figure 6 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6336, ISL6336A to include the combined tolerances of each of these elements. VCOMP FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT TABLE 3. VR11 VID 8-BIT VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 0 0 0 0 0 0 0 0 OFF 0 0 0 0 0 0 0 1 OFF 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 The ISL6336, ISL6336A incorporates an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the non-inverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, VDIFF, is connected to the inverting input of the error amplifier through an external resistor. 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 A digital-to-analog converter (DAC) generates a reference voltage based on the state of logic signals at pins VID7 through VID0. The DAC decodes the 8-bit logic signal (VID) into one of the discrete voltages shown in Table 3. Each VID input has an internal 30µA minimum pull-up to VCC after tD3. The pull-up current diminishes to zero above the logic threshold (near 1V) to protect voltage-sensitive output devices. External pull-up resistors can augment the pull-up current sources in case the leakage into the driving device is greater than 30µA. 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 The output of the error amplifier, VCOMP, is compared to the sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitries which control the voltage regulation are illustrated in Figure 6. 15 FN6504.0 March 3, 2008 ISL6336, ISL6336A TABLE 3. VR11 VID 8-BIT (Continued) TABLE 3. VR11 VID 8-BIT (Continued) VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 1.46875 0 0 1 1 1 1 1 1 1.21875 0 1.46250 0 1 0 0 0 0 0 0 1.21250 0 1 1.45625 0 1 0 0 0 0 0 1 1.20625 0 1 0 1.45000 0 1 0 0 0 0 1 0 1.20000 1 0 1 1 1.44375 0 1 0 0 0 0 1 1 1.19375 1 1 1 0 0 1.43750 0 1 0 0 0 1 0 0 1.18750 0 1 1 1 0 1 1.43125 0 1 0 0 0 1 0 1 1.18125 0 0 1 1 1 1 0 1.42500 0 1 0 0 0 1 1 0 1.17500 0 0 0 1 1 1 1 1 1.41875 0 1 0 0 0 1 1 1 1.16875 0 0 1 0 0 0 0 0 1.41250 0 1 0 0 1 0 0 0 1.16250 0 0 1 0 0 0 0 1 1.40625 0 1 0 0 1 0 0 1 1.15625 0 0 1 0 0 0 1 0 1.40000 0 1 0 0 1 0 1 0 1.15000 0 0 1 0 0 0 1 1 1.39375 0 1 0 0 1 0 1 1 1.14375 0 0 1 0 0 1 0 0 1.38750 0 1 0 0 1 1 0 0 1.13750 0 0 1 0 0 1 0 1 1.38125 0 1 0 0 1 1 0 1 1.13125 0 0 1 0 0 1 1 0 1.37500 0 1 0 0 1 1 1 0 1.12500 0 0 1 0 0 1 1 1 1.36875 0 1 0 0 1 1 1 1 1.11875 0 0 1 0 1 0 0 0 1.36250 0 1 0 1 0 0 0 0 1.11250 0 0 1 0 1 0 0 1 1.35625 0 1 0 1 0 0 0 1 1.10625 0 0 1 0 1 0 1 0 1.35000 0 1 0 1 0 0 1 0 1.10000 0 0 1 0 1 0 1 1 1.34375 0 1 0 1 0 0 1 1 1.09375 0 0 1 0 1 1 0 0 1.33750 0 1 0 1 0 1 0 0 1.08750 0 0 1 0 1 1 0 1 1.33125 0 1 0 1 0 1 0 1 1.08125 0 0 1 0 1 1 1 0 1.32500 0 1 0 1 0 1 1 0 1.07500 0 0 1 0 1 1 1 1 1.31875 0 1 0 1 0 1 1 1 1.06875 0 0 1 1 0 0 0 0 1.31250 0 1 0 1 1 0 0 0 1.06250 0 0 1 1 0 0 0 1 1.30625 0 1 0 1 1 0 0 1 1.05625 0 0 1 1 0 0 1 0 1.30000 0 1 0 1 1 0 1 0 1.05000 0 0 1 1 0 0 1 1 1.29375 0 1 0 1 1 0 1 1 1.04375 0 0 1 1 0 1 0 0 1.28750 0 1 0 1 1 1 0 0 1.03750 0 0 1 1 0 1 0 1 1.28125 0 1 0 1 1 1 0 1 1.03125 0 0 1 1 0 1 1 0 1.27500 0 1 0 1 1 1 1 0 1.02500 0 0 1 1 0 1 1 1 1.26875 0 1 0 1 1 1 1 1 1.01875 0 0 1 1 1 0 0 0 1.26250 0 1 1 0 0 0 0 0 1.01250 0 0 1 1 1 0 0 1 1.25625 0 1 1 0 0 0 0 1 1.00625 0 0 1 1 1 0 1 0 1.25000 0 1 1 0 0 0 1 0 1.00000 0 0 1 1 1 0 1 1 1.24375 0 1 1 0 0 0 1 1 0.99375 0 0 1 1 1 1 0 0 1.23750 0 1 1 0 0 1 0 0 0.98750 0 0 1 1 1 1 0 1 1.23125 0 1 1 0 0 1 0 1 0.98125 0 0 1 1 1 1 1 0 1.22500 0 1 1 0 0 1 1 0 0.97500 16 FN6504.0 March 3, 2008 ISL6336, ISL6336A TABLE 3. VR11 VID 8-BIT (Continued) TABLE 3. VR11 VID 8-BIT (Continued) VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 0.96875 1 0 0 0 1 1 1 1 0.71875 0 0.96250 1 0 0 1 0 0 0 0 0.71250 0 1 0.95625 1 0 0 1 0 0 0 1 0.70625 0 1 0 0.95000 1 0 0 1 0 0 1 0 0.70000 1 0 1 1 0.94375 1 0 0 1 0 0 1 1 0.69375 0 1 1 0 0 0.93750 1 0 0 1 0 1 0 0 0.68750 1 0 1 1 0 1 0.93125 1 0 0 1 0 1 0 1 0.68125 1 1 0 1 1 1 0 0.92500 1 0 0 1 0 1 1 0 0.67500 0 1 1 0 1 1 1 1 0.91875 1 0 0 1 0 1 1 1 0.66875 0 1 1 1 0 0 0 0 0.91250 1 0 0 1 1 0 0 0 0.66250 0 1 1 1 0 0 0 1 0.90625 1 0 0 1 1 0 0 1 0.65625 0 1 1 1 0 0 1 0 0.90000 1 0 0 1 1 0 1 0 0.65000 0 1 1 1 0 0 1 1 0.89375 1 0 0 1 1 0 1 1 0.64375 0 1 1 1 0 1 0 0 0.88750 1 0 0 1 1 1 0 0 0.63750 0 1 1 1 0 1 0 1 0.88125 1 0 0 1 1 1 0 1 0.63125 0 1 1 1 0 1 1 0 0.87500 1 0 0 1 1 1 1 0 0.62500 0 1 1 1 0 1 1 1 0.86875 1 0 0 1 1 1 1 1 0.61875 0 1 1 1 1 0 0 0 0.86250 1 0 1 0 0 0 0 0 0.61250 0 1 1 1 1 0 0 1 0.85625 1 0 1 0 0 0 0 1 0.60625 0 1 1 1 1 0 1 0 0.85000 1 0 1 0 0 0 1 0 0.60000 0 1 1 1 1 0 1 1 0.84375 1 0 1 0 0 0 1 1 0.59375 0 1 1 1 1 1 0 0 0.83750 1 0 1 0 0 1 0 0 0.58750 0 1 1 1 1 1 0 1 0.83125 1 0 1 0 0 1 0 1 0.58125 0 1 1 1 1 1 1 0 0.82500 1 0 1 0 0 1 1 0 0.57500 0 1 1 1 1 1 1 1 0.81875 1 0 1 0 0 1 1 1 0.56875 1 0 0 0 0 0 0 0 0.81250 1 0 1 0 1 0 0 0 0.56250 1 0 0 0 0 0 0 1 0.80625 1 0 1 0 1 0 0 1 0.55625 1 0 0 0 0 0 1 0 0.80000 1 0 1 0 1 0 1 0 0.55000 1 0 0 0 0 0 1 1 0.79375 1 0 1 0 1 0 1 1 0.54375 1 0 0 0 0 1 0 0 0.78750 1 0 1 0 1 1 0 0 0.53750 1 0 0 0 0 1 0 1 0.78125 1 0 1 0 1 1 0 1 0.53125 1 0 0 0 0 1 1 0 0.77500 1 0 1 0 1 1 1 0 0.52500 1 0 0 0 0 1 1 1 0.76875 1 0 1 0 1 1 1 1 0.51875 1 0 0 0 1 0 0 0 0.76250 1 0 1 1 0 0 0 0 0.51250 1 0 0 0 1 0 0 1 0.75625 1 0 1 1 0 0 0 1 0.50625 1 0 0 0 1 0 1 0 0.75000 1 0 1 1 0 0 1 0 0.50000 1 0 0 0 1 0 1 1 0.74375 1 1 1 1 1 1 1 0 OFF 1 0 0 0 1 1 0 0 0.73750 1 1 1 1 1 1 1 1 OFF 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500 17 FN6504.0 March 3, 2008 ISL6336, ISL6336A Load-Line Regulation Some microprocessor manufacturers require a precisely controlled output resistance. This dependence of the output voltage on the load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from the fast changes of the load-current demand. The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. OFS. If ROFS is connected to ground, the voltage across it is regulated to 0.4V, and IOFS flows out of OFS. A resistor between DAC and REF, RREF, is selected so that the product (IOFS x ROFS) is equal to the desired offset voltage. These functions are shown in Figure 7. Once the desired output offset voltage has been determined, use Equations 11 and 12 to set ROFS: For Positive Offset (connect ROFS to VCC): 1.6 ⋅ R REF R OFS = ---------------------------V OFFSET For Negative Offset (connect ROFS to GND): 0.4 ⋅ R REF R OFS = ---------------------------V OFFSET (EQ. 12) FB DYNAMIC VID D/A E/A REF CREF VCC OR GND (EQ. 8) The regulated output voltage is reduced by the droop voltage VDROOP. The output voltage as a function of load current is derived by combining Equation 8 with the appropriate sample current expression defined by the current sense method employed. RX ⎛ I OUT ⎞ V OUT = V REF – V OFS – ⎜ ------------- ⋅ ------------------ ⋅ R FB⎟ R ISEN ⎝ N ⎠ ROFS + + 0.4V VCC - OFS ISL6336, ISL6336A GND FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING Therefore the equivalent loadline impedance, i.e. Droop impedance, is equal to Equation 10: (EQ. 10) Output-Voltage Offset Programming The ISL6336, ISL6336A allows the designer to accurately adjust the offset voltage. When resistor, ROFS, is connected between OFS to VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (IOFS) to flow into 18 1.6V (EQ. 9) Where VREF is the reference voltage, VOFS is the programmed offset voltage, IOUT is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, and RFB is the feedback resistor, N is the active channel number, and RX is the DCR, or RSENSE depending on the sensing method. RX R FB R LL = ------------ ⋅ -----------------N R ISEN DAC RREF As shown in Figure 6, a current proportional to the average current of all active channels, IAVG, flows from FB through a load-line regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined in Equation 8. V DROOP = I AVG ⋅ R FB (EQ. 11) Dynamic VID Modern microprocessors need to make changes to their core voltage as part of the normal operation. They direct the core-voltage regulator to do this by making changes to the VID inputs during the regulator operation. The power management solution is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. In order to ensure a smooth transition of output voltage during VID change, a VID step change smoothing network, composed of RREF and CREF, can be used. The selection of RREF is based on the desired offset voltage as detailed above in “Output-Voltage Offset Programming” on page 18. FN6504.0 March 3, 2008 ISL6336, ISL6336A The selection of CREF is based on the time duration for 1-bit VID change and the allowable delay time. Assuming the microprocessor controls the VID change at 1-bit every tVID, the relationship between the time constant of RREF and CREF network and tVID is given by Equation 13. C REF ⋅ R REF = t VID (EQ. 13) ISL6336, ISL6336A INTERNAL CIRCUIT +12V VCC POR CIRCUIT ENABLE COMPARATOR + 100kΩ EN_PWR - During dynamic VID transition and VID up steps, the overcurrent trip point increases by 140% to avoid false triggering OCP circuits, while the overvoltage trip point is set to its maximum VID OVP trip level. If dynamic VID occurs when PSI# is asserted, the controller will activate all phases and complete the transition at which point the status of the PSI# pin will control operation. 9.1kΩ 0.875V + EN_VTT - Operation Initialization Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, VR_RDY asserts logic high. EXTERNAL CIRCUIT 0.875V SOFT-START AND FAULT LOGIC FIGURE 8. POWER SEQUENCING USING THRESHOLD SENSITIVE ENABLE (EN) FUNCTION Enable and Disable While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6336, ISL6336A is released from shutdown mode. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6336, ISL6336A is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6336, ISL6336A will not inadvertently turn off unless the bias voltage drops substantially (see “Electrical Specifications” table beginning on page 7). 2. The ISL6336, ISL6336A features an enable input (EN_PWR) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6336, ISL6336A in shutdown until the voltage at EN_PWR rises above 0.875V. The enable comparator has about 130mV of hysteresis to prevent bounce. It is important that the driver ICs reach their POR level before the ISL6336, ISL6336A becomes enabled. The schematic in Figure 8 demonstrates sequencing the ISL6336, ISL6336A with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. When all conditions above are satisfied, ISL6336, ISL6336A begins soft-start and ramps the output voltage to 1.1V first. After remaining at 1.1V for some time, ISL6336, ISL6336A reads the VID code at VID input pins. If the VID code is valid, ISL6336, ISL6336A will regulate the output to the final VID setting. If the VID code is an OFF code, ISL6336, ISL6336A will shut down, and cycling VCC, EN_PWR or EN_VTT is needed to restart. Soft-Start ISL6336, ISL6336A based VR has 4 periods during soft-start as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, The controller will have fixed delay period tD1. After this delay period, the VR will begin first soft-start ramp until the output voltage reaches 1.1V Vboot voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period tD3. At the end of tD3 period, ISL6336, ISL6336A reads the VID signals. If the VID code is valid, ISL6336, ISL6336A will initiate the second softstart ramp until the voltage reaches the VID voltage minus the offset voltage. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of the VTT voltage regulator. 19 FN6504.0 March 3, 2008 ISL6336, ISL6336A where VIMON is the voltage at the IMON pin, RIMON is the resistor between IMON and GND, IOUT is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number and RX is the DC resistance of the current sense element. VOUT, 500mV/DIV tD2 tD3 tD4 The resistor from the IMON pin to GND should be chosen to ensure that the voltage at the IMON pin is less than 1.12V under the maximum load current. The IMON pin voltage is clamped at a maximum of 1.12V. Once the 1.12V threshold is reached, an overcurrent shutdown will be initiated as described in “Overcurrent Protection” on page 21. tD5 EN_VTT VR_RDY 500µs/DIV FIGURE 9. SOFT-START WAVEFORMS The soft-start time is the sum of the 4 periods as shown in Equation 14: t SS = t D1 + t D2 + t D3 + t D4 A small capacitor can be placed between the IMON pin and GND to reduce noise. In addition, some applications will require the VIMON signal to be filtered with a minimum time constant. The filter capacitor can be chosen appropriately based on the RIMON value to set the desired time constant. (EQ. 14) tD1 is a fixed delay with a typical value as 1.36ms. tD3 is determined by a fixed 85µs plus the time to obtain valid VID voltage. If the VID is valid before the output reaches the 1.1V, the minimum time to validate the VID input is 500ns. Therefore the minimum tD3 is about 86µs. During tD2 and tD4, ISL6336, ISL6336A digitally controls the DAC voltage change at 6.25mV per step. The time for each step is determined by the frequency of the soft-start oscillator, which is defined by a resistor RSS from SS pin to GND or VCC. The equations are the same for the case where RSS is connected to GND or VCC. The two soft-start ramp times tD2 and tD4 can be calculated based on the Equations 15 and 16: 1.1 ⋅ R SS t D2 = ------------------------ ( μs ) 6.25 ⋅ 25 (EQ. 15) ( ( V VID – 1.1 ) ⋅ R SS ) t D4 = ------------------------------------------------------ ( μs ) 6.25 ⋅ 25 (EQ. 16) For example, when VID is set to 1.5V and the RSS is set at 100kΩ, the first soft-start ramp time tD2 will be 704µs and the second soft-start ramp time tD4 will be 256µs. After the DAC voltage reaches the final VID setting, VR_RDY will be set to high with the fixed delay tD5. The typical value for tD5 is 85µs. Before VR_RDY is released, the controller disregards the PSI# input and always operates in normal CCM PWM mode. Current Sense Output The current sourced at the IMON pin is equal to the sensed average current inside the ISL6336, ISL6336A, IAVG. In a typical application, a resistor is placed from the IMON pin to GND to generate a voltage which is proportional to the load current as shown in Equation 17: R IMON RX V IMON = ------------------- ⋅ ------------------ ⋅ I OUT N R ISEN 20 IMON VOLTAGE tD1 VIMON_OFS 0V 0A LOAD INCREASING FIGURE 10. IMON VOLTAGE vs OUTPUT CURRENT The voltage at the IMON pin will vary linearly with output current, as shown in Figure 10 with some tolerance. Some applications may require the addition of a positive offset on IMON to offset for the tolerance at the maximum IMON voltage value. This can be done by connecting a resistor from the IMON pin to VCC as shown in Figure 11. The required value for RVCC can be determined by using Equation 18: R IMON ⋅ ( VCC – V IMONOFS – V IMONMAX ) R VCC = --------------------------------------------------------------------------------------------------------------------V IMONOFS (EQ. 18) where RIMON is the resistor from IMON to GND, VIMONOFS is the desired offset voltage at VIMONMAX, and VIMONMAX is the voltage at IMON at the maximum load current. For example, if the maximum IMON voltage is 900mV at full load and the required offset voltage is 50mV and RIMON is 10kΩ then RVCC should be 810kΩ. RIMON should be connected to GND near the load to increase accuracy. (EQ. 17) FN6504.0 March 3, 2008 ISL6336, ISL6336A Undervoltage Detection EXTERNAL CIRCUIT The undervoltage threshold is set at 50% of the VID voltage. When the output voltage at VSEN is below the undervoltage threshold, VR_RDY gets pulled low. When the output voltage comes back to 60% of the VID voltage, VR_RDY will return back to high. ISL6336, ISL6336A INTERNAL CIRCUIT VCC IAVG RVCC IMON RIMON CIMON Overvoltage Protection Regardless of the VR being enabled or not, the ISL6336, ISL6336A overvoltage protection (OVP) circuit will be active after its POR. The OVP thresholds are different under different operation conditions. When VR is not enabled and before the 2nd soft-start, the OVP threshold is 1.275V. Once the controller detects a valid VID input, the OVP trip point will be changed to the VID voltage plus 175mV. + VIMON - NEAR LOAD GND FIGURE 11. IMON RESISTOR DIVIDER Fault Monitoring and Protection The ISL6336, ISL6336A actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 12 outlines the interaction between the fault monitors and the VR_RDY signal. VR_RDY - + UV 50% DAC 105µA OC + - + VDIFF - SOFT-START, FAULT AND CONTROL LOGIC IAVG 1.11V OC OV + - IMON VID + 0.175V FIGURE 12. VR_RDY AND PROTECTION CIRCUITRY VR_RDY Signal The VR_RDY pin is an open-drain logic output to indicate that the soft-start period is completed and the output voltage is within the regulated range. VR_RDY is pulled low during shutdown and releases high after a successful soft-start and a fixed delay time, tD5 (see Figure 9). VR_RDY will be pulled low when an undervoltage, overvoltage, or overcurrent condition is detected, or if the controller is disabled by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code. 21 Two actions are taken by the ISL6336, ISL6336A to protect the microprocessor load when an overvoltage condition occurs. At the inception of an overvoltage event, all PWM outputs are commanded low instantly (in less than 20ns). This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage down to avoid damaging the load. When the voltage at VDIFF falls below the DAC plus 75mV, PWM signals enter a high-impedance state. The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the overvoltage condition reoccurs, the ISL6336, ISL6336A will again command the lower MOSFETs to turn on. The ISL6336, ISL6336A will continue to protect the load in this fashion as long as the overvoltage condition occurs. Once an overvoltage condition is detected, normal PWM operation ceases until the ISL6336, ISL6336A is reset. Cycling the voltage on EN_PWR, EN_VTT or VCC below the POR-falling threshold will reset the controller. Cycling the VID codes will not reset the controller. Overcurrent Protection ISL6336, ISL6336A has two levels of overcurrent protection. Each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis. In instantaneous protection mode, the ISL6336, ISL6336A utilizes the sensed average current IAVG to detect an overcurrent condition. See “Channel-Current Balance” on page 15 for more detail on how the average current is measured. The average current is continually compared with a constant 105µA reference current, as shown in Figure 12. Once the average current exceeds the reference current, a comparator trips and causes the converter to shutdown. The voltage at the IMON pin is used for average current protection (compared to the instantaneous current protection described above). The current out of the IMON pin is equal to the sensed average current, IAVG. With a resistor from IMON to GND, the voltage at IMON will be proportional to the FN6504.0 March 3, 2008 ISL6336, ISL6336A sensed average current and the resistor value. The ISL6336, ISL6336A continually monitors the voltage at the IMON pin. If the voltage at the IMON pin is higher than 1.11V, a comparator trips and causes the converter to shutdown. The voltage at the IMON pin may be delayed relative to the sensed current, IAVG, due to the capacitor that is in parallel with the IMON resistor to GND that is required in some applications. This time constant can be >300µs. This lag can cause the output voltage to remain high for a longer time period before the OC comparator is tripped. This can lead to higher duty cycles of the output voltage during overcurrent hiccup mode. To avoid this the external current sense resistors should be selected so that the instantaneous overcurrent trip occurs at about the same sense current level as the IMON trip. For example, the IMON resistor to GND should be selected such that the voltage at IMON reaches 1.12V when IAVG reaches ~100µA. Another option is to remove the capacitor that is in parallel with the IMON resistor and add the required filter to the output of a IMON buffer. At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state for 4096 switching cycles (programmed switching frequency). If the controller is still enabled at the end of this wait period, it will attempt a soft-start. If the fault remains, the trip-retry cycles will continue indefinitely (as shown in Figure 13) until either controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during fullload operation, so there is no thermal hazard during this kind of operation. OUTPUT CURRENT 0A OUTPUT VOLTAGE 0V 2ms/DIV FIGURE 13. OVERCURRENT BEHAVIOR IN HICCUP MODE, FSW = 500kHz For the individual channel overcurrent protection, the ISL6336, ISL6336A continuously compares the sensed current signal of each channel with the 129µA reference current. If one channel current exceeds the reference current, ISL6336, ISL6336A will pull the PWM signal of this channel low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 129µA reference current. The peak 22 current limit of individual channel will not trigger the converter to shutdown. The overcurrent protection level for the above three OCP modes can be adjusted by changing the value of current sensing resistors. In addition, ISL6336, ISL6336A can also adjust the average OCP threshold level by adjusting the value of the resistor from IMON to GND. This provides additional safety for the voltage regulator. Equation 19 can be used to calculate the value of the resistor RIMON based on the desired OCP level IAVG, OCP2. 1.11V R IOUT = ------------------------------I AVG, OCP2 (EQ. 19) Thermal Monitoring (VR_HOT/VR_FAN) There are two thermal signals to indicate the temperature status of the voltage regulator: VR_HOT and VR_FAN. Both VR_FAN and VR_HOT are open-drain outputs, and external pull-up resistors are required. The VR_HOT/VR_FAN signals are valid only after the controller is enabled. VR_FAN signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. VR_HOT signal can be used to inform the system that the temperature of the voltage regulator is too high and the CPU should reduce its power consumption. VR_HOT signal may be tied to the CPU’s PROCHOT# signal. The diagram of the thermal monitoring function block is shown in Figure 14. One NTC resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for TM pin. The NTC thermistor should be placed next to the current sense element of a phase that will remain active when PSI# is asserted low. As the temperature of the power stage increases, the resistance of the NTC will reduce, resulting in the reduced voltage at the TM pin. Figure 15 shows the TM voltage over temperature for a typical design with a recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801 from Vishay) and 1kΩ resistor RTM1. We recommend using these resistors for accurate temperature compensation. There are two comparators with hysteresis to compare the TM pin voltage to the fixed thresholds for VR_FAN and VR_HOT signals respectively. VR_FAN signal is set high when the TM voltage is lower than 39.1% of VCC voltage, and is pulled to GND when the TM voltage increases to above 45.1% of VCC. VR_HOT is set to high when the TM voltage goes below 33.3% of VCC, and is pulled to GND when the TM voltage goes back to above 39.1% of VCC. Figure 16 shows the operation of these signals. FN6504.0 March 3, 2008 ISL6336, ISL6336A The NTC resistance at the set point T2 and release point T1 of VR_FAN signal can be calculated as: VCC VR_FAN R (EQ. 21) R NTC ( T1 ) = 1.644xR NTC ( T3 ) (EQ. 22) With the NTC resistance value obtained from Equations 21 and 22, the temperature value T2 and T1 can be found from the NTC datasheet. 0.391VCC TM1 R NTC ( T2 ) = 1.267xR NTC ( T3 ) VR_HOT TM Temperature Compensation oc R NTC 0.333VCC FIGURE 14. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION In order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. The ISL6336, ISL6336A provides two methods: integrated temperature compensation and external temperature compensation. 100 90 VTM/VCC (%) 80 70 60 Integrated Temperature Compensation 50 40 30 20 0 ISL6336, ISL6336A supports inductor DCR sensing, or resistive sensing techniques. The inductor DCR has a positive temperature coefficient of about +0.385%/°C. Because the voltage across inductor is sensed for output current information, the sensed current has the same positive temperature coefficient as the inductor DCR. 20 40 60 80 100 120 140 TEMPERATURE (°C) When the TCOMP voltage is equal to or greater than VCC/15, ISL6336, ISL6336A will utilize the voltage at the TM and TCOMP pins to compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 17. FIGURE 15. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE WITH RECOMMENDED PARTS VCC ISen6 R TM1 TM TM 0.451*Vcc o 0.391*Vcc 0.333*Vcc c I6 D/A VCC VR_FAN NON-LINEAR A/D R NTC ISen5 ISen4 ISen3 ISen2 ISen1 CHANNEL CURRENT SENSE I5 I4 I3 I2 I1 ki R TC1 VR_HOT TEMPERATURE TCOMP T1 T2 T3 FIGURE 16. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE Based on the NTC temperature characteristics and the desired threshold of VR_HOT signal, the pull-up resistor RTM1 of TM pin is given by Equation 20: R TM1 = 2.75xR NTC ( T3 ) (EQ. 20) RNTC(T3) is the NTC resistance at the VR_HOT threshold temperature T3. 23 4-BIT A/D DROOP IOUT AND OVERCURRENT PROTECTION R TC2 FIGURE 17. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE COMPENSATION When the TM NTC is placed close to the current sense component (inductor), the temperature of the NTC will track the temperature of the current sense component. Therefore, the TM voltage can be utilized to obtain temperature of the current sense component. FN6504.0 March 3, 2008 ISL6336, ISL6336A Based on the VCC voltage, ISL6336, ISL6336A converts the TM pin voltage to a 6-bit digital signal for temperature compensation. With the non-linear A/D converter of ISL6336, ISL6336A, the TM digital signal is linearly proportional to the NTC temperature. For accurate temperature compensation, the ratio of the TM voltage to the NTC temperature of the practical design should be similar to that in Figure 15. Depending on the location of the NTC and the air-flowing, the NTC may be cooler or hotter than the current sense component. The TCOMP pin voltage can be utilized to correct the temperature difference between the NTC and the current sense component. When a different NTC type or different voltage divider is used for the TM function, the TCOMP voltage can also be used to compensate for the difference between the recommended TM voltage curve in Figure 16 and that of the actual design. According to the VCC voltage, ISL6336, ISL6336A converts the TCOMP pin voltage to a 4-bit TCOMP digital signal as TCOMP factor N. TCOMP factor N is an integer between 0 and 15. The integrated temperature compensation function is disabled for N = 0. For N = 4, the NTC temperature is equal to the temperature of the current sense component. For N < 4, the NTC is hotter than the current sense component. The NTC is cooler than the current sense component for N > 4. When N > 4, the larger TCOMP factor N, the larger the difference between the NTC temperature and the temperature of the current sense component. ISL6336, ISL6336A multiplexes the TCOMP factor N with the TM digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. The compensated channel current signal is used for droop and overcurrent protection functions. Design Procedure 8. If N = 15, do not need the pull-down resistor RTC2, otherwise obtain RTC2 by Equation 25: NxR TC1 R TC2 = ----------------------15 – N (EQ. 25) 9. Run the actual board under full load again with the proper resistors to TCOMP pin. 10. Record the output voltage as V1 immediately after the output voltage is stable with the full load; Record the output voltage as V2 after the VR reaches the thermal steady state. 11. If the output voltage increases over 2mV as the temperature increases, i.e. V2 - V1 >2mV, reduce N and redesign RTC2; if the output voltage decreases over 2mV as the temperature increases, i.e. V1 - V2 >2mV, increase N and redesign RTC2. A design spreadsheet is available to speed aid calculations. External Temperature Compensation By pulling the TCOMP pin to GND, the integrated temperature compensation function is disabled. In addition, one external temperature compensation network, shown in Figure 18, can be used to cancel the temperature impact on the droop (i.e. load line). COMP ISL6336, ISL6336A INTERNAL CIRCUIT FB o C VDIFF 1. Properly choose the voltage divider for TM pin to match the TM voltage vs temperature curve with the recommended curve in Figure 15. 2. Run the actual board under the full load and the desired cooling condition. 3. After the board reaches the thermal steady state, record the temperature (TCSC) of the current sense component (e.g., inductor) and the voltage at TM and VCC pins. 4. Use Equation 23 to calculate the resistance of the TM NTC, and find out the corresponding NTC temperature TNTC from the NTC datasheet. R NTC ( T 7. Choose the pull-up resistor RTC1 (typical 10kΩ); V TM xR TM1 = ------------------------------) V CC – V NTC TM (EQ. 23) 5. Use Equation 24 to calculate the TCOMP factor N: 209x ( T CSC – T ) NTC N = -------------------------------------------------------- + 4 3xT NTC + 400 (EQ. 24) FIGURE 18. EXTERNAL TEMPERATURE COMPENSATION The sensed current will flow out of the FB pin and develop the droop voltage across the resistor (RFB) between FB and VDIFF pins. If the RFB resistance reduces as the temperature increases, the temperature impact on the droop can be compensated. An NTC thermistor can be placed close to the power stage and used to form RFB. Due to the non-linear temperature characteristics of the NTC, a resistor network is needed to make the equivalent resistance between FB and VDIFF pin reverse proportional to the temperature. The external temperature compensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6336, ISL6336A. Therefore this network cannot compensate for the temperature impact on the overcurrent protection function. 6. Choose an integral number close to the above result for the TCOMP factor. If this factor is higher than 15, use N = 15. If it is less than 1, use N = 1. 24 FN6504.0 March 3, 2008 ISL6336, ISL6336A General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. Power Stages The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles generally between 20A and 25A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors, and heat-dissipating surfaces. MOSFETS The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 26, IM is the maximum continuous output current; IPP is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance. I L, 2PP ( 1 – d ) ⎛ I M⎞ 2 P LOW, 1 = r DS ( ON ) ⎜ -----⎟ ( 1 – d ) + -------------------------------12 ⎝ N⎠ (EQ. 26) An additional term can be added to Equation 26 to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, fS; and the length of dead times, tD1 and tD2, at the beginning and the end of the lower-MOSFET conduction interval respectively. 25 ⎛I ⎞ I M I PP⎞ M I-------P LOW, 2 = V D ( ON ) f S ⎛ -----⎠ t d1 + ⎜ ----- – PP-⎟ t d2 ⎝ N- + -------2 ⎠ 2 ⎝N (EQ. 27) Thus, the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upper MOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverse recovery charge, Qrr; and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 28, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. I M I PP⎞ ⎛ t 1 ⎞ P UP,1 ≈ V IN ⎛ ----- ⎜ ---- ⎟ f ⎝ N- + -------2 ⎠⎝ 2⎠ S (EQ. 28) At turn-on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 29, the approximate power loss is PUP,2. ⎛ I M I PP⎞ ⎛ t 2 ⎞ P UP, 2 ≈ V IN ⎜ ----- – ---------⎟ ⎜ ---- ⎟ f S 2 ⎠⎝ 2⎠ ⎝N (EQ. 29) A third component involves the lower MOSFET’s reverse recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lower MOSFET’s body diode can draw all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3 and is approximated in Equation 30 : P UP,3 = V IN Q rr f S (EQ. 30) Finally, the resistive part of the upper MOSFET’s is given in Equation 31 as PUP,4. 2 I PP2 ⎛ I M⎞ P UP,4 ≈ r DS ( ON ) ⎜ -----⎟ d + ---------- d 12 ⎝ N⎠ (EQ. 31) The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 28, 29, 30 and 31. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. FN6504.0 March 3, 2008 ISL6336, ISL6336A Current Sensing Resistor The desired loadline can be calculated by Equation 34: The resistors connected to the ISEN+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors by the Equation 32. V DROOP R LL = -----------------------I FL RX I OCP R ISEN = -------------------------- ------------–6 N 105 ×10 (EQ. 32) where RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method, and IOCP is the desired overcurrent trip point. Typically, IOCP can be chosen to be 1.2 times the maximum load current of the specific application. With integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the temperature effect on the current sense element RX is cancelled by the integrated temperature compensation function. RX in Equation 32 should be the resistance of the current sense element at the room temperature. When the integrated temperature compensation function is disabled by pulling the TCOMP pin to GND, the sensed current will be dependent on the operational temperature of the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. RX in Equation 32 should be the maximum DC resistance of the current sense element at all the operational temperature. In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistors. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section titled “Channel-Current Balance” on page 15). Choose RISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. ΔT R ISEN ,2 = R ISEN ----------2 ΔT 1 (EQ. 33) In Equation 33, make sure that ΔT2 is the desired temperature rise above the ambient temperature, and ΔT1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 33 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve optimal thermal balance between all channels. Load-Line Regulation Resistor (EQ. 34) where IFL is the full load current of the specific application, and VRDROOP is the desired voltage droop under the full load condition. Based on the desired loadline RLL, the loadline regulation resistor can be calculated by Equation 35: NR R ISEN LL R FB = --------------------------------RX (EQ. 35) where N is the active channel number, RISEN is the sense resistor connected to the ISEN+ pin, and RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method. If one or more of the current sense resistors are adjusted for thermal balance, as in Equation 35, the load-line regulation resistor should be selected based on the average value of the current sensing resistors, as given in Equation 36: R LL R FB = ---------RX ∑ RISEN ( n ) (EQ. 36) n where RISEN(n) is the current sensing resistor connected to the nth ISEN+ pin. Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, RC and CC. Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. The load-line regulation resistor is labelled RFB in Figure 6. Its value depends on the desired loadline requirement of the application. 26 FN6504.0 March 3, 2008 ISL6336, ISL6336A C2 (OPTIONAL) ISL6336, ISL6336A RC CC COMP FB + RFB VDROOP VDIFF FIGURE 19. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6336, ISL6336A CIRCUIT The feedback resistor, RFB, has already been chosen as outlined in “Load-Line Regulation Resistor” on page 26. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to ensure adequate transient performance, but generally smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the three cases which follow, there are a separate set of equations for the compensation components. Case 1: The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 19). Keep a position available for C2, and be prepared to install a high frequency capacitor between 22pF and 150pF in case excessive jitter is noted. Once selected, the compensation values in Equation 37 ensure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equation 37 unless some performance issue is noted. C1 and R1 can also be added to improve transient performance per the type III compensation discussion below. COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 20, provides the necessary compensation. C2 ISL6336, ISL6336A RC 1 ------------------- > f 0 2π LC 2πf 0 V PP LC R C = R FB -----------------------------------0.75V IN CC COMP FB C1 0.75V IN C C = ----------------------------------2πV PP R FB f 0 R1 RFB VDIFF Case 2: 1 1 ------------------- ≤ f 0 < ----------------------------2πC ( ESR ) 2π LC V PP ( 2π ) 2 f 02 LC R C = R FB -------------------------------------------0.75 V IN (EQ. 37) 0.75V IN C C = -----------------------------------------------------------2 ( 2π ) f 02 V PP R FB LC Case 3: 1 f 0 > -----------------------------2πC ( ESR ) 2π f 0 V PP L R C = R FB ----------------------------------------0.75 V IN ( ESR ) 0.75V IN ( ESR ) C C C = -----------------------------------------------2πV PP R FB f 0 L In Equation 37, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in the “Electrical Specifications” table beginning on page 7. 27 FIGURE 20. COMPENSATION CIRCUIT FOR ISL6336, ISL6336A BASED CONVERTER WITHOUT LOAD-LINE REGULATION The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to ensure adequate transient performance but generally not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to ensure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose fHF = 10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth. In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equation 38, RFB is selected arbitrarily. The remaining compensation components are then selected according to Equation 38. FN6504.0 March 3, 2008 ISL6336, ISL6336A response, the output voltage initially deviates by an amount, as shown in Equation 39: C ( ESR ) R 1 = R FB ----------------------------------------LC – C ( ESR ) di ΔV ≈ ( ESL ) ⋅ ----- + ( ESR ) ⋅ ΔI dt LC – C ( ESR ) C 1 = ----------------------------------------R FB (EQ. 39) The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔVMAX. 0.75V IN C 2 = -----------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V PP (EQ. 38) 2 V PP ⎛ 2π⎞ f 0 f HF LCR FB ⎝ ⎠ R C = -------------------------------------------------------------------⎛2πf ⎞ 0.75 V ⎝ HF LC – 1⎠ IN ⎞ 0.75V IN ⎛2πf ⎝ HF LC – 1⎠ C C = ------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V PP In Equation 38, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in the “Electrical Specifications” table beginning on page 7. Output Filter Design The output inductors and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ΔI; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ΔVMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator 28 Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see “Interleaving” on page 11 and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance, as shown in Equation 40. ⎛V – N ⋅ V ⎞ OUT⎠ ⋅ V OUT ⎝ IN L ≥ ( ESR ) ⋅ -------------------------------------------------------------------f S ⋅ V IN ⋅ V PP( MAX ) (EQ. 40) Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. Equation 41 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 42 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually much less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. 2 ⋅ N ⋅ C ⋅ VO L ≤ --------------------------------- ΔV MAX – ( ΔI ⋅ ( ESR ) ) ( ΔI ) 2 1.25 ⋅ N ⋅ C L ≤ ----------------------------- ΔV MAX – ( ΔI ⋅ ( ESR ) ) ⋅ ⎛ V IN – V O⎞ ⎝ ⎠ ( ΔI ) 2 (EQ. 41) (EQ. 42) Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 25, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response FN6504.0 March 3, 2008 ISL6336, ISL6336A Switching frequency is determined by the selection of the frequency-setting resistor, RT (see “Typical Application - 5Phase Buck Converter with DCR Sensing and Integrated TCOMP” on page 5 and “Typical Application - 4-Phase Buck Converter with coupled inductors” on page 6). Equation 3 is provided to assist in selecting the correct value for RT. Input Capacitor Selection The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs that is related to duty cycle and the number of active phases. INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0.2 0.4 0.6 DUTY CYCLE (VO/VIN) 0.8 1.0 FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 2-PHASE CONVERTER INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.25 IO IL,PP = 0.75 IO 0.2 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0.2 0.1 0 0 0.2 0.4 0.6 DUTY CYCLE (VO/VIN) 0.8 1.0 FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 4-PHASE CONVERTER For a two phase design, use Figure 21 to determine the input-capacitor RMS current requirement given the duty cycle, maximum sustained output current (IO), and the ratio of the per-phase peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. They result from the high current slew rates produced by the upper MOSFETs turning on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression. More than one of these low ESL capacitors may be needed. MULTIPHASE RMS IMPROVEMENT 0.1 0 IL,PP = 0 IL,PP = 0.25 IO Figures 22 and 23 provide the same input RMS current information for three and four phase designs respectively. Use the same approach to selecting the bulk capacitor type and number, as previously described. 0.1 0 0.3 INPUT-CAPACITOR CURRENT (IRMS/IO) and small output-voltage ripple as outlined in “Output Filter Design” on page 28. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. 0.2 0.4 0.6 DUTY CYCLE (VO/VIN) 0.8 1.0 FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 3-PHASE CONVERTER 29 Figure 24 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multiphase topology. For example, compare the input RMS current requirements of a two-phase converter versus that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of IL,PP to IO of 0.5. The single phase converter would require 17.3ARMS current capacity while the two-phase converter would only require 10.9ARMS. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach. FN6504.0 March 3, 2008 ISL6336, ISL6336A The ISL6336, ISL6336A can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, RT resistor, feedback resistor, and compensation components. INPUT-CAPACITOR CURRENT (IRMS/IO) 0.6 0.4 Bypass capacitors for the ISL6336, ISL6336A and ISL66xx driver bias supplies must be placed next to their respective pins. Trace parasitic impedances will reduce their effectiveness. 0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 Plane Allocation and Routing 0.4 0.6 DUTY CYCLE (VO/VIN) 0.8 1.0 FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER Layout Considerations The following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. The following sections highlight some important practices which should not be overlooked during the layout process. Component Placement Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that spaces between the components are minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. Dedicate one solid layer, usually a middle layer, for a ground plane. Make all critical component ground connections with vias to this plane. Dedicate one additional layer for power planes; breaking the plane up into smaller islands of common voltage. Use the remaining layers for signal wiring. Route phase planes of copper filled polygons on the top and bottom once the switching component placement is set. Size the trace width between the driver gate pins and the MOSFET gates to carry 4A of current. When routing components in the switching path, use short wide traces to reduce the associated parasitic impedances. Voltage Regulator (VR) Design Materials Voltage tolerance band calculation (TOB) worksheets for VR output regulation and IMON tolerance have been developed using the Root-Sum-Squared (RSS) method with 3-sigma distribution data of the related components and parameters. Note that the “Electrical Specifications” table beginning on page 7 specifies no less than 6-sigma distribution data and is not suitable for RSS TOB calculations. Intersil has developed a set of worksheets to help support VR designs and layout. Contact Intersil’s local office or field support for the latest information. Next, place the input and output capacitors. Position one high frequency ceramic input capacitor next to each upper MOSFET drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions. Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 30 FN6504.0 March 3, 2008 ISL6336, ISL6336A Package Outline Drawing L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4X 5.5 7.00 A 44X 0.50 B 37 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 48 1 7.00 36 4. 30 ± 0 . 15 12 25 (4X) 0.15 13 24 0.10 M C A B 48X 0 . 40± 0 . 1 TOP VIEW 4 0.23 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" ( 6 . 80 TYP ) ( 0.10 C BASE PLANE 0 . 90 ± 0 . 1 4 . 30 ) C SEATING PLANE 0.08 C SIDE VIEW ( 44X 0 . 5 ) C 0 . 2 REF 5 ( 48X 0 . 23 ) ( 48X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 31 FN6504.0 March 3, 2008