ISL97634 ® Data Sheet April 10, 2007 White LED Driver with Wide PWM Dimming Range Features • Drives Up to 6 LEDs in Series The ISL97634 represents an efficient and highly integrated PWM boost LED driver that is suitable for 1.8” to 3.5” LCDs that employ 2 to 6 white LEDs for backlighting. With integrated Schottky diode, OVP, and wide range of PWM dimming capability, the ISL97634 provides a simple, reliable, and flexible solution to the backlight designers. The ISL97634 features a wide range of PWM dimming control capability. It allows dimming frequency as low as DC to 32kHz beyond audible spectrum. The ISL97634 also features a feedback disconnect switch to prevent the output from being modulated by the PWM dimming signal that minimizes system disturbance. The ISL97634 is available in the 8 Ld TDFN (2mmx3mm) package. There are 14V, 18V, and 26V OVP options that are suitable for 3 LEDS, 4 LEDs, and 6 LEDs backlight applications respectively. The ISL97634 is specified for operation over the -40°C to +85°C ambient temperature at input voltage from 2.4V to 5.5V. Pinout ISL97634 (8 LD TDFN) TOP VIEW GND 1 8 LX VIN 2 7 VOUT PWM/EN 3 6 FBSW NC 4 5 FB • OVP (14V, 18V, and 26V for 3, 4 and 6 LEDs Applications) • PWM Dimming Control From DC to 32kHz • Output Disconnect Switch • Integrated Schottky Diode • 2.4V to 5.5V Input • 85% Efficiency • 1.4MHz Switching Frequency Allows Small LC • 1µA Shutdown Current • Internally Compensated • 8 Ld TDFN (2mmx3mm) • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • LED Backlighting for: - Cell phones - Smartphones - MP3 - PMP - Automotive Navigation Panel - Portable GPS Ordering Information PART NUMBER (Note) ISL97634IRT14Z-T PART MARKING PWM/EN 13” 8 Ld 2x3 TDFN L8.2x3A (1k pcs.) ISL97634IRT18Z-T ELF 13” 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) ISL97634IRT18Z-TK ELF 13” 8 Ld 2x3 TDFN L8.2x3A (1k pcs.) ISL97634IRT26Z-T ELG 13” 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) ISL97634IRT26Z-TK ELG 13” 8 Ld 2x3 TDFN L8.2x3A (1k pcs.) VOUT FBSW GND FB 1 PKG. DWG. # ISL97634IRT14Z-TK ELE LX NC PACKAGE (Pb-free) 13” 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) VIN VIN TAPE & REEL (QTY) ELE Typical Application Circuit 10µH or 22µH FN6264.2 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97634 Absolute Maximum Ratings (TA = +25°C) Thermal Information Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Thermal Resistance θJA (°C/W) θJC (°C/W) TDFN Package (Notes 1, 2). . . . . . . . . 77 12 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40°C to +85°C unless otherwise stated. Typ values are for information purposes only at TJ = TC = TA = +25°C. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER VIN = VPWM/EN = 3V DESCRIPTION VIN Supply Voltage IIN Supply Current CONDITION MIN TYP 2.4 PWM/EN = 3V, enabled, not switching 0.8 PWM/EN = 0V, disabled fSW DMAX ILIM RSW(LX) ILEAK Switching Frequency UNIT 5.5 V 1.5 mA 1 μA 1,600 kHz 1,300 1,450 Maximum Switching Duty Cycle 90 95 % LX Current 400 470 mA mΩ LX Switch ON-Resistance ILX = 100mA 900 LX Switch Leakage Current VLX = 28V 0.01 1 μA 95 100 mV 1 μA VFB Feedback Voltage IFB FB Pin Bias Current RSW(FBSW) MAX 90 VFB = 95mV FBSW Switch ON-Resistance Ω 10 VDIODE Schottky Diode Forward Voltage IDIODE = 100mA, TA = +25°C 600 OVP Overvoltage Protection ISL97634IRT14Z 14 V ISL97634IRT18Z 18 V ISL97634IRT26Z 26 VIL Logic Low Voltage of PWM/EN VIH Logic High Voltage of PWM/EN 2 1.5 850 mV 28 V 0.6 V V FN6264.2 April 10, 2007 ISL97634 Block Diagram VIN (2.4V to 5.5V) L CIN VIN PWM/EN 1.4MHZ OSCILLATOR AND RAMP GENERATOR LX ISL97634 VOUT COUT PWM COMPARATOR PWM LOGIC CONTROLLER FET DRIVER 2 LEDs to 6 LEDS CURRENT SENSE GND FBSW PWM/EN GM AMP COMPENSATION GM AMPLIFIER FB 95mV BANDGAP REFERENCE GENERATOR RSET Pin Description PIN NUMBER PIN NAME 1 GND Ground Pin. Connect to local ground. 2 VIN Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling capacitor. 3 PWM/EN PWM or Enable Pin. Connect external PWM signal allows pulse width modulation current operation. Enable signal allows peak current operation or disable signal shuts down the device. 4 NC No Connect 5 FB Feedback Pin. Connect the sense resistor between FB and ground. The cathode of bottom LED can also be connected at this pin if the output current is not to be PWMed. 6 FBSW FB Disconnect Switch. Connect to the cathode of the bottom LED if the output current to be PWMed. 7 VOUT Output Pin. Connect to the anode of the top LED and the output filter capacitor. 8 LX DESCRIPTION Switching Pin. Connect to inductor. 3 FN6264.2 April 10, 2007 ISL97634 Typical Performance Curves 1.0 90 85 0.8 0.6 4 LEDs, 10µH 75 3 LEDs, 10µH 70 3 LEDs, 22µH 65 6 LEDs, 10µH 6 LEDs, 22µH ILED_peak = 25mA VIN = 4V 55 RSET = 4Ω fPWM = 1kHz 0 20 0.4 0.2 60 50 Iq (mA) EFFICIENCY (%) 80 40 60 80 PWM DUTY CYCLE (%) 0.0 -0.2 100 FIGURE 1. EFFICIENCY vs PWM DUTY CYCLE 0 1 2 3 VIN (V) 4 6 5 FIGURE 2. QUIESCENT CURRENT vs VIN (PWM/EN = HI) 20.08 19.76 19.74 20.04 IO (mA) IO (mA) 19.72 20.00 19.70 19.68 19.66 19.96 19.64 19.92 0 5 10 15 VOUT (V) 20 25 30 19.62 2.5 FIGURE 3. LOAD REGULATION (VIN = 4V) 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 FIGURE 4. LINE REGULATION 100 6 LEDs VIN = 4V RSET = 4Ω L = 10µH 90 FB VOLTAGE (mV) 80 70 VOUT VIN = 4V 1kHz R1 = 4Ω L1 = 22µH LX 60 50 40 PWM/EN 30 20kHz 20 10 32kHz ILED 0 0 20 40 60 80 100 120 DUTY CYCLE (%) FIGURE 5. DIMMNG LINEARITY (FB VOLTAGE) vs DUTY CYCLE 4 FIGURE 6. PWM DIMMING AT 1kHz, D = 1% FN6264.2 April 10, 2007 ISL97634 VOUT VOUT LX LX PWM/EN PWM/EN VIN = 4V ILED R1 = 4Ω L1 = 22µH ILED VIN = 4V R1 = 4Ω L1 = 22µH FIGURE 7. PWM DIMMING AT 1kHz, D = 1% ZOOM IN FIGURE 8. PWM DIMMING AT 1kHz, D = 99% VOUT LX PWM/EN ILED R1 = 4Ω VIN = 4V L1 = 22µH FIGURE 9. PWM DIMMING AT 20kHz, D = 50% Detailed Description The ISL97634 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. There are three OVP models for driving 3, 4, and 6 LEDs and their OVP thresholds are set at 14V, 18V, and 26V respectively. The ISL97634 operates from an input voltage of 2.4V to 5.5V and ambient temperature from -40°C to +85°C. The switching frequency is around 1.45MHz and allows the driver circuit to employ small LC components. The peak forward current of the LED is set using the RSET resistor. In the steady state mode, the LED peak current is given by the following equation: V FB I LED = --------------R SET (EQ. 1) PWM Dimming The ISL97634’s PWM/EN pin can be tied permanently to high for a fixed current operation. On the other hand, the ISL97634 can be applied with an external PWM signal to 5 pulse width modulated the output current. It is well understood that the LED brightness is a linear function of the LED current. In addition, the average LED current corresponds to the duty cycle “D” of the PWM signal as: V FB I LED – AVG = --------------- ⋅ D R SET (EQ. 2) As a result, PWM signal provides a means to dim the LED brightness. PWM dimming offers the best LEDs matching over DC dimming. It is because the LED peak current operating point is far away from the knee of the diode I-V curve where part to part variations are high. The PWM dimming test results are shown in Figure 6 with two PWM frequencies, 1kHz and 20kHz. The vertical scale parameter FB is proportional to the current and therefore the brightness. For the ISL97634, PWM dimming provides linear dimming adjustment with low frequency signal, such as 1kHz and below. The applied PWM dimming signal can be up to 32kHz FN6264.2 April 10, 2007 ISL97634 ; however, the dimming linearity is compromised at low duty cycles as their durations are too short for the ISL97634’s control loop to respond properly. This non ideality behavior does not cause any functional problem. The PWM dimming linear responses in Figure 5 are expanded in Figure 10. At 1kHz PWM dimming, the duty cycle can virtually vary from below 1% to DC. On the other hand, at 20kHz PWM dimming, the linearity range is from 5% to DC only. FB VOLTAGE (mV) 8 VOUT LX PWM/EN 10 9 . 6 LEDs VIN = 4V RSET = 4Ω L = 10µH VIN = 4V 1kHz ILED 7 R1 = 4Ω L1 = 22µH 6 FIGURE 12. PWM DIMMING AT 1kHz WITHOUT USING FBSW 5 4 3 20kHz 2 1 32kHz 0 0 2 4 6 8 DUTY CYCLE (%) 10 12 FIGURE 10. DIMMING LINEARITY vs DUTY CYCLES ZOOM IN The low level non-linearity effects at high frequency PWM dimming is also reflected in the efficiency measurements in Figure 11. The FBSW should be used for PWM dimming as illustrated in “Typical Application Circuit” on page 1. During the PWM off time, the FBSW is opened. The LEDs are floating and therefore the output capacitor has no path to discharge. The LED current responds accurately with the PWM signal (see Figure 13). The output switches very quickly to the target current with minimal settling ringing and without being modulated by the PWM signal and therefore minimizes any system disturbance. VOUT 90 85 LX EFFICIENCY (%) 80 75 PWM/EN 70 60 3 LEDs VIN = 4V 55 RSET = 4Ω L = 22µH 50 0 5 10 15 ILED (mA) 20 25 VIN = 4V R1 = 4Ω L1 = 22µH 65 ILED 30 FIGURE 11. EFFICIENCY vs PWM DIMMING FREQUENCIES Feedback Disconnect Switch The ISL97634 functions properly without using the FBSW. However, the output capacitor will discharge during the PWM off time resulting in poor dimming linearity at low duty cycles. The output discharge effect can be seen in Figure 12. Moreover, the output is modulated by the PWM signal that may create interference to other systems. FIGURE 13. PWM DIMMING AT 1kHz USING FBSW Overvoltage Protection The ISL97634 comes with overvoltage protection. The OVP trip points are at 14V, 18V, and 26V for ISL97634IRT14Z, ISL97634IRT18Z, and ISL97634IRT26Z respectively. The maximum numbers of LEDs and OVP threshold are shown in Table 1. When the device reaches the OVP, the LX stops switching, disabling the boost circuit until VOUT falls about 7% below the OVP threshold. At this point, LX will be allowed to switch again. The OVP event will not cause the device to shutdown. There are three OVP options so that the 3 LEDs application should use the 14V OVP device and the 6 LEDs application should use the 26V OVP device. An output capacitor that is only rated for the required voltage range can therefore be 6 used, which will optimize the component costs in some cases. FN6264.2 April 10, 2007 ISL97634 TABLE 1. OVP MAX NO. OF LEDS MAX ILED ISL97634IRT14Z 14V 3 70mA ISL97634IRT18Z 18V 4 50mA ISL97634IRT26Z 26V 6 30mA PART NO. ISL97634 has internal compensation network that ensures the device operates reliably under the specified conditions. The internal compensation and the highly integrated functions of the ISL97634 make it a design friendly device to be used in high volume, high reliability applications. Applications Analog Dimming Shutdown When PWM/EN is taken low the ISL97634 enters into the power down mode where the supply current is reduced to less than 1µA. The device resumes normal when the PWM/EN goes high. Components Selection The input capacitance is typically 0.22µF. The output capacitor should be in the range of 0.22µF to 1µF. X5R or X7R type of ceramic capacitors of the appropriate voltage rating are recommended. When choosing an inductor, make sure the average and peak current ratings are adequate by using the following formulas (80% efficiency assumed): I LED ⋅ V OUT I LAVG = --------------------------------0.8 ⋅ V IN (EQ. 3) 1 I LPK = I LAVG + --- ⋅ ΔI L 2 (EQ. 4) V IN ⋅ ( V OUT – V IN ) ΔI L = --------------------------------------------------L ⋅ V OUT ⋅ f OSC (EQ. 5) Analog dimming is usually not recommended because of the brightness non-linearity at low levels dimming. However, some systems are EMI or noise sensitive that analog dimming may be more suitable than PWM dimming under those situations. The ISL97632 is part of the same family as the ISL97634 and has been designed with a serial interface to give access to 32 separate dimming levels. Alternatively analog dimming can be achieved by applying a variable DC voltage (VDim) at FB pin (see Figure 14) to adjust the LED current. As the DC dimming signal voltage increases above VFB, the voltages drop on R1 and R2 increase and the voltage drop on RSET decreases. Thus, the LED current decreases. V FB ⋅ ( R 1 + R 2 ) – V Dim ⋅ R 1 I LED = -------------------------------------------------------------------------R2 ⋅ R (EQ. 6) SET If VDIM is taken below FB, the inverse will happen and the brightness will increase. The DC dimming signal voltage can be a variable DC voltage from a POT, a DCP (Digitally Controlled Potentiometer), or a DC voltage generated by filtering a high frequency PWM control signal. L1 22µH Where: VIN • ΔIL is the peak-to-peak inductor current ripple in Amps • L is the inductance in H. LEDs VIN 3.3V VOUT C1 1µF • fOSC is the switching frequency, typically 1.45MHz The ISL97634 supports a wide range of inductance values (10µH~82µH). For lower inductor values or lighter loads, the boost inductor current may become discontinuous. For high boost inductor values, the boost inductor current will be in continuous mode. In addition to the inductor value and switching frequency, the input voltage, number of LEDs and the LED current also affects whether the converter operates in continuous conduction or discontinuous conduction mode. Both operating modes are allowed and normal. The discontinuous conduction mode yields lower efficiency due to higher peak current. Compensation LX C2 0.22µF ISL97634 R1 PWM FB GND R2 3.3k RSET 4.75Ω VDim FIGURE 14. ANALOG DIMMING CONTROL APPLICATION CIRCUIT As brightness is directly proportional to LED currents, VDim may be calculated for any desired “relative brightness” (F) using Equation 7: R2 R1 ⎛ ⎞ V Dim = ------- ⋅ V FB ⋅ ⎜ 1 + ------- – F⎟ R1 R2 ⎝ ⎠ (EQ. 7) Where F = ILED (dimmed)/ILED (undimmed). These equations are valid for values of R1 and R2 such that both R1>>RSET and R2>>RSET. The product of the output capacitor and the load create a pole while the inductor creates a right half plane zero. Both of these attributes degrade the phase margin but the 7 FN6264.2 April 10, 2007 ISL97634 [ ( V Dim_max – V FB ) • R 1 ] R 2 = ------------------------------------------------------------------[ V FB • ( 1 – F min ) ] (EQ. 8) Where VDim_max is the maximum VDim voltage and Fmin is the minimum relative brightness (i.e., the brightness with VDim_max applied). i.e., VDim_max = 5V, Fmin = 10% (i.e., 0.1), R2 = 189k i.e., VDim_max = 1V, Fmin = 10% (i.e., 0.1), R2 = 35k Efficiency Improvement Figure 1 shows the efficiency measurements during PWM operation. The choice of the inductor has a significant impact on the power efficiency. As shown in Equation 4, the higher the inductance, the lower the peak current therefore the lower the conduction and switching losses. On the other hand, it has also a higher series resistance. Nevertheless, the efficiency improvement effect by lowering the peak current is greater than the resistance increases with larger value of inductor. Efficiency can also be improved for systems that have high supply voltages. Since the ISL97634 can only supply from 2.4V to 5.5V, VIN must be separated from the high supply voltage for the boost circuit as shown in Figure 15 and the efficiency improvement is shown in Figure 16. C3 0.22µ D1 L1 Vs = 12V C1 1 C2 22µ 1µ VIN = 2.7V to 5.5V 0.1µ D2 2 D3 D4 VIN LX VOUT ISL97634 FBSW D5 D6 FB PWM/EN GND R1 4Ω FIGURE 15. SEPARATE HIGH INPUT VOLTAGE FOR HIGHER EFFICIENCY OPERATION 8 . 90 EFFICIENCY (%) The analog dimming circuit can be tailored to a desired relative brightness for different VDim ranges using Equation 8. VS = 12V VS = 9V 85 80 VIN = 4V 6 LEDs L1 = 22µH R1 = 4Ω fPWM 75 70 0 5 10 15 20 25 30 ILED (mA) FIGURE 16. EFFICIENCY IMPROVEMENT WITH 9 AND 12V INPUTS 8 LEDs Operation For medium size LCDs that need more than 6 low power LEDs for backlighting, such as a Portable Media Player or Automotive Navigation Panel displays, the voltage range of the ISL97634 is not sufficient. However, the ISL97634 can be used as an LED controller with an external protection MOSFET connected in cascode fashion to achieve higher output voltage. A conceptual 8 LEDs driver circuit is shown in Figure 17. A 60V logic level N-Channel MOSFET is configured such that its drain ties between the inductor and the anode of schottky diode, its gate ties to the input, and its source ties to the ISL97634 LX node connecting to the drain of the internal switch. When the internal switch turns on, it pulls the source of M1 down to ground, and LX conducts as normal. When the internal switch turns off, the source of M1 will be pulled up by the follower action of M1, limiting the maximum voltage on the ISL97634 LX pin to below Vin, but allowing the output voltage to go much higher than the breakdown limit on the LX pin. The switch current limit and maximum duty cycle will not be changed by this setup, so input voltage will need to be carefully considered to make sure that the required output voltage and current levels are achievable. Because the source of M1 is effectively floating when the internal LX switch is off, the drain-to-source capacitance of M1 may be sufficient to capacitively pull the node high enough to breaks down the gate oxide of M1. To prevent this, VOUT should be connected to VIN, allowing the internal schottky to limit the peak voltage. This will also hold the VOUT pin at a known low voltage, preventing the built in OVP function from causing problems. This OVP function is effectively useless in this mode as the real output voltage is outside its intended range. If the user wants to implement their own OVP protection (to prevent damage to the output capacitor, they should insert a zener from vout to the FB pin. In this setup, it would be wise not to use the FBSW to FB switch as otherwise the zener will have to be a high power one capable of dissipating the entire LED load power. Then the LED stack can then be connected directly to the sense resistor and via a 10k resistor to FB. A zener can be placed from Vout to the FB pin allowing an over voltage event to pull up on FB with a low breakdown current (and thus low power zener) as a result of the 10k resistor. FN6264.2 April 10, 2007 ISL97634 1 C1 1µ L1 D0 2 2.2µ 10BQ100 M1 FQT13N06L SK011C226KAR VIN C2 0.1µ C3 4.7µ VOUT LX ISL97634 FBSW D1 D2 D3 D4 FB PWM/EN GND D5 R1 6.3Ω D6 D7 D8 FIGURE 17. CONCEPTUAL 8 LEDs HIGH VOLTAGE DRIVER SEPIC Operation For applications where the output voltage is not always above the input voltage, a buck or boost regulation is needed. A SEPIC (Single Ended Primary Inductance Converter) topology, shown in Figure 18, can be considered for such application. A single cell Li-Ion battery operating a cellular phone backlight or flashlight is one example. The battery voltage is between 2.5V and 4.2V, depending on the state of charge. On the other hand, the output may require only one 3V to 4V medium power LED for illumination because the light guard of the backlight assembly is optimized for cost efficiency trade-off reason. In fact, a SEPIC configured LED driver is flexible enough to allow the output to be well above or below the input voltage, unlike the previous example. Another example is when the number of LEDs and input requirements are different from platform to platform, a common circuit and PCB that fit all the platforms in some cases may be beneficial enough that it outweighs the disadvantage of adding additional component cost. L1 and L2 can be a coupled inductor in one package. VIN = 2.7V to 5.5V 1 L1 2 22µ C1 1µ VA C3 VB 1µ D0 L2 22µ C4 (EQ. 9) where D is the on-time of the PWM duty cycle. The convenience of SEPIC comes with some trade off in addition to the additional L and C costs. The efficiency is usually lowered because of the relatively large efficiency loss through the Schottky diode if the output voltage is low. The L2 series resistance also contributes additional loss. Figure 19 shows the efficiency measurement of a single LED application as the input varies between 2.7V and 4.2V. Note VB is considered the level-shifted LX node of a standard boost regulator. The higher the input voltage, the lower the VB voltage will be during PWM on period. The result is that the efficiency will be lower at higher input voltages because the SEPIC has to work harder to boost up to the required level. This behavior is the opposite to the standard boost regulator’s and the comparison is shown in Figure 19. 76 VIN = 2.7V 72 VIN = 4.2V 68 1 LED L1 = L2 = 22µH 64 C3 = 1µF R1 = 4.7Ω 60 LX VOUT ISL97634 FBSW VIN 0 5 10 ILED (mA) 15 20 FIGURE 19. EFFICIENCY MEASUREMENT OF A SINGLE LED SEPIC DRIVER FB SDIN D V OUT = V IN -----------------(1 – D) 0.22µ D1 C2 0.1µ The SEPIC works as follows; assume the circuit in Figure 18 operates normally, when the ISL97634 internal switch opens and it is in the PWM off state, after a short duration where few LC time constants elapsed, the circuit is considered in the steady-state within the PWM off period that L1 and L2 are shorted. VB is therefore shorted to the ground and C3 is charged to VIN with VA = VIN. When the ISL97634 internal switch closes and the circuit is in the PWM on state, VA is now pulled to ground. Since the voltage in C3 cannot be changed instantaneously, therefore VB is shifted downward and becomes -VIN. The next cycle when the ISL97634 switch opens, VB boosts up to the targeted output like the standard boost regulator operation, except the lowest reference point is at -VIN. The output is approximated as: EFFICIENCY (%) VIN = 2.7V to 5.5V PCB Layout Considerations GND R1 1Ω FIGURE 18. SEPIC LED DRIVER The simplest way to understand SEPIC topology is to think about it as a boost regulator where the input voltage is level shifted downward at the same magnitude and the lowest reference level starts at -VIN rather than 0V. 9 The layout is very important for the converter to function properly. RSET must be located as close as possible to the FB and GND pins. Longer traces to the LEDs are acceptable. Similarly, the supply decoupling cap and the output filter cap should be as close as possible to the VIN and VOUT pins. The heat of the IC is mainly dissipated through the thermal pad of the package. Maximizing the copper area connected to this pad if possible. In addition, a solid ground plane is always helpful for the EMI performance. FN6264.2 April 10, 2007 ISL97634 Thin Dual Flat No-Lead Plastic Package (TDFN) L8.2x3A 2X 0.15 C A A D 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C B SYMBOL E MIN A 0.70 A1 - 6 A3 INDEX AREA b TOP VIEW D2 0.20 0.10 SIDE VIEW C SEATING PLANE D2 (DATUM B) 0.08 C A3 7 0.75 0.80 - - 0.05 - 0.25 0.32 1.50 1.65 1.75 1 7,8 3.00 BSC - 8 1.65 e 1.80 1.90 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 8 Nd 4 D2/2 6 INDEX AREA 5,8 C E2 A NOTES 2.00 BSC E // MAX 0.20 REF D B NOMINAL 2 3 Rev. 0 6/04 2 NX k NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. (DATUM A) E2 4. All dimensions are in millimeters. Angles are in degrees. E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. NX L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. N N-1 NX b e 8 5 0.10 (Nd-1)Xe REF. M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. BOTTOM VIEW CL (A1) NX (b) L 5 SECTION "C-C" C C TERMINAL TIP e FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6264.2 April 10, 2007