X9119
®
Single Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
PRELIMINARY
September 15, 2005
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8162.2
DESCRIPTION
The X9119 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 40Ω Typical @ VCC = 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current < 3µA Max
• VCC: 2.7V to 5.5V Operation
• 100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per
Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9118
• Pb-Free Plus Anneal Available (RoHS Compliant)
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four non-volatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
RH
Write
Read
Transfer
Control
VSS
1
NC
Power On Recall
100KΩ
1024-taps
POT
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
NC
Wiper
RW
RL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9119
Ordering Information
PART NUMBER
PART MARKING
X9119TV14I
X9119TV I
X9119TV14
X9119TV
X9119TV14-2.7*
X9119TV F
X9119TV14I-2.7
X9119TV G
POTENTIOMETER
VCC LIMITS (V) ORGANIZATION (kΩ) TEMP RANGE (°C)
5 ±10%
10
-2.7 to 5.5
X9119TV14IZ-2.7* (Note)
PACKAGE
-40 to 85
14 Ld TSSOP (4.4mm)
0 to 70
14 Ld TSSOP (4.4mm)
0 to 70
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm)
-40 to 85
14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
VCC
Power On
Recall
DR0 DR1
SCL
Interface
and
Control
Circuitry
SDA
A2
A1
Data
DR2 DR3
Wiper
Counter
Register
(WCR)
RH
100KΩ
1024-taps
RL
Control
A0
RW
WP
VSS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage
amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
2
FN8162.2
September 15, 2005
X9119
SERIAL CLOCK (SCL)
PIN CONFIGURATION
This input is used by 2-wire master to supply 2-wire
serial clock to the X9119.
TSSOP
NC
A0
NC
A2
SCL
SDA
VSS
14
1
13
2
3
12
4 X9119 11
5
10
6
9
8
7
VCC
RL
RH
RW
NC
A1
WP
PIN ASSIGNMENTS
DEVICE ADDRESS (A2–A0)
The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9119. A maximum of 8
devices may occupy the 2-wire serial bus.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Pin
(TSSOP)
Symbol
1
NC
No Connect
2
A0
Device Address for 2-wire bus
3
NC
No Connect
4
A2
Device Address for 2-wire bus
5
SCL
6
SDA
Serial Data Input/Output for 2-wire bus
7
VSS
System Ground
RW
8
WP
Hardware Write Protect
9
A1
Device Address for 2-wire bus
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Function
Serial Clock for 2-wire bus
10
NC
No Connect
11
RW
Wiper terminal of the Potentiometer
12
RH
High terminal of the Potentiometer
13
RL
Low terminal of the Potentiometer
14
VCC
System Supply Voltage
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
PIN DESCRIPTIONS
The VCC pin is the system supply voltage. The VSS
pin is the system ground.
Bus Interface Pins
Other Pins
SERIAL DATA INPUT/OUTPUT (SDA)
NO CONNECT
The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of
the serial clock SCL.
No connect pins should be left open. These pins are
used for Intersil manufacturing and testing purposes.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
PRINCIPLES OF OPERATION
The X9119 is an integrated microcircuit incorporating
a resistor array and its associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description
3
FN8162.2
September 15, 2005
X9119
Resistor Array Description
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
RH
Serial
Bus
Input
From Interface
Circuitry
Register 1
(DR1)
Register 0
(DR0)
10
Register 2
(DR2)
10
Register 3
(DR3)
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
RL
R
W
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
4
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 3.
STOP CONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
ACKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
FN8162.2
September 15, 2005
X9119
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE POLLING
ACKNOWLEDGE
FLOW 1. ACK Polling Sequence
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9119 is still busy with the write operation no ACK
will be returned. If the X9119 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Issue STOP
No
Yes
Further
Operation?
No
Yes
5
Issue
Instruction
Issue STOP
Proceed
Proceed
FN8162.2
September 15, 2005
X9119
Instruction and Register Description
DEVICE ADDRESSING: IDENTIFICATION BYTE
(ID AND A)
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9119; this is fixed as 0101[B] (refer to Table 1).
The A2–A0 bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A2–A0 input pins. The slave address is
externally specified by the user. The X9119 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9119 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2–A0 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS. The R/W bit is the LSB and is be used to
program the device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9119 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (IOP[2:0]). The RB and RA bits point to one of
the four registers. The format is shown below in
Table 2.
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Internal Slave
Address
Device Type
Identifies
ID3
ID2
ID1
ID0
0
1
0
1
A2
A1
Read or
Write Bit
A0
(MSB)
R/W
(LSB)
Table 2. Instruction Byte Format
Register
Selection
Instruction
Opcode
I2
I1
I0
0
(MSB)
RB
RA
0
0
(LSB)
Register Selected
RB
RA
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
6
FN8162.2
September 15, 2005
X9119
Table 3. Instruction Set
R/W
1
I2
1
I1
0
Instruction Set
I0
0 RB RA
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
1
0
1/0
1/0
0
0
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Note:
0
0
0
0
Operation
Read the contents of the Wiper Counter
Register
Write new value to the Wiper Counter
Register
Read the contents of the Data Register
pointed to RB-RA.
Write new value to the Data Register
pointed to RB-RA.
Transfer the contents of the Data Register
pointed to by RB-RA.to the Wiper Counter
Register
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA.
(1) 1/o = data is one or zero.
Instruction and Register Description
DEVICE ADDRESSING
WIPER COUNTER REGISTER (WCR)
The X9119 contains a Wiper Counter Registers (see
Table 4) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024
switches along its resistor array. The contents of the
WCR can be altered in one of three ways: (1) it may be
written directly by the host via the write wiper counter
register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR data register; (3)
it is loaded with the contents of its data register zero
(R0) upon power-up.
DATA REGISTERS (DR0 TO DR3)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the Wiper Counter Register.
All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit 9–Bit 0 are used to store one of the 1024 wiper
position (0 ~1023).
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9119 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
7
FN8162.2
September 15, 2005
X9119
Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Four of the six instructions are four bytes in length.
These instructions are:
Two instructions (see Figure 4) require a two-byte
sequence to complete. These instructions transfer
data between the host and the X9119; either between
the host and one of the data registers or directly
between the host and the Wiper Counter Register.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Write Wiper Counter Register – change current
wiper position of the selected potentiometer,
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers.
See Instruction format for more details.
POWER UP AND DOWN REQUIREMENTS
There are no restrictions on the power-up condition of
Vcc and the voltages applied to the potentiometer pins
provided that the Vcc is always more positive than or
equal to the voltages at RH, RL, and RW, i.e. VCC ≥
RH, RL, RW. There are no restrictions on the powerdown condition. However, the datasheet parameters
for the DCP do not apply until 1milisecond after VCC
reaches its final value.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0 A2 A1 A0 R/W
T
A
Internal
Device ID
R
Address
T
8
A
C
K
I2
I0
I1
Instruction
Opcode
0
0
0
RB RA 0
Register
Address
0
A
C
K
S
T
O
P
FN8162.2
September 15, 2005
X9119
Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
SCL
SDA
0
1
0
0
1
S ID3 ID2 ID1 ID0 A2 A1 A0 R/W A I2 I1 I0
T
C
A Device ID
K Instruction
Internal
R
Opcode
Address
T
0 X
0
X 0
X X
A
C
K
0 RB RA 0
Register
Address
X X
X X
W
C
R
9
W A W W
C C C C
R K R R
8
7 6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W A
C C
R K
0
S
T
O
P
Wiper or Data
Position
INSTRUCTION FORMAT
Device Type
Device
S
Identifier
Addresses
T
A
R 0 1 0 1 A2 A1 A0
T
R/W=1
Read Wiper Counter Register (WCR)
Instruction
Opcode
S
A
C
K 1 0 0 0
Register
Addresses
0
0
Wiper Position
(Sent by Slave on SDA)
S
A
W W
C
C C
0 K X X X X X X
R R
9 8
0
Wiper Position
(Sent by Slave on SDA)
M
A
W W W W W W W W
C C C C C C C C C
K R R R R R R R R
7 6 5 4 3 2 1 0
M
A
C
K
Wiper Position
S (Sent by Master on SDA)
A W W W W W W W W
C C C C C C C C C
K R R R R R R R R
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
Device Type
Device
S
Identifier
Addresses
T
A
R 0 1 0 1 A2 A1 A0
T
R/W=0
Write Wiper Counter Register (WCR)
Instruction
Opcode
S
A
C
K 1 0 1 0
Register
Addresses
0
0
0
Wiper Position
S (Sent by Master on SDA)
A
W W
C
C C
0 K X X X X X X R R
9 8
S
T
O
P
Read Data Register (DR)
R/W=1
Device Type
Device
S
Identifier
Addresses
T
A
R 0 1 0 1 A2 A1 A0
T
9
Instruction
Register
Wiper Position
Opcode
Addresses
(Sent by Slave on SDA)
S
S
A
A
W W
C
C
C C
K 1 0 1 0 RB RA 0 0 K X X X X X X R R
9 8
wiper position or data
(Sent by Slave on SDA)
M
A W W W W W W W W
C C C C C C C C C
K R R R R R R R R
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
FN8162.2
September 15, 2005
X9119
Device
Addresses
S
T
A
R 0 1 0 1 A2 A1 A0
T
Instruction
Opcode
Register
Addresses
Wiper Position or Data
(Sent by Master on SDA)
S
S
A
A
W
C
C
C
1
1
0
0
RB
RA
0
0
X
X
X
X
X
X
K
K
R
9
R/W=0
Device Type
Identifier
Wiper Position or Data
(Sent by Master on SDA)
S
W A W W W
C C C C C
R K R R R
8
7 6 5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
S S
W A T
C C O
R K P
0
HIGH-VOLTAGE
WRITE CYCLE
Write Data Register (DR)
Device Type
Device
S
Identifier
Addresses
T
A
R 0 1 0 1 A2 A1 A0
T
R/W=0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Instruction
Register
Opcode
Addresses
S S
S
A T
A
C O
C
K 1 1 1 0 RB RA 0 0 K P
HIGH-VOLTAGE
WRITE CYCLE
Device Type
Device
S
Identifier
Addresses
T
A
R 0 1 0 1 A2 A1 A0
T
R/W=1
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Instruction
Register
Opcode
Addresses
S S
S
A T
A
C O
C
K 1 1 0 0 RB RA 0 0 K P
Notes: (1) “A2 ~ A0”: stand for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
10
FN8162.2
September 15, 2005
X9119
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCL, SDA, or any address input
with respect to VSS ................................. -1V to +7V
∆V = | (VH–VL) | ......................................................5V
Lead temperature (soldering, 10s) .................... 300°C
IW (10s) ..............................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (VCC) Limits(4)
5V ± 10%
2.7V to 5.5V
Device
X9118
X9118-2.7
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operation conditions unless otherwise stated.)
Limits
Symbol
Parameter
RTOTAL
End to End Resistance
Min.
Typ.
Max.
100
Units
Test Conditions
kΩ
End to End Resistance Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
40
110
Ω
Wiper Current = ± 50µA,
VCC = 5V
150
300
Ω
Wiper Current = ± 50µA,
VCC = 3V
5
V
VSS = 0V
VTERM
Voltage on any RH or RL Pin
Noise
Resolution
VSS
-120
dBV
0.1
%
Absolute Linearity(1)
±1.5
Relative Linearity(2)
±0.5
Temperature Coefficient of RTOTAL
CH/CL/CW Potentiometer Capacitancies
MI(3)
Rw(n)(actual) – Rw(n)(expected),
where n=8 to 1006
±2.0
MI(3)
Rw(n)(actual) – Rw(n)(expected)(5)
±0.5
MI(3)
Rw(m + 1) – [Rw(m) + MI], where
m=8 to 1006
±1.0
MI(3)
Rw(m + 1) – [Rw(m) + MI](5)
ppm/°C
20
10/10/25
Ref: 1V
±1
±300
Ratiometric Temp. Coefficient
25°C, each pot
ppm/°C
pF
See Macro model
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot
(4) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
(5) ESD Rating on RH, RL, RW pins is 1.5KV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
11
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC supply current
(active)
3
mA
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
ICC2
VCC supply current
(nonvolatile write)
5
mA
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
ISB
VCC current (standby)
3
µA
VCC = +5.5V; VIN = VSS or VCC;
SDA = VCC;
(for 2-wire, Standby State only)
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage
current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
VOH
Output HIGH voltage
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
CAPACITANCE
Symbol
CIN/OUT
CIN
(6)
(6)
Test
Max.
Units
Test Conditions
Input/Output capacitance (SI)
8
pF
VOUT = 0V
Input capacitance (SCL, WP, A1 and A0)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
tPUR
(6)
Parameter
VCC Power-up Rate
Min.
Max.
Units
0.2
50
V/ms
(7)
Power-up to Initiation of read operation
1
ms
(7)
Power-up to Initiation of write operation
50
ms
tPUW
Notes: (6) This parameter is not 100% tested.
(7) tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued.
These parameters are not 100% tested.
(8) This is not a tested or guaranteed parameter and should be used only as a guideline.
12
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X9119
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
1533Ω
SPICE Macromodel
867Ω
RTOTAL
RL
RH
SDA OUTPUT
SDA OUTPUT
100pF
CW
CL
10pF
CL
10pF
25pF
100pF
RW
AC TIMING HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
0
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
tDH
SDA Data Output Hold Time
0
ns
TI
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
tBUF
Bus Free Time (Prior to Any Transmission)
1300
ns
tSU:WPA
A0, A1, A2 Setup Time
0
ns
tHD:WPA
A0, A1, A2 Hold Time
0
ns
13
250
ns
FN8162.2
September 15, 2005
X9119
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWR
Parameter
Typ.
Max.
Units
5
10
ms
High-voltage write cycle time (store instructions)
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load
instructions)
5
10
µs
tWRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
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X9119
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
RW
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1, A2
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X9119
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10kΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
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FN8162.2
September 15, 2005
X9119
Application Circuits (Continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
17
FN8162.2
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X9119
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
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