Compact Quad Step-Down Regulator with 100% Duty Cycle Operation Withstands 180V Surges Jonathan Paolucci Automotive, industrial and distributed applications routinely subject step-down DC/DC converters to a vast assortment of supply voltage transients. High voltage power spikes and input voltage dips can destroy sensitive circuits and jeopardize system reliability. To avoid damage, most applications rely on Tranzorbs or protection circuits that use MOSFETs as pass elements to suppress input voltage transients. If an N-channel MOSFET is used for this purpose, some means of providing gate drive above the input rail is necessary to bias the MOSFET on. Generating this bias is an undesirable complication that most engineers would prefer to avoid. The LT3504 is a 4-channel monolithic step-down regulator designed for 100% duty cycle operation. Its unique architecture makes available a bias voltage, which is easily adapted to an N-channel protection scheme, allowing the LT3504 to operate continuously through overvoltage transients and dropouts down to 3.2V. Among its many features, the LT3504 includes output voltage tracking and sequencing, programmable frequency, programmable undervoltage lockout, and a power good pin to indicate when all outputs are in regulation. QUAD 1A STEP-DOWN REGULATOR Figure 1 shows the complete application circuit for a 4-output, 1A step-down regulator operating over a 3.2V to 30V range. Q1 provides surge protection to 180V. An on-chip boost regulator generates VSUPPLY 3.2V to 30V SURGE PROTECTION TO 180V 10Ω Q1 R2 100k R3 1k D2 6.8V SKY C1 0.1µF VIN circuits.linear.com/628 C2 22µF DA4 FB4 LT3504 L3 8.2µH DA3 FB3 DA2 FB2 SW1 fSW = 1MHz GND DA1 FB1 10µF 10.2k 31.6k 10µF 10.2k SW2 RT/SYNC 18.2k 53.6k 3.3V/1A D5 43pF L2 4.2µH 0.1µF + 5V/1A D4 22pF SW3 EN/UVLO VIN VIN VIN VIN RUN/SS1 RUN/SS2 RUN/SS3 RUN/SS4 1µF ×4 Figure 1. Complete quad buck regulator with 180V surge protection 26 | April 2013 : LT Journal of Analog Innovation SW4 SW5 L5 10µH C1: Sanyo 50CE22BS D1: BZT52C36-7-F D2: BZT52C6V8-7-F D3: BAT54-7-F D4–D7: ON SEMI MBRM140T3 L3, L4: SUMIDA CDRH5D28-8R2 (8.2µH) L1, L2: CDRH5D28-4R2 (4.2µH) L5: TAIYO YUDEN CBC2016T100M (10µH) Q1: FQB34N20L L4 8.2µH D3 2.2µF D1 36V LTspice IV a voltage rail (VSKY) that is 5V greater than the input voltage VIN . Under normal operating conditions (VIN < 33V), the VSKY rail supplies gate drive to MOSFET Q1, providing the LT3504 with a low resistance path to VSUPPLY. Additionally, the VSKY pin supplies base drive for the switches in each buck converter channel, which allows for 100% duty cycle and 2.5V/1A D6 82pF L1 4.2µH 21.5k 22µF 10.2k 1.8V/1A D7 100pF 12.7k 10.2k 22µF design ideas VIN 50V/DIV SKY 2V/DIV VSUPPLY 50V/DIV VOUT1 1V/DIV VIN 50V/DIV VOUT2 1V/DIV VOUT3 1V/DIV VOUT4 1V/DIV VSUPPLY 2V/DIV VIN 2V/DIV VOUT1,2,3,4 2V/DIV 20ms/DIV 100ms/DIV 100ms/DIV Figure 2. Figure 1’s start-up behavior Figure 3. Figure 1’s dropout performance Figure 4. Overvoltage protection withstands 180V surge eliminates the need for the boost capacitor typically found in buck converters. cycle-by-cycle peak current limiting, as well as catch diode current limit sensing, to protect the part and the external pass device from carrying excessive current during overload conditions. during the transient event is approximately half the peak power. As such, the average power is given by: Bear in mind that significant power dissipation occurs in Q1 during an overvoltage event. The MOSFET junction temperature must be kept below its absolute maximum rating. For the overvoltage transient shown in Figure 4, MOSFET Q1 conducts 0.5A (1A load on all buck channels) while withstanding the voltage difference between VSUPPLY (180V) and VIN (33V). This results in a peak power of 74W. Since the overvoltage pulse in Figure 4 is roughly triangular, average power dissipation In order to approximate the MOSFET junction temperature rise from an overvoltage transient, one must determine the MOSFET transient thermal response as well as the MOSFET power dissipation. Fortunately, most MOSFET transient thermal response curves are provided by the manufacturer (as shown in Figure 5). For a 400ms pulse duration, the FQB34N20L MOSFET thermal response ZθJC (t) is 0.65°C/W. The MOSFET junction temperature rise is given by: OVERVOLTAGE INPUT TRANSIENT PROTECTION FOR MULTIPLE OUTPUTS Figure 4 shows the LT3504 regulating all four channels at 1A load through a 180V surge event without interruption. As the supply voltage rises, Zener diode D1 clamps Q1’s gate voltage to 36V. The source-follower configuration prevents VIN from rising further than about 33V, well below the LT3504’s 40V maximum input voltage rating. The LT3504 uses Figure 5. FQB34N20L MOSFET transient thermal response 1 ZθJC(t), THERMAL RESPONSE (°C/W) Start-up behavior is shown in Figure 2. Resistor R2 pulls up on the gate of Q1, forcing source-connected VIN to follow approximately 3V below VSUPPLY. Once VIN reaches the LT3504’s 3.2V minimum start-up voltage, the on-chip boost converter immediately regulates the VSKY rail 5V above VIN . Diode D3 and resistor R3 bootstrap Q1’s gate to the VSKY, fully enhancing Q1. This connects VIN directly to VSUPPLY through Q1’s low resistance drain-source path. It should be noted that, prior to the presence of VSKY, the minimum input voltage is about 6.2V. However, with VSKY in regulation and Q1 enhanced, the minimum run voltage drops to 3.2V, permitting the LT3504 to maintain regulation through deep input voltage dips. Figure 3 shows all channels operating down to the LT3504’s 3.2V minimum input voltage. 0.1 0.01 10–3 10–5 SINGLE PULSE D = 0.5 D = 0.2 D = 0.1 D = 0.05 D = 0.02 D = 0.01 0.1 1 10–4 10–3 0.01 10 t1, SQUARE WAVE PULSE DURATION (s) PDM t1 t2 ZθJC(t) = 0.7°C/W MAX DUTY FACTOR = D = t1/t2 TJM – TC = PDM • ZθJC(t) PAVG( W) = 1 • PPEAK ( W) = 37 W 2 TRISE (°C) = Z θJC ( t) • PAVG( W) = 24°C Note that, by properly selecting MOSFET Q1, it is possible to withstand even higher input voltage surges. Consult manufacturer data sheets to ensure that the MOSFET operates within its Maximum Safe Operating Area. INDUCTIVE SPIKE PROTECTION Input voltage transients, coupled with low ESR input capacitors, can produce large inductive spikes, which may damage buck converters. These high dV/dt events cause large inrush currents to flow in power connections and filter capacitors, particularly if parasitic inductance and resistance (continued on page 29) April 2013 : LT Journal of Analog Innovation | 27 design ideas The inputs for three of the LDOs are hardwired to the output of the switching regulator, but the input to the remaining bank of two LDOs is undedicated, so it can be connected to the switching regulator or elsewhere. The outputs of the LDOs can be operated separately or paralleled for higher output currents. BIAS-TO-OUTPUT DROPOUT VOLTAGE (V) 1.52 the LTM8001 parallels LDOs to distribute heat and lower operating temperatures. VIN 10V/DIV 1.50 1.48 VOUT0(SUPERCAP) 2V/DIV 1.46 1.44 1.42 VOUT1,2,3(3.3V) 2V/DIV 1.40 1.38 VOUT4,5(2.5V) 2V/DIV 1.36 1.34 0 200 400 800 600 OUTPUT CURRENT (mA) 1000 500ms/DIV Figure 2. LDO VBIAS -to-output dropout voltage vs output current Figure 3. Supercapacitor power backup system holds up the 3.3V output for well over 100ms output current of the LDOs is 1.5A, the holdup time for the 3.3V LDO output is: regard to power dissipation, it maximizes holdup time if the input supply fails. Power loss is minimized by operating the LDO with inputs that just meet, and do not exceed, the bias dropout requirements of the 3.3V LDO. But the supercapacitor voltage must exceed the input power dropout requirement to meet bias dropout and holdup requirements. To mitigate this increased power dissipation, C ∆V I 1.5 0.1 = 1.5 = 100ms 3.3V HOLDUP TIME = Both the LDO bias and LDO input power are connected to 5V from the supercapacitor. Although 5V is non-optimal with Holdup time is longer when the supercapacitor provides bias to the LDOs compared to using a conventional capacitor for that purpose. This avoids detrimental effects of charging a large capacitor directly with the input voltage. Figure 3 shows that the 3.3V output holdup time exceeds 100ms when the supercapacitor is charged to 5V and the LDO outputs are 3.3V at 1A and 2.5V at 0.5A. CONCLUSION The LTM8001 makes it easy to design a multiple output voltage regulator circuit featuring supercapacitor backup power. It is possible to achieve significant holdup time without adding large and undesirable capacitance directly to input power. Visit www.linear.com/LTM8001 for data sheets, demo boards and other applications information. n (LT3504 continued from page 27) is low. External gate network C1 and D2 limits these inrush currents by controlling Q1’s gate voltage slew rate. Since VIN follows Q1’s gate voltage, the external gate network forces VIN to ramp modestly compared to the abrupt input voltage transient present on VSUPPLY, as shown in Figure 6. LT3504. During normal operation, the LT3504’s built-in boost regulator permits 100% switch duty cycle operation and serves as an excellent MOSFET gate driver. The LT3504, along with a MOSFET and gate clamp, provides a transient-robust, compact multioutput solution. CONCLUSION Visit www.linear.com/LT3504 for data sheets, demo boards and other applications information. n The high voltage standoff capability of the series connected MOSFET blocks dangerous spikes from reaching the VSUPPLY 10V/DIV VIN 10V/DIV 40µs/DIV Figure 6. Fast VSUPPLY dV/dt is blocked from VIN by series MOSFET and gate network April 2013 : LT Journal of Analog Innovation | 29