LatticeSC Communications Platform Evaluation Board: LFSC25E-H-EV User's Guide

LatticeSC™ Communications Platform Evaluation Board: LFSC25E-H-EV
User’s Guide
April 2007
Revision: ebug16_01.3
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Introduction
This user’s guide describes the LatticeSC Communications Platform Evaluation Board featuring the LatticeSC 900fpBGA FPGA device. The stand-alone evaluation PCB provides a functional platform for development and rapid
prototyping of applications that incorporate high-performance, source-synchronous interfaces such as SFI-4, XSBI,
SPI-4.2, and DDR2 SDRAM.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR-4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete customer evaluation of the LatticeSC
device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the
LatticeSC FPGA.
Features
• Single Data Rate (SDR) performance for SFI-4.1/XSBI applications via a 300-pin MSA transponder interconnection
• System packet interface level 4-phase 2 (SPI-4.2) via a Molex VHDM interconnection
• DDR2 dual in-line memory module (DIMM) via a 200-pin SODIMM socket supporting 64-bit 200-pin DDR-2
SDRAM
• SERDES high-speed interface SMA test points and clock connections
• Power connections and power sources
• ispVM® programming support
• On-board and external reference clock sources
– Interchangeable clock oscillators
– On-board reference clock management using Lattice ispClock™ devices
• ORCAstra™ demonstration software interface via standard ispVM JTAG connection
• Various high-speed layout structures
• User-defined input and output points
– 24 board programmable switches or LEDs
– 2 defined debounced push-buttons connected to GPIO
• SMA connectors included (10) for high-speed clock or data interfacing
• On-board Flash configuration memory
• Performance monitoring via Agilent logic analyzer connectors and 100-mil test headers
• Flash memory devices for on-board non-volatile configuration storage
• On-board voltage margin testing with multiple voltage regulators Verification and Debug capabilities
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Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 1. LatticeSC Communications Platform Evaluation Board (LFSC25E-H-EV), Top View
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LatticeSC Communications Platform
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Lattice Semiconductor
Figure 2. LatticeSC Communications Platform Evaluation Board Block Diagram
Analog
Power
SERDES
REF
CLKs
VREF
2 SERDES
Quads
SMAs
PLL/DLL
Test
Debug Pins
LEDs
General
I/O
VTT
JTAG
DDR REF
CLK
ORCAstra
LatticeSC
RF
DDR II
Memory
SODIMM
Switches
SSTL
Serial/
Parallel
900 fpBGA
Memory
Power
1.8V
ispVM
Configuration/
FPGA Loader
MSA CTRLS
Status
VCCIO, VCCAUX,
VREF, VIT
300-Pin MSA
XSB I/SFI4
Power Input
1.0/1.2/1.8/
2.5/3.3V
SPI4
REF CLK
SPI4
Interop
MSA REF CLK
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 3 shows the functional partitioning of the board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
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Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 3. LatticeSC Communications Platform Evaluation Board Functional Partitioning
LatticeSC Device
This board features a LFSC25E FPGA with a 1.2V core supply in the 900-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeSC Family Data Sheet on the Lattice web site at www.latticesemi.com.
Note: The connections referenced in this document refer to the LFSC25E device. Available I/Os and associated
PURESPEED™ I/O banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeSC Communications Platform Evaluation Board is delivered ready to power-on. The evaluation system
is shipped with AC line cord for the included multi-voltage power supply. Follow these steps to power-on the board.
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1. Connect the power supply unit to the board using the attached rainbow cable from the power supply to the
power input connector on the board (PWR1).
2. Confirm that the ON-OFF switch, SW1, is in the OFF position. Back towards the Molex input connector.
3. Plug the desktop power supply AC line cord into an electrical outlet supplying the appropriate voltage.
4. Turn on switch on desktop power supply unit. Toggle switch is located on the side of the unit.
5. Turn SW1 to the ON position. The power indicators for all regulator modules should illuminate, indicating output
from the regulators.
Power Supplies
(For schematics, see Appendix A, Figures 7-10)
Many methods can be used to provide power to the board. The board is equipped to accept a main supply via the
PWR1 connection. This connection is provided to use with the switching supply provided with the kit using a Molex
87427-1203 connector.
This power supply sources the needed intermediate power and is used for turnkey evaluations without the need to
control and supply power from other sources. This supply provides intermediate 5V DC and 3.3V DC to the secondary power stages of the PCB. The intermediate supplies can also be sourced from adequately sized benchtop
supplies via banana jacks located near the PWR1 input connector.
Table 1. External Power Supply Input Jack (See Appendix A, Figure 5)
BAN1
Bench Supply for 3.3V Intermediate Supply Input
BAN2
Bench Supply for Intermediate Supply 5.0V Input
BAN3
Ground connection
BAN4
Ground connection
The intermediate supplies are fused on-board with indicating fuses and have green LEDs to indicate power GOOD
status of the intermediate supplies
Table 2. Input Supply Fuses/Indicators (See Appendix A, Figure 5)
F1
5.0VDC Input Indicator Fuse
F2
3.3VDC Input Indicator Fuse
D7
5.0VDC Input Source Good Indicator
D8
3.3VDC Input Source Good Indicator
SW1 is used to enable the off-board switching power supply module as well as discrete power inputs from a benchtop power supply. The intermediate power supplies are supplied to the secondary POL supply modules. These five
independent supplies, U2, U3, U4, U5, and U6, are used to provide the necessary power supplies for the LatticeSC
FPGA and other on-board devices. All five DC/DC outputs are fused on board with indicating fuses and have
GREEN power good indicating LEDs.
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Table 3. Board Power Supply Fuses (See Appendix A, Figure 6)
F3
1.0V/1.2V POL Source Indicator Fuse
F4
1.2V POL Source Indicator Fuse
F5
2.5V POL Source Indicator Fuse
F6
1.5V POL Source Indicator Fuse
F7
3.3V POL Source Indicator Fuse
F8
1.8V POL Source Indicator Fuse
Table 4. Board Power Supply Indicators (See Appendix A, Figure 6)
D1
1.0V/1.2V VCC Core Source Good Indicator
D2
1.5V Source Good Indicator
D3
1.8V Source Good Indicator
D4
2.5V Source Good Indicator
D5
3.3V Source Good Indicator
D6
1.2V Source Good Indicator
External power can be alternatively connected rather than the POL DC/DC modules. Barrier strips can isolate the
supplies allowing for benchtop supplies to source power the secondary rails. Table 5 shows these barrier connections.
Table 5. Board Supply Disconnects (See Appendix A, Figure 6)
BS1
Screw terminal for VCC Core
BS2
Screw terminal for 1.2V source/On Board disconnect
BS3
Screw terminal for 2.5V source/On Board disconnect
BS4
Screw terminal for 1.5V source/On Board disconnect
BS5
Screw terminal for 3.3V source/On Board disconnect
BS6
Screw terminal for 1.8V source/On Board disconnect
The on-board power supplies can be adjusted by trimming potentiometers. The on-board supplies can be margined
up or down from the nominal operating level. The variable resistors are outlined in Table 6.
Table 6. Variable Resistors for Power Supply Margining
Adjust
Supply
R226
R228
R230
R227
R229
CORE
R230
3.3V
1.5V
1.8V
1.2V
2.5V
The board is designed to provide a standard platform as well as a diagnostic platform for device evaluations. The
board is capable of user provisioning that can provide the means to change and re-assign supplies other than the
factory supplied settings. These settings are accomplished by reassignment of two-position jumpers. Two-position
shunts such as AMP/Tyco Electronics part number 881545-2 are used for field PCB provisioning.
The POL DC/DC modules, U2, U3, U4, U5, and U6, include pins to control features of the modules. These DC
modules convert either the 5V DC or 3.3V DC input.
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Table 7. Board Supply Voltage Source Selectors (See Appendix A, Figures 7 and 10)
J23
VCC12 Power Source Select
J25
VCCAUX Power Source Select
J28
VDDAX25 Power Source Select
J29
VDDRX Power Source Select
J30
VDDTX Power Source Select
J31
VDDP Power Source Select
J26
VDDIB Power Source Select
J27
VDDOB Power Source Select
External Power Interface
Power sources can be independently sourced to the board via terminal blocks located on the PCB edge. This interface allows the user to provide power sources from benchtop power supplies. The table below identifies the terminals of the interface.
Table 8. External Power Source Inputs (See Appendix A, Figure 5)
TB2
TB1
1
VDDP
1
VTT RIGHT
2
VDDTX
2
VTT BOTTOM
3
VDDRX
3
VTT LEFT
4
VDDAX25
4
VCCIO18
5
VDDOB
5
VCCIO25
6
VDDIB
6
GND
7
VCCAUX
7
GND
8
VCC12
9
VCC
10
VCCJ
11
GND
12
GND
J10 is used to control the output voltage setting of the U2 DC/DC module. A two-position shunt will connect the
appropriate trim resistor to the module.
Exclusively the LatticeSC device for VCC core supply uses this power source.
Table 9. VCC Core Voltage Select (See Appendix A, Figure 6)
J10
VCC Core DC/DC Module Output/ [1:2]= 1V, [3-2]= 1.2V
VCCIO1 Selection
VCCIO1 is board programmable using the 2X2 0.1 headers. These jumpers select the input for the VCCIO1 voltage.
Table 10. VCCIO1 Bank Voltage Select (See Appendix A, Figure 9)
J32
VCCIO1 Power Source Select (2.5V or 3.3V on-board generated)
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VCCIO18 and VCCIO25
VCCIO to banks 2-7 have predetermined settings and can be supplied from external benchtop supplies by using
the external terminal block. The associated VCCIO source will enter the board via a terminal block TB2 (see
Appendix A, Figure 5).
VCCIO Banks 2, 3, 6 and 7 are planed together on the board and notated as VCCIO25.
Banks 4 and 5 are planed together and notated as VCCIO18.
• VCCIO25 is board connected to a 2.5V supply.
• VCCIO18 is board connected to a 1.8V supply.
VCCAUX
VCCAUX can be board-programmed to connect to a common 2.5V supply. Placing a jumper between on J44 (see
Appendix A, Figure 10) connects all VCCAUX device pins to a board-generated 2.5V supply. A connection to terminal block TB1 (see Appendix A, Figure 5) is available.
VCCJ
The VCCJ supply of the LatticeSC device can be selected via J46 (see Appendix A, Figure 10). J46 is a 2x3
0.1header that can select VCCJ to be 3.3V, 2.5V, or 1.8V using a jumper between the supply voltage and adjacent
pin of J46.
Table 11. VCCJ Supply Selector (See Appendix A, Figure 10)
1
3
5
2
4
6
2
3.3V
4
2.5V
6
1.8V
VTT
On-board voltage regulators are available for generation of VTT supplies for use with SSTL and HSTL I/Os. These
regulators are designed to provide precision voltages for the LatticeSC VTT pins per bank. The regulators can be
shut down according to the following.
Table 12. VTT Generation Source (See Appendix A, Figure 11)
1
3
5
2
4
6
J48
Regulated VTT Right Source (U8) Shutdown
J56
Regulated VTT Left Source (U12) Shutdown
J49
Regulated VTT Bottom Source (U9) Shutdown
3x2-pin headers select the source of the VTT supplies. This selection is between the on-board VTT regulators,
external source, or AC-coupled ground. A jumper between pins 3 and 4 will connect the on-board VTT regulator to
the device, jumper between pins 1 and 2 will connect VTT to an external connection via the terminal block, and an
AC-coupled ground is connected by placing a jumper between pins 3 and 5.
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Table 13. VTT Termination Type (See Appendix A, Figure 11)
J52
VTT Right Selector
J59
VTT Bottom Selector
J50
VTT Left Selector
Programming/FPGA Configuration
Two programming headers are provided on the evaluation board, providing access to the LatticeSC JTAG port. The
standard 1x10 pin header is available for compatibility with all Lattice download cables. The 10-pin 0.100”pitch
header connector which plugs directly into a mating connector provided.
Note: An ispDOWNLOAD® cable is included with this board, and with each ispLEVER® design tool shipment.
Cables may also be purchased separately from Lattice.
ispVM Download Interface
J68 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.
Table 14. ispVM JTAG Connector (See Appendix A, Figure 13)
Pin 1
VCC
Pin 2
TDO
Pin 3
TDI
Pin 4
PROGRAMN
Pin 5
NC
Pin 6
TMS
Pin 7
GND
Pin 8
TCK
Pin 9
DONE
Pin 10
INITN
Download Procedures
Requirements:
• PC with ispVM System v.14.4 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.)
JTAG Download
The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion.
1. Connect the ispDOWNLOAD cable to the appropriate header. J68 is used for the 1x10 cable.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and
render the board inoperable.
2. Connect the LatticeSC Evaluation Board to the appropriate power sources and power up board.
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3. Start the ispVM System software.
4. Press the ‘SCAN’ button located in the toolbar. The LatticeSC device should be automatically detected.
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LatticeSC Communications Platform
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5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse
button located under ‘Data File’. Locate the desired bitstream file (.bit or .rbt). Click OK to both dialog boxes.
The ‘Operation’ should be ‘Fast Program’ and ‘Device Access Options’ set to ‘JTAG 1532 Mode’.
6. Click the green ‘GO’ button. This will begin the download process into the device. Upon successful download,
the device will be operational.
Note: Bitstreams that have been compressed with Bitgen will not download via the JTAG configuration port.
Header Connections
Standard 0.1 headers are provided for interconnecting points on the board. This can be accomplished with 0.100
IDC connectors and ribbon cable for bus connections or 0.025 pin socket patch cords (such as Pomona Electronics
#5948 www.pomonelectronics.com). Most connections can be made using two-pin shunts provided with the board
kits.
Configuration Status Indicators
(see Appendix A, Figure 13)
These LEDs indicate the status of configuration to the FPGA.
• D9 (RED) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output
low.
• D10 (GREEN) is illuminated, this indicates the successful completion of configuration by releasing the open collector DONE output pin.
• D13 (GREEN) will flash indicating TDI activity.
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PROGRAMN and RESETN
(see Appendix A, Figure 13)
These push button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and RESETN (SW2).
Depressing the button drives a logic level “0” to the device.
MODE [3:0]
(see Appendix A, Figure 13)
The FPGA MODE pins can be selected via the SW6 DIP-switch. These settings must be selected accordingly for
the particular configuration mode. However for ispVM downloading via the download cable, the settings of these
pins are required.
FPGA Loader Interface
(see Appendix A, Figure 13)
A 2x17 header is provided to connect the LatticeSC to the Serial Configuration Module (SCM) or Parallel Configuration Module (PCM). These modules are available from Lattice and are utilized to verify the parallel and serial
loading of the configuration memory.
On-Board Flash Memory
(see Appendix A, Figure 13)
Two memory devices (U25 and U26) are on-board for non-volatile configuration memory storage. SW20 is used to
control writing and reading from the memory. When used to configure the board, the user must set the MODE[3:0]
pins accordingly [0101] with SW6. Refer to Lattice technical note number TN1100, SPI Serial Flash Programming
Using ispJTAG on LatticeSC FPGAs for recommended procedures and software usage.
To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individually. This is accomplished by setting SW20 accordingly. Writing to Flash #1(U26), close 3 and 5 switch positions
(ON) and open all others.
Writing to Flash #2(U25), close 2 and 4 switch positions (ON) and open all others.
For reading from the Flash devices individually, use the same switch settings and described for writing.
For reading from both Flash devices in cascading format, close switch positions (1, 3, 4, 5, 8).
FPGA Clock Management
(see Appendix A, Figure 14)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated either from input provided from SMAs (see table below) or from crystal oscillators (Y1 and Y2), which are
socketed. Both of these input clock sources are routed through the Lattice ispClock5620 programmable clock manager devices (U19 and U20). These clock management devices allow for clock synthesis and buffering.
Table 15. External ispCLOCK5620 Reference Clock Input Connections
J91
U19 Reference + Input
J92
U19 Reference - Input
J93
U20 Reference + Input
J95
U20 Reference - Input
U19 and U20 are Lattice ispClock5620 In-System-Programmable Analog Circuit allows designers to implement
clock distribution networks supporting multiple, synchronized output frequencies using a single integrated circuit.
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By integrating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620 can derive up to
five separate output frequencies from a single input reference frequency. PAC-Designer® software (available from
the Lattice web site at www.latticesemi.com) is used to program the ispClock features.
The ispClock5620 supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source
need not be 50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25ns or
longer. The following standards are supported with either minimal or no external components: LVTTL / LVCMOS /
SSTL2 / SSTL3 / HSTL / LVDS / LVPECL.
When the ispClock5620 is in a LOCKED state, the LOCK output pin goes LOW. The LOCKN pins are connected to
amber LEDs, D14 and D15, that will illuminate when the LOCKN pin goes low. The lock detector has two operating
modes; phase lock mode and frequency lock mode. In phase lock mode, the LOCK signal is asserted if the phases
of the reference and feedback signals match. In frequency lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals match.
Table 16. ispClock Lock Indicators (See Appendix A, Figure 14)
D14
CLK5560 #1(U19) PLL Lock Indicator- Locked when Lit
D15
CLK5560 #2 (U20) PLL Lock Indicator- Locked when Lit
U19 and U20 are controlled by SW8 and SW7 respectively. These DIP switches control the ispClock devices. The
reference clock selection and device reset is controlled using the switches. The switches controlling the ispClock
outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tri-stated on an outputby-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the GOEb input high.
The VCCO voltage is board connected to 2.5V.
J98 is provided to allow reprogramming of the ispClock devices. Both devices are in the same JTAG chain. Please
refer to the ispClock documentation for altering the designs. The output clocks, U19 and U20, are routed to devices
to provide system level clocking. These pre-defined board clocks are routed to input LatticeSC input clock pins for
SERDES reference clocks, primary clocks, PLL inputs and DLL inputs as well as connection to the external MSA
(MSA1) transponder site. There are also two output pairs available via 50-ohm terminated SMA connections for offboard interconnections.
Table 17. ispClock Output SMA Connections (See Appendix A, Figure 14)
J90
U19 Reference + Output
J94
U19 Reference - Output
J96
U20 Reference + Output
J97
U20 Reference - Output
SERDES
SERDES Reference Clock
J128/J129 are provided to allow a DC-coupled reference clocks from an external clock generator. This reference
clock is for the Quad PCS 3E0.
J134/137 are available for the same Quad to provide a separate Rx Clock.
For Quad PCS 360, this reference clock is sourced from the ispClock device.
The following 50-ohm terminated SMA connectors are provided the supply reference clocks directly to the LatticeSC device.
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Table 18. SERDES Reference Clock Input Connectors (See Appendix A, Figure 15)
J128
A_REFCLKN_R
J129
A_REFCLKP_R
SERDES Channels
DC coupled SMA connectors connect to the SERDES Tx and Rx channels of both the Quad A SERDES on the left
and right device sides. These pins are directly coupled to the designated SMA connector creating a path for both
input and output differential data.
Table 19. SERDES Connectors (See Appendix A, Figure 15)
J105
A_HDINN0_L
J120
A_HDINN0_R
J103
A_HDINP0_L
J118
A_HDINP0_R
J108
A_HDINN1_L
J124
A_HDINN1_R
J106
A_HDINP1_L
J122
A_HDINP1_R
J112
A_HDINN2_L
J130
A_HDINN2_R
J110
A_HDINP2_L
J126
A_HDINP2_R
J116
A_HDINN3_L
J135
A_HDINN3_R
J114
A_HDINP3_L
J132
A_HDINP3_R
J102
A_HDOUTN0_L
J121
A_HDOUTN0_R
J104
A_HDOUTP0_L
J119
A_HDOUTP0_R
J109
A_HDOUTN1_L
J125
A_HDOUTN1_R
J107
A_HDOUTP1_L
J123
A_HDOUTP1_R
J113
A_HDOUTN2_L
J131
A_HDOUTN2_R
J111
A_HDOUTP2_L
J127
A_HDOUTP2_R
J117
A_HDOUTN3_L
J136
A_HDOUTN3_R
J115
A_HDOUTP3_L
J133
A_HDOUTP3_R
Note: For accurate electrical analysis of SERDES transmit outputs, it is recommended to terminate the unused output SMAs with 50-ohm terminations.
Multi-Chip Alignment
(see Appendix A, Figure 15)
ZP1 connector interconnects test points for multi-chip alignment pins. It is not populated for general use. This connector type is an Amp Z-Pack 2mm header. A cable similar to one from W.L Gore (www.wlgore.com) P/N
2MMA3192-01 adapts the 2mm Z-Pack to individual SMA connectors and is useful to observe signals or connect to
other test devices
FPGA Test Pins
(see Appendix A, Figure 21)
General-purpose FPGA pins are available via a 36 x 3 pin header. The use of this header connects FPGA pins to
either a Switch or LED based on the user’s requirement by placing a jumper across the appropriate pins of J152.
The switch nets are tied to 4-position DIP switches designated according to the following table.
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Table 20. FPGA Test Selector Header (See Appendix A, Figure 21)
Switch
Pin
Netname
Pin
BGA
Pin
NetName
LED
SW19D
1
Switch1
2
AK15
3
RED1
D35
SW19C
4
Switch2
5
AJ28
6
RED2
D36
SW19B
7
Switch3
8
AH28
9
RED3
D37
SW19A
10
Switch4
11
AE25
12
RED4
D38
SW18D
13
Switch5
14
AE26
15
RED5
D39
SW18C
16
Switch6
17
AD25
18
YELLOW1
D40
SW18B
19
Switch7
20
H26
21
YELLOW2
D41
SW18A
22
Switch8
23
G26
24
YELLOW3
D42
SW17D
25
Switch9
26
L25
27
YELLOW4
D43
SW17C
28
Switch10
29
L26
30
YELLOW5
D44
SW17B
31
Switch11
32
J28
33
GREEN1
D45
SW17A
34
Switch12
35
H28
36
GREEN2
D46
SW16D
37
Switch13
38
P27
39
GREEN3
D47
SW16C
40
Switch14
41
L29
42
GREEN4
D48
SW16B
43
Switch15
44
M30
45
GREEN5
D49
SW16A
46
Switch16
47
U26
48
BLUE1
D50
SW15D
49
Switch17
50
T24
51
BLUE2
D51
SW15C
52
Switch18
53
AB27
54
BLUE3
D52
SW15B
55
Switch19
56
H14
57
BLUE4
D53
SW15A
58
Switch20
59
AB5
60
BLUE5
D54
SW14D
61
Switch21
62
W5
63
ORANGE1
D55
SW14C
64
Switch22
65
AK28
66
ORANGE2
D56
SW14B
67
Switch23
68
AF24
69
ORANGE3
D57
SW14A
70
Switch24
71
AG24
72
ORANGE4
D58
FPGA Pin
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
Switch
LED
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
Test SMA Connections
General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit
evaluations of several types of FPGA I/O buffers. The use of several termination schemes permit easy interfaces for
the type of buffer.
16
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Lattice Semiconductor
Table 21. FPGA I/O Test SMA Connectors (See Appendix A, Figure 21)
SMA
Designation
Name
Signal
900-BGA
Termination
Description
Termination
Resistor(s)
J154
LVDS_INP
PR27C/PCLKT2_2
P26
DC-Coupled
n/a
J153
LVDS_INN
PR27D/PCLKC2_2
N27
DC-Coupled
n/a
J182
LVDS_OUTP
PR57A/LRC_DLLT_IN
AF29
100-ohm Differential Termination
R205
J181
LVDS_OUTN
PR57B/LRC_DLLC_IN
AF28
100-ohm Differential Termination
R205
J161
LRC_PLLC PB69B/LRC_PLLC_IN_A
AH30
50-ohm Ground Termination
R215
J163
LRC_PLLT
PB69A/LRC_PLLT_IN_A
AJ30
50-ohm Ground Termination
R214
J162
LRC_DLLC PB68B/LRC_DLLC_IN_C
AH29
50-ohm Ground Termination
R217
J164
LRC_DLLT
PB68A/LRC_DLLT_IN_C
AJ29
50-ohm Ground Termination
R216
J166
50_OHM_1
PB61B
AH27
50-ohm VTT/GND
R222/R219
J165
50_OHM_2
PB61A
AH26
50-ohm VTT/GND
R223/R218
J168
50_OHM_3
PB60C
AE22
50-ohm VTT/GND
R224/R221
J167
50_OHM_4
PB60B
AK29
50-ohm VTT/GND
R225/R220
LSR and LSRN
(see Appendix A, Figure 13)
These push button switches assert/de-assert the logic levels on the LSR (SW5) and LSRN (SW4).
Depressing the LSRN (SW4) drives a logic level “0” to the device.
Depressing the LSR (SW5) drives a logic level “1” to the device.
300-pin MSA Transponder Interface
(see Appendix A, Figure 16)
MSA1 connector provides an interface for interoperability to 300-pin SFI4.2 or XSBI transponders. The interface is
complete with high-speed parallel connections to the LatticeSC device as well as clocking, status, control, and
power. The interface pin-out is outlined in the table below.
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Lattice Semiconductor
Table 22. SFI-XSBI 300-Pin Connector Standard (See Appendix A, Figure 16)
Receiver
K
J
H
5.0V Analog
RxTRACE
Frame GND
5.0V Analog
FFU
RxRATESEL0
RxRATESEL1
3.3V Analog
3.3V Analog
G
F
E
D
RxDout12P
APS Digital
RxDout8P
Digital GND
Frame GND
RxDout12N
APS Digital
RxDout8N
APDTEMPMON
Digital GND
RxPOWMON
Digital GND
NUC
Frame GND
RxDout13P
3.3V Digital
NUC
Frame GND
RxDout13N
3.3V Digital
RxRESET
NUC
DLOOPENB
Digital GND
3.3V Analog
FFU
Analog GND
3.3V Analog
FFU
Analog GND
RxMUTEPOCLK NUC
-5.2V Analog
-5.2V Analog
C
B
A
RxDout4P
Digital GND
RxDout0P
Digital GND
RxDout4N
Digital GND
RxDout0N
I2CAD0
Digital GND
RxDTV
Digital GND
RxDout9P
Digital GND
RxDout5P
Digital GND
RxDout1P
RxDout9N
Digital GND
RxDout5N
Digital GND
RxDout1N
RxPOWALM
Digital GND
I2CAD1
Digital GND
RxMUTEDout
Digital GND
RxDout14P
3.3V Digital
RxDout10P
Digital GND
RxDout6P
Digital GND
RxDout2P
RxDout14N
3.3V Digital
RxDout10N
Digital GND
RxDout6N
Digital GND
RxDout2N
FFU
Digital GND
RxSIGMON
Digital GND
I2CAD2
Digital GND
RxLCKREF
Digital GND
APS Sense
Analog GND
RxDout15P
-5.2V Digital
RxDout11P
Digital GND
RxDout7P
Digital GND
RxDout3P
APS Set
Analog GND
RxDout15N
-5.2V Digital
RxDout11N
Digital GND
RxDout7N
Digital GND
RxDout3N
RXMUTEMCLK
NUC
FFU
Digital GND
RxSIGALM
Digital GND
MOD_RESET
Digital GND
RxMCLKSEL
Digital GND
-5.2V Analog
FFU
Analog GND
FFU
-5.2V Digital
RxPOCLKP
Digital GND
RxMCLKP
Digital GND
RxREFCLKP
-5.2V Analog
RxALM INT
Analog GND
FFU
-5.2V Digital
RxPOCLKN
Digital GND
RxMCLKN
Digital GND
RxREFCLKN
I2CCLOCK
NUC
ALM INT
Digital GND
RxREFSEL
Digital GND
FFU
Digital GND
RxLOCKERR
Digital GND
Receiver power and GND supplies
Receiver DC signals
622 differential signals
NUC = No user connection
FFU = Reserved for future use
Italics = Optional feature
Transmitter
K
J
H
5.0V Analog
TxALM INT
Analog GND
5.0V Analog
FFU
I2CDATA
NUC
3.3V Analog
3.3V Analog
G
F
E
D
TxDin12P
APS Digital
TxDin8P
Digital GND
Analog GND
TxDin12N
APS Digital
TxDin8N
LsTUNE0
Digital GND
LsBIASMON
Digital GND
ModBIASMON
Analog GND
TxDin13P
3.3V Digital
ModBIASALM
Analog GND
TxDin13N
3.3V Digital
TxRATESEL0
TxRATESEL1
LsTUNE1
Digital GND
3.3V Analog
FFU
Analog GND
3.3V Analog
FFU
Analog GND
TxRESET
NUC
-5.2V Analog
-5.2V Analog
C
B
A
TxDin4P
Digital GND
Digital GND
TxDin4N
Digital GND
TxDin0N
LsPOWMON
Digital GND
TxSKEWSEL0
Digital GND
TxDin9P
Digital GND
TxDin5P
Digital GND
TxDin1P
TxDin9N
Digital GND
TxDin5N
Digital GND
TxDin1N
LsENABLE
Digital GND
LsTEMPMON
Digital GND
TxSKEWSEL1
Digital GND
TxDin14P
3.3V Digital
TxDin10P
Digital GND
TxDin6P
Digital GND
TxDin2P
TxDin14N
3.3V Digital
TxDin10N
Digital GND
TxDin6N
Digital GND
TxDin2N
LsTUNE2
Digital GND
LsBIASALM
Digital GND
TxPHSAD30
Digital GND
LsTWEAK
Digital GND
NUC
Frame GND
TxDin15P
-5.2V Digital
TxDin11P
Digital GND
TxDin7P
Digital GND
TxDin3P
NUC
Frame GND
TxDin15N
-5.2V Digital
TxDin11N
Digital GND
TxDin7N
Digital GND
TxDin3N
TxFIFO RES
NUC
LLOOPENB
Digital GND
LsTEMPALM
Digital GND
TxPHSAD31
Digital GND
TxPICLKSEL
Digital GND
-5.2V Analog
LsWAVEMON
Frame GND
TxPICLKP
-5.2V Digital
TxPCLKP
Digital GND
TxMCLKP
Digital GND
TxREFCLKP
-5.2V Analog
TxTRACE
Frame GND
TxPICLKN
-5.2V Digital
TxPCLKN
Digital GND
TxMCLKN
Digital GND
TxREFCLKN
TxFIFO ERR
NUC
TxLINETIMSEL
Digital GND
TxREFSEL
Digital GND
LsPOWALM
Digital GND
TxLOCKERR
Digital GND
Transmitter power and GND supplies
Transmitter DC signals
622 differential signals
NUC = No user connection
FFU = Reserved for future use
Italics = Optional feature
18
TxDin0P
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
Table 23 outlines the physical connections between the 300-pin MSA connector and the LatticeSC device.
Table 23. SFI4/XSBI Interface Pinout (See Appendix A, Figure 16)
LatticeSC
To XPNDR
MSA
LatticeSC
FROM XPNDR
MSA
D29
MSA_TX_P_00
A16
R27
MSA_RX_P_00
A1
D30
MSA_TX_N_00
A17
T27
MSA_RX_N_00
A2
G28
MSA_TX_P_01
A19
V28
MSA_RX_P_01
A4
F28
MSA_TX_N_01
A20
W28
MSA_RX_N_01
A5
G27
MSA_TX_P_02
A22
T30
MSA_RX_P_02
A7
H27
MSA_TX_N_02
A23
U30
MSA_RX_N_02
A8
L27
MSA_TX_P_03
A25
V26
MSA_RX_P_03
A10
M27
MSA_TX_N_03
A26
W26
MSA_RX_N_03
A11
E29
MSA_TX_P_04
C16
V29
MSA_RX_P_04
C1
E30
MSA_TX_N_04
C17
W29
MSA_RX_N_04
C2
F29
MSA_TX_P_05
C19
V30
MSA_RX_P_05
C4
G29
MSA_TX_N_05
C20
W30
MSA_RX_N_05
C5
H30
MSA_TX_P_06
C22
Y27
MSA_RX_P_06
C7
J30
MSA_TX_N_06
C23
W27
MSA_RX_N_06
C8
K30
MSA_TX_P_07
C25
Y30
MSA_RX_P_07
C10
L30
MSA_TX_N_07
C26
AA30
MSA_RX_N_07
C11
P28
MSA_TX_P_08
E16
AA25
MSA_RX_P_08
E1
R28
MSA_TX_N_08
E17
AB25
MSA_RX_N_08
E2
N28
MSA_TX_P_09
E19
AD30
MSA_RX_P_09
E4
N29
MSA_TX_N_09
E20
AE30
MSA_RX_N_09
E5
P29
MSA_TX_P_10
E22
AB28
MSA_RX_P_10
E7
R29
MSA_TX_N_10
E23
AC28
MSA_RX_N_10
E8
T28
MSA_TX_P_11
E25
AD29
MSA_RX_P_11
E10
U28
MSA_TX_N_11
E26
AE29
MSA_RX_N_11
E11
M29
MSA_TX_P_12
G17
AF30
MSA_RX_P_12
G1
N30
MSA_TX_N_12
G16
AG30
MSA_RX_N_12
G2
T29
MSA_TX_P_13
G19
AB26
MSA_RX_P_13
G4
U29
MSA_TX_N_13
G20
AC26
MSA_RX_N_13
G5
P30
MSA_TX_P_14
G22
AC27
MSA_RX_P_14
G7
R30
MSA_TX_N_14
G23
AD28
MSA_RX_N_14
G8
U27
MSA_TX_P_15
G25
AD26
MSA_RX_P_15
G10
V27
MSA_TX_N_15
G26
AC25
MSA_RX_N_15
G11
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LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
MSA Power Supplies
(See Appendix A, Figure 17)
Table 24. MSA Power Indicators (See Appendix A, Figure 17)
D34
MSA +1.8VDC Auxiliary Supply Good Indicator
D30
MSA +3.3VDC Analog Supply Good Indicator
D31
MSA +3.3VDC Digital Supply Good Indicator
D29
MSA +5VDC Analog Supply Good Indicator
D32
MSA -5VDC Analog Supply Good Indicator
D33
MSA -5VDC Digital Supply Good Indicator
J141 is a 3x6-pin header is board programmed using jumpers. The header selects between use of on-board regulated power supplies or connections to terminal block TB4 for connection to external supplies for supplying the 300pin module.
MSA Status Indicators
The status signals of the MSA interface are observed via the LED indicators listed below
Table 25. MSA Status Indicators (See Appendix A, Figure 16)
D17
MSA ALM_INT Indicator- Error when lit
D24
MSA LSBIASALM Indicator- Error when lit
D22
MSA LSPOWALM Indicator- Error when lit
D23
MSA LSTEMPALM Indicator- Error when lit
D21
MSA MODBIAS_ALM Indicator- Error when lit
D19
MSA RXALM_INT Indicator- Error when lit
D26
MSA RXLOCKERR Indicator- RX PLL Locked when lit
D20
MSA RXPOWALM Indicator- Error when lit
D16
MSA RXSIGALM Indicator- Error when lit
D18
MSA TXALM_INT Indicator- Error when lit
D25
MSA TXFIFOERR Indicator- Error when lit
D27
MSA TXLOCKERR Indicator- TX PLL Locked when lit
J139 and J140 provide connections to analog MSA outputs and undetermined use pins respectively.
SW10 and SW12 are push-button switches used to drive the MSA RXRESET and TXRESET pins to logic “0” when
depressed.
MSA Input Switches
The 300-pin MSA pin out standard includes logical inputs to various transponder implementations. The evaluation
board is equipped with DIP switches that are connected to the MSA pins for the users to setup their particular transponder. Table 26 outlines the switch and signal.
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Lattice Semiconductor
Table 26. MSA Static input switches (See Appendix A, Figure 16)
Switch
Position
Signal
9
1
MOD-RESET
9
2
I2CAD2
9
3
I2CAD1
9
4
I2CAD0
9
5
TXPICLKSEL
9
6
TXSKEWSEL1
9
7
TXSKEWSEL0
9
8
RXMCLKSEL
9
9
RXLCKREF
9
10
RXMUTEDOUT
11
1
LSENABLE
11
2
RXREFSEL
11
3
DLOOPENB
11
4
LSTUNE0
11
5
LSTUNE1
11
6
LSTUNE2
11
7
LLOOPENB
11
8
TXLINETIMSEL
11
9
TXPHSADJ1
11
10
TXPHSADJ0
13
1
nc
13
2
nc
13
3
TXFIFO_RES
13
4
RXMUTEMCLK
13
5
RXMUTEPOCLK
13
6
TXRATESEL0
13
7
TXRATESEL1
13
8
RXRATESEL0
13
9
RXRATESEL1
13
10
TXREFSEL
SFI/XSBI Interface Voltage References
The SFI/XSBI I/O interface requires a voltage reference for proper operation. This voltage reference is VCCAUX/2
typical. This reference is sourced from a regulator (Appendix A, U8 schematic, Figure 11) or can be trimmed by the
user with potentiometers (Appendix A, R146/R148 schematic, Figure 16). J138 is used to select the source of the
voltage reference.
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LatticeSC Communications Platform
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Lattice Semiconductor
SPI4.2/PL-4 Interface Support
Provided for SPI 4.2 interfaces are two active 6x10 backplane connectors. MOLEX-VHDM-74057-002 connectors
are used to provide off-board connections to SPI4.2 devices. Connector VHDM1 includes necessary data pairs and
control signals for transmit data from a PHY to the LatticeSC, while VHDM2 has been configured for receive data
from the PHY to the LatticeSC device.
The SPI4.2 Interface is also visible via high-speed Agilent Logic Analyzer connections (P/N ASP65067-01). The
table below references the appropriate signal and connector.
Table 27. SPI4.2 Test Interface (See Appendix A, Figure 20)
SPI4 NET
Logic Analyzer
LA Pin
LA Signal
SPI4 Test
Connector
SPI4 Pin
LatticeSC BGA
TDAT_P0
ASP1
8
D0P
VHDM1
A1
J6
TDAT_P14
ASP1
64
D14P
VHDM1
A10
Y5
TDAT_P2
ASP1
16
D2P
VHDM1
A2
K5
TDAT_P4
ASP1
24
D4P
VHDM1
A3
L5
TDAT_P6
ASP1
32
D6P
VHDM1
A4
T3
TDAT_P8
ASP1
40
D8P
VHDM1
A7
U3
TDAT_P10
ASP1
48
D10P
VHDM1
A8
V1
TDAT_P12
ASP1
56
D12P
VHDM1
A9
Y1
TDAT_N0
ASP1
7
D0N
VHDM1
B1
J5
TDAT_N14
ASP1
63
D14N
VHDM1
B10
Y6
TDAT_N2
ASP1
15
D2N
VHDM1
B2
K6
TDAT_N4
ASP1
23
D4N
VHDM1
B3
M5
TDAT_N6
ASP1
31
D6N
VHDM1
B4
R3
TDAT_N8
ASP1
39
D8N
VHDM1
B7
V3
TDAT_N10
ASP1
47
D10N
VHDM1
B8
W1
TDAT_N12
ASP1
55
D12N
VHDM1
B9
AA1
TCTL_P
ASP3
56
D12P
VHDM1
C10
AC3
TSCLK_P
ASP3
80
D16P/CLKP
VHDM1
C5
AF2
TSTAT0_P
ASP3
28
D5P
VHDM1
C6
AC4
TCTL_N
ASP3
55
D12N
VHDM1
D10
AD3
TSTAT1_P
ASP3
36
D7P
VHDM1
D6
AF1
TDAT_P1
ASP1
12
D1P
VHDM1
E1
K4
TDAT_P15
ASP1
68
D15P
VHDM1
E10
AD2
TDAT_P3
ASP1
20
D3P
VHDM1
E2
E1
TDAT_P5
ASP1
28
D5P
VHDM1
E3
R7
TDAT_P7
ASP1
36
D7P
VHDM1
E4
R5
TDCLK_P
ASP1
80
D16P/CLKP
VHDM1
E5
P8
TDAT_P9
ASP1
44
D9P
VHDM1
E7
T5
TDAT_P11
ASP1
52
D11P
VHDM1
E8
V5
TDAT_P13
ASP1
60
D13P
VHDM1
E9
Y3
TDAT_N1
ASP1
11
D1N
VHDM1
F1
J4
TDAT_N15
ASP1
67
D15N
VHDM1
F10
AE2
TDAT_N3
ASP1
19
D3N
VHDM1
F2
D1
TDAT_N5
ASP1
27
D5N
VHDM1
F3
R6
TDAT_N7
ASP1
35
D7N
VHDM1
F4
R4
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LatticeSC Communications Platform
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Lattice Semiconductor
Table 27. SPI4.2 Test Interface (See Appendix A, Figure 20) (Continued)
SPI4 Test
Connector
SPI4 NET
Logic Analyzer
LA Pin
LA Signal
SPI4 Pin
LatticeSC BGA
TDCLK_N
ASP1
79
D16N/CLKN
TDAT_N9
ASP1
43
D9N
VHDM1
F5
R8
VHDM1
F7
T4
TDAT_N11
ASP1
51
D11N
VHDM1
F8
V4
TDAT_N13
ASP1
59
D13N
VHDM1
F9
W3
RDAT_P14
ASP2
64
D14P
VHDM2
A1
V2
RDAT_P0
ASP2
8
D0P
VHDM2
A10
D3
RDAT_P12
ASP2
56
D12P
VHDM2
A2
T1
RDAT_P10
ASP2
48
D10P
VHDM2
A3
P1
RDAT_P8
ASP2
40
D8P
VHDM2
A4
N3
RDAT_P6
ASP2
32
D6P
VHDM2
A7
J1
RDAT_P4
ASP2
24
D4P
VHDM2
A8
K3
RDAT_P2
ASP2
16
D2P
VHDM2
A9
F3
RDAT_N14
ASP2
63
D14N
VHDM2
B1
W2
RDAT_N0
ASP2
7
D0N
VHDM2
B10
D2
RDAT_N12
ASP2
55
D12N
VHDM2
B2
U1
RDAT_N10
ASP2
47
D10N
VHDM2
B3
R1
RDAT_N8
ASP2
39
D8N
VHDM2
B4
P3
RDAT_N6
ASP2
31
D6N
VHDM2
B7
K1
RDAT_N4
ASP2
23
D4N
VHDM2
B8
L3
RDAT_N2
ASP2
15
D2N
VHDM2
B9
G3
RCTL_P
ASP3
48
D10P
VHDM2
C1
AB1
RSTAT0_P
ASP3
12
D1P
VHDM2
C5
AB6
RSCLK_P
ASP3
68
D15P
VHDM2
C6
AC6
RCTL_N
ASP3
47
D10N
VHDM2
D1
AC1
RSTAT1_P
ASP3
16
D2P
VHDM2
D5
AE3
RDAT_P15
ASP2
68
D15P
VHDM2
E1
Y2
RDAT_P1
ASP2
12
D1P
VHDM2
E10
E3
RDAT_P13
ASP2
60
D13P
VHDM2
E2
U4
RDAT_P11
ASP2
52
D11P
VHDM2
E3
T2
RDAT_P9
ASP2
44
D9P
VHDM2
E4
P2
RDCLK_P
ASP2
80
D16P/CLKP
VHDM2
E6
L1
RDAT_P7
ASP2
36
D7P
VHDM2
E7
N2
RDAT_P5
ASP2
28
D5P
VHDM2
E8
F2
RDAT_P3
ASP2
20
D3P
VHDM2
E9
G2
RDAT_N15
ASP2
67
D15N
VHDM2
F1
AA2
RDAT_N1
ASP2
11
D1N
VHDM2
F10
E2
RDAT_N13
ASP2
59
D13N
VHDM2
F2
U5
RDAT_N11
ASP2
51
D11N
VHDM2
F3
U2
RDAT_N9
ASP2
43
D9N
VHDM2
F4
R2
RDCLK_N
ASP2
79
D16N/CLKN
VHDM2
F6
M1
RDAT_N7
ASP2
35
D7N
VHDM2
F7
N1
RDAT_N5
ASP2
27
D5N
VHDM2
F8
F1
RDAT_N3
ASP2
19
D3N
VHDM2
F9
G1
23
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
SPI4.2 Interface Voltage References
The SPI4.2 I/O interface requires a voltage reference for proper operation. This voltage reference is VCCAUX/2
typical. This reference is sourced from a regulator (Appendix A, U9 schematic, Figure 11) or can be trimmed by the
user with potentiometers (Appendix A, R196/R201 schematic, Figure 20). J149 is used to select the source of the
voltage reference.
DDR2 Interface Support
The LatticeSC Evaluation Board is equipped to be interconnected to DDR2 SDRAM memory modules. The DDR2
memory interface includes a 64-bit wide DIMM connection to one 200-pin DDR2 SODIMM socket. The evaluation
board includes termination of address, command, and control lines to the DIMM.
For the SODIMM data-path, the data bytes are spread across multiple banks of the FPGA device. The board
includes all power and external components needed to demonstrate the memory controller of the LatticeSC device
Table 28. DDR2 Memory SODIMM Module Interface (See Appendix A, Figure 18)
DDR2 Net
900-fpBGA Ball
5S25 Site
SODIMM Pin
SODIMM Signal
MEMINTF_A0
AG3
PB4A
102
A0
MEMINTF_A1
AH2
PB4B
101
A1
MEMINTF_A2
AD6
PB4C
100
A2
MEMINTF_A3
AJ2
PB5A
99
A3
MEMINTF_A4
AK2
PB5B
98
A4
MEMINTF_A5
AD7
PB5C
97
A5
MEMINTF_A6
AD8
PB5D
94
A6
MEMINTF_A7
AF7
PB7A
92
A7
MEMINTF_A8
AF6
PB7B
93
A8
MEMINTF_A9
AH4
PB8A
91
A9
MEMINTF_BA0
AF9
PB11C
107
BA0
MEMINTF_BA1
AE10
PB11D
106
BA1
MEMINTF_DM0
AK3
PB12A
10
DM0
MEMINTF_DM1
AK5
PB16B
26
DM1
MEMINTF_DM2
AJ12
PB23B
52
DM2
MEMINTF_DM3
AH12
PB31A
67
DM3
MEMINTF_DM4
AK16
PB37A
130
DM4
MEMINTF_DM5
AK19
PB41B
147
DM5
MEMINTF_DM6
AJ21
PB49B
170
DM6
MEMINTF_DM7
AG21
PB55A
185
DM7
MEMINTF_DQ0
AJ4
PB12B
5
DQ0
MEMINTF_DQ1
AE11
PB13A
7
DQ1
MEMINTF_DQ2
AF10
PB13B
17
DQ2
MEMINTF_DQ3
AH7
PB15A
19
DQ3
MEMINTF_DQ4
AH8
PB15B
4
DQ4
MEMINTF_DQ5
AE12
PB15C
6
DQ5
MEMINTF_DQ6
AE13
PB15D
14
DQ6
MEMINTF_DQ7
AK4
PB16A
16
DQ7
MEMINTF_DQ8
AJ5
PB17A
23
DQ8
MEMINTF_DQ9
AJ6
PB17B
25
DQ9
MEMINTF_DQ10
AJ7
PB19A
35
DQ10
MEMINTF_DQ11
AJ8
PB19B
37
DQ11
24
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
Table 28. DDR2 Memory SODIMM Module Interface (See Appendix A, Figure 18) (Continued)
DDR2 Net
900-fpBGA Ball
5S25 Site
SODIMM Pin
SODIMM Signal
MEMINTF_DQ12
AH11
PB20B
20
DQ12
MEMINTF_DQ13
AE14
PB20D
22
DQ13
MEMINTF_DQ14
AF14
PB21C
36
DQ14
MEMINTF_DQ15
AF15
PB21D
38
DQ15
MEMINTF_DQ16
AG13
PB23C
43
DQ16
MEMINTF_DQ17
AK9
PB24B
45
DQ17
MEMINTF_DQ18
AH14
PB25A
55
DQ18
MEMINTF_DQ19
AG14
PB25B
57
DQ19
MEMINTF_DQ20
AK10
PB28A
44
DQ20
MEMINTF_DQ21
AK11
PB28B
46
DQ21
MEMINTF_DQ22
AH15
PB29A
56
DQ22
MEMINTF_DQ23
AG15
PB29B
58
DQ23
MEMINTF_DQ24
AJ13
PB31B
61
DQ24
MEMINTF_DQ25
AD15
PB31C
63
DQ25
MEMINTF_DQ26
AE15
PB31D
73
DQ26
MEMINTF_DQ27
AK12
PB32A
75
DQ27
MEMINTF_DQ28
AK13
PB32B
62
DQ28
MEMINTF_DQ29
AJ14
PB33A
64
DQ29
MEMINTF_DQ30
AJ15
PB33B
74
DQ30
MEMINTF_DQ31
AK14
PB35A
76
DQ31
MEMINTF_DQ32
AK17
PB37B
123
DQ32
MEMINTF_DQ33
AJ16
PB38A
125
DQ33
MEMINTF_DQ34
AJ17
PB38B
135
DQ34
MEMINTF_DQ35
AE16
PB38C
137
DQ35
MEMINTF_DQ36
AH16
PB39A
124
DQ36
MEMINTF_DQ37
AG16
PB39B
126
DQ37
MEMINTF_DQ38
AF16
PB38D
134
DQ38
MEMINTF_DQ39
AK18
PB41A
136
DQ39
MEMINTF_DQ40
AH17
PB42A
141
DQ40
MEMINTF_DQ41
AH18
PB42B
143
DQ41
MEMINTF_DQ42
AF17
PB42C
151
DQ42
MEMINTF_DQ43
AG17
PB42D
153
DQ43
MEMINTF_DQ44
AJ18
PB43A
140
DQ44
MEMINTF_DQ45
AJ19
PB43B
142
DQ45
MEMINTF_DQ46
AK21
PB46B
152
DQ46
MEMINTF_DQ47
AG18
PB47B
154
DQ47
MEMINTF_DQ48
AF19
PB49D
157
DQ48
MEMINTF_DQ49
AK23
PB51B
159
DQ49
MEMINTF_DQ50
AH19
PB51C
173
DQ50
MEMINTF_DQ51
AH20
PB51D
175
DQ51
MEMINTF_DQ52
AE19
PB52C
158
DQ52
MEMINTF_DQ53
AE20
PB52D
160
DQ53
MEMINTF_DQ54
AE21
PB53A
174
DQ54
MEMINTF_DQ55
AF21
PB53B
176
DQ55
MEMINTF_DQ56
AG22
PB55B
179
DQ56
25
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
Table 28. DDR2 Memory SODIMM Module Interface (See Appendix A, Figure 18) (Continued)
DDR2 Net
900-fpBGA Ball
5S25 Site
SODIMM Pin
SODIMM Signal
MEMINTF_DQ57
AH22
PB56A
181
DQ57
MEMINTF_DQ58
AH23
PB56B
189
DQ58
MEMINTF_DQ59
AH21
PB56C
191
DQ59
MEMINTF_DQ60
AD23
PB57A
180
DQ60
MEMINTF_DQ61
AE23
PB57B
182
DQ61
MEMINTF_DQ62
AH24
PB59A
192
DQ62
MEMINTF_DQ63
AH25
PB59B
194
DQ63
MEMINTF_DQS0
AH10
PB20A
13
DQS0
MEMINTF_DQS1
AF13
PB20C
31
DQS1
MEMINTF_DQS2
AJ11
PB23A
51
DQS2
MEMINTF_DQS3
AK8
PB24A
70
DQS3
MEMINTF_DQS4
AK20
PB46A
131
DQS4
MEMINTF_DQS5
AF18
PB47A
148
DQS5
MEMINTF_DQS6
AJ20
PB49A
169
DQS6
MEMINTF_DQS7
AK22
PB51A
188
DQS7
MEMINTF_K
AK24
PB52A
30
CK0
MEMINTF_K#
AK25
PB52B
32
CK0#
MEMINTF_K#_COPY
AF27
PB65B
164
CK1
MEMINTF_K_COPY
AG26
PB65A
166
CK1#
MEMINTF_RAS#
AJ1
PB3B
108
RAS#
MEMINTF_WE#
AE5
PB3D
109
WE#
SSTL Memory Interface Voltage References
The SSTL I/O interface requires a voltage reference for proper operation. This voltage reference is VCCIO18/2 typical. This reference is sourced from a regulator (Appendix A, U12 schematic, Figure 11) or can be trimmed by the
user with potentiometers (Appendix A, R185/184 schematic, Figure 17). J147 is used to select the source of the
voltage reference.
Memory Interface Voltage Terminations
The DDR2 interface needs termination of the memory module. This is accomplished using the VTT regulator
(Appendix A, U23 schematic, Figure 19). The VTT is used by the resistor terminations provided on the board. This
regulator also provides a dedicated voltage reference to the SODIMM.
The LatticeSC also has an optional termination that can be supplied to the device. This termination voltage is generated on board by (Appendix A, U12 Figure 11) and must be selected by the user’s design. This VTT source also
needs to be chosen on the board with the adjacent J59.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
26
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Lattice Semiconductor
Revision History
Date
Version
March 2006
01.0
Initial release.
Change Summary
July 2006
01.2
Updated FPGA Test Selector Header table and FPGA I/O Test SMA
Connectors table.
April 2007
01.3
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
27
28
A
B
C
5
4
4
Lattice
SC-FPGA
Config/MPI
Memory Controller
PB
3
SERDES
3
SERDES
2
2
SFI/XSBI Intf.
PR
D
5
D a te :
S iz e
B
Title
10/29/05
Date
GL027
Description
1
S he e t
1
1
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
Block Diagram
JPS
Initials
Revision
of
19
3.0
3.0
Rev.
Version
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Appendix A. PCB Schematics
Figure 4. Block Diagram
SPI4 Intf.
PL
A
B
C
3_3
OUT5
OUT7
COMP8
COMP6
COMP4
COMP2
PWR_POR#
IN2
IN4
VMON1
VMON3
VMON5
VMON7
VMON9
VMON11
HVOUT4
HVOUT2
VCCIO25
VCCJ
5
HEADER 20x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J1
VCCIO18
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
OUT6
OUT8
COMP7
COMP5
COMP3
COMP1
PWR_CLK
VMON2
VMON4
VMON6
VMON8
VMON10
VMON12
HVOUT3
HVOUT1
IN1
IN3
PWR_RESETN
pg.8 VTT_RIGHT_EXT
pg.8 VTT_BOTTOM_EXT
pg.8 VTT_LEFT_EXT
VDDTX
VDDRX
VDDAX25
VDDOB
VDDIB
VCCAUX
VCC12
VCC
TB2
Q1
2N2222/SOT23
220R/SMT0603
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
76
79
82
85
88
91
94
97
100
103
106
J2A
Q2
2N2222/SOT23
1
10K/SMT0603
R4
1_5
LED-SMT1206_GREEN
D2
1.5V
J2B
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
SENSE3_3
SENSE2_5
SENSE1_8
SENSE1_5
SENSE1_2
SENSE1_0/1_2
VCCIO1
VCCIO18
VCC12
VDDAX25
VDDIB
VDDRX
VCC_ENABLE
VCCAUX_ENABLE
VCCIO_ENABLE
VCC12_ENABLE
VDDAX25_ENABLE
VDDOB_ENABLE
VDDIB_ENABLE
VDDTX_ENABLE
VDDRX_ENABLE
VDDP_ENABLE
R10
1
10K/SMT0603
LED-SMT1206_GREEN
D6
1_2
1.2V
R7
220R/SMT0603
5_0_IN
2_5
SENSE3_3 pg.3
SENSE2_5 pg.3
SENSE1_8 pg.3
SENSE1_5 pg.3
SENSE1_2 pg.3
SENSE1_0/1_2 pg.3
VCCIO25
VCC
VCCAUX
VDDOB
VDDTX
VDDP
VCC_ENABLE pg.5
VCCAUX_ENABLE pg.7
VCCIO_ENABLE pg.6
VCC12_ENABLE pg.7
VDDAX25_ENABLE pg.4
VDDOB_ENABLE pg.4
VDDIB_ENABLE pg.4
VDDTX_ENABLE pg.4
VDDRX_ENABLE pg.4
VDDP_ENABLE pg.4
R8
130R/SMT0603
2.5V
D4
LED-SMT1206_GREEN
4
3_3
3
1
10K/SMT0603
R6
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
75
78
81
84
87
90
93
96
99
102
105
108
111-0703-001-BLACK
BAN3
3_3
1_8
1_5
1_2
PROBE_VCC pg.7
2_5
PHR3
VDD
GND
RPM
1
2
3
2
5_0_IN
3_3V_INPUT
5V_INPUT
CHIP COOLER
CONNECTION
J3
PROGRAMN pg.10
GSRN
pg.10
111-0703-001-BLACK
BAN4
POWER INPUTS
FROM BENCH
TOP SUPPLIES
BAN1
111-0702-001-RED
3_3V_BENCH_INPUT
BAN2
111-0702-001-RED
IN1
IN2
IN3
IN4
OUT5
OUT6
OUT7
OUT8
5_0_IN
R9
165R/SMT0603
3.3V
D5
LED-SMT1206_GREEN
J2C
5V_BENCH_INPUT
LED-SMT1206_GREEN
D3
1_8
1.8V
R3
220R/SMT0603
5_0_IN
Q3
2N2222/SOT23
PWR1208 EVAL BRD INTERFACE
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT1
HVOUT2
HVOUT3
HVOUT4
VMON12
VMON11
VMON10
VMON9
VMON8
VMON7
VMON6
VMON5
VMON4
VMON3
VMON2
VMON1
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
PWR_RESETN
PWR_CLK
PWR_POR#
1
10K/SMT0603
R5
LED-SMT1206_GREEN
D1
1_0/1_2
1.0/1.2V
VCC
R2
220R/SMT0603
5_0_IN
POWER RAIL GOOD INDICATORS
Q4
2N2222/SOT23
TRM BLK ED120/7DS
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
G
3
2
D
5_0_IN
HEADER 36x3
TRM BLK ED120/12DS
R1
G
TB1
G
3
2
G
3
2
G
3
2
G
1
1
VDDP
HEADER 36x3
1
1
2
8
5
2
1520
+
+
T1
T3
4
3B
7
3A
+
+
3_3V_INPUT
+
+
+
+
+
+
NOTE: PIN 2
IS USED AS
LINE SIDE
AND PIN 1 IS
USED AS LOAD
SIDE OF
FUSE.
F1400-ND
F2
NOTE: PIN 2
IS USED AS
LINE SIDE
AND PIN 1 IS
USED AS LOAD
SIDE OF
FUSE.
F1400-ND
F1
1
S he e t
5_0_IN
LED-SMT1206_GREEN
D7
5V INPUT
T2
T4
3_3_IN
2
of
R12
220R/SMT0603
19
Rev
3.0
LED-SMT1206_GREEN
D8
3.3V INPUT
1520
R11
220R/SMT0603
1520
3_3V_PS_INPUT
MOLEX_87427-1203
PWR1
3_3V_PS_INPUT
P roje c t
SC-900FPBGA Communications Platform Evaluation Board
Power Input/Misc.
+
5V_PS_INPUT
PS_MOD_EN
3_3V_BENCH_INPUT
3_3V_PS_INPUT
5V_BENCH_INPUT
5V_PS_INPUT
PS_MOD_EN
5V_INPUT
9
OFF
6
2B
OFF
2A
+
D a te :
S iz e
B
Title
1
OFF
3
CK7303MD9ABE
1520
POWER INPUTS
1
SUPPLY INPUTS FROM
PC POWER & COOLING
SILENCER 310 ATX POWER MODULE
24 AMP- 3.3V /28 AMP-5.0V
1B
1A
3PDT
ON-OFF-ON
COM3
COM2
COM1
SW1
S31X-LA1
PS1
100UF/ALCAP
100UF/ALCAP
EXTERNAL
SUPPLIES
HEADER 36x3
C1
C7
C2
C8
C3
C9
100UF/ALCAP
100UF/ALCAP
10UF/SM_TANT_B
10UF/SM_TANT_B
3
10UF/SM_TANT_B
C5
10UF/SM_TANT_B
C11
4
10UF/SM_TANT_B
10UF/SM_TANT_B
12
11
10
9
8
7
PS ON
5V
GND
5V
GND
5V
GND
5V
3.3V GND
3.3V
3.3V
6
5
4
3
2
1
G
5
100UF/ALCAP
100UF/ALCAP
C4
C10
C6
C12
29
G
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 5. Power Input
A
B
C
D
5
REMOVE BARRIER TAB
& ADD JUMPER TO SHUTDOWN
DC/DC MODULE
EXTERNAL SUPPLIES CAN BE SOURCED
VIA THE TERMINAL BLOCK
470UF/ALCAP
+
470UF/ALCAP
3_3_IN
C13
+
5_0_IN
3_3_IN
2
1
1
2
2
1
1
2
U7
2
1
2
1
GND
VIN
HEADER 2x1
J22
2
1
GND
VIN
HEADER 2x1
J16
J8
1
2
U2
2
1
GND
VIN
HEADER 2x1
U5
3_3_IN
SENSE
PTH05010W
VOUT
5_0_IN
SENSE
VOUT
4
R87
5
6
1_8REG
4_7K/SMT0603
SET VALUE
1.8V= 5.49K
BOURNS-3224W-10K
R230
R37
470UF/ALCAP
C16
+
1
JUMPER TAB/MOLEX #1432
TAB4
R24
15K/SMT0603
R25
34K/SMT0603
BS1
2
TAB6
BS4
2
470UF/ALCAP
C24
+
1
BS6
2
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
JUMPER TAB/MOLEX #1432
470UF/ALCAP
C20
+
1
T10
1_0/1_2_FUSE
T6
1_8_FUSE
T14
1_5_FUSE
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
HEADER 3x1
1
3
JUMPER TAB/MOLEX #1432
TAB1
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
1_0/1_2REG
1V
ADJ
1.2V
J10
1_5REG
2
5
6
8_25K/SMT0603
SET VALUE
1.5V= 8.87K
5
6
SET VALUE
1V= 36.5K
1.2V=17.4K
3_3_IN
BOURNS-3224W-10K
R228
PTH03010W
VOUT
SENSE
BOURNS-3224W-10K
R226
PTH03010W
INHIBIT#
3
5_0_IN
ADJUST
C22
9
MDWN
10
MUP
3_3_IN
4
9
4
5
10
MUP
9
MDWN
ADJUST
4
INHIBIT#
3
MUP
R13
8
TRACK
10
INHIBIT#
3
100K/SMT0603
GND
7
MDWN
100K/SMT0603
SENSE1_0/1_2
SENSE1_0/1_2
ADJUST
4
R29
100K/SMT0603
TRACK
7
GND
8
R45
8
TRACK
GND
7
SENSE1_5
SENSE1_5
SENSE1_8
SENSE1_8
1_8
1_5
T12
1520
T16
F8
F1400-ND
1.8V
1520
F6
F1400-ND
1.5V
T7
F3
F1400-ND
1.0/1.2V
1520
1_0/1_2
J15
3
2
1
2
1
1
2
U4
2
1
R227
2
1
VOUT
SENSE
5_0_IN
SENSE
VOUT
5_0_IN
PTH05010W
VOUT
SENSE
5
6
BS2
JUMPER TAB/MOLEX #1432
TAB3
470UF/ALCAP
C15
+
1
T9
2
1
TAB5
2
1
470UF/ALCAP
C23
+
BS5
2
1520
T8
F4
F1400-ND
1.2V
3_3
1520
1520
F7
F1400-ND
T15
3.3V
T11
F5
F1400-ND
2.5V
1_2
2
2
Date:
Size
Title
B
1
SSheet
he e t
1
3
SC-900FPBGA Communications Platform Evaluation Board
Project
Power Regulation
Power Rails are not sequenced.
All sequencing is done on a per SC device
power supply.
3_3_FUSE
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
T13
2_5_FUSE
JUMPER TAB/MOLEX #1432
BS3
2_5
1_2_FUSE
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
470UF/ALCAP
3_3REG
470R/SMT0603
SET VALUE
3.3V= 698-ohm R48
BOURNS-3224W-10K
R231
R36
T5
JUMPER TAB/MOLEX #1432
TAB2
BARRIER BLK/MOLEX SERIES 71-5-2-45-C
C18
+
1_2REG
2_5REG
1_82K/SMT0603
SET VALUE
2.5V= 2.21K
5
6
5
6
SENSE1_2
R23
15K/SMT0603
SET VALUE
1.2V= 17.4K
BOURNS-3224W-10K
BOURNS-3224W-10K
GND
3_3_IN
PTH03010W
PTH05010W
R229
VIN
HEADER 2x1
J21
1
2
U6
2
1
GND
VIN
2
1
GND
VIN
HEADER 2x1
J9
1
2
U3
HEADER 2x1
5_0_IN
5_0_IN
3_3_IN
3
10
MUP
INHIBIT#
3
pg.2
R15
8
TRACK
ADJUST
4
pg.2
pg.2
MUP
10
INHIBIT#
3
9
MDWN
ADJUST
10
INHIBIT#
3
MUP
9
MDWN
8
TRACK
100K/SMT0603
GND
7
ADJUST
4
R28
9
MDWN
R40
8
TRACK
SENSE2_5
SENSE2_5
4
100K/SMT0603
GND
7
100K/SMT0603
GND
7
pg.2
SENSE1_2
SENSE3_3
pg.2
pg.2
30
SENSE3_3
off
o
19
3.0
Rev
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 6. Power Regulation
A
B
1_2
J29
5
1x2 0.100" Header
HEADER 2x1
VDDRX_ENABLE
C38
Analog Supply
SERDES RX
VDDRX
FB29
VDDRX_I
BLM41PG471SN1L
VDDIB_ENABLE
+
+
4
VDDIB
VDDRX
1_2
pg.2
pg.2
VDDTX_S
1x2 0.100" Header
HEADER 2x1
J30
3
3
VDDOB_S
J27
Q21
IRLR8103V/TO
VDDOB
SERDES
CML OUTPUT SUPPLY
IRLR8103V/TO
Q25
+
FB30
10UF/SM_TANT_B
VDDTX_ENABLE
VDDOB
3
Analog Supply
SERDES TX
VDDTX
VDDTX_I
BLM41PG471SN1L
VDDOB_ENABLE
C39
1
pg.2
2
3
2
IRLR8103V/TO
Q24
pg.2
10K/SMT0603
3
VDDIB_S
Q20
IRLR8103V/TO
R53
VDDIB_ENABLE
J26
10UF/SM_TANT_B
C54
1
VDDRX_S
1
1
1UF/SMT1206
C55
C
2
2
C43
10UF/SM_TANT_B
VDDIB
1UF/SMT1206
R54
SERDES
CML INPUT SUPPLY
10K/SMT0603
C45
1_2 1_5
1UF/SMT1206
1_2 1_5
C56
1
1
+
VDDAX25
2_5
J28
VDDTX
1x2 0.100" Header
HEADER 2x1
1_2
VDDAX25_S
VDDP_S
pg.2
2
+
10UF/SM_TANT_B
C40
VDDAX25
VDDP_ENABLE
D a te :
S iz e
B
Title
+
10UF/SM_TANT_B
VDDP
1
1
S he e t
4
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
SERDES SUPPLIES
Analog Supply
For SERDES PLL
VDDP
FB31
VDDP_I
BLM41PG471SN1L
Q23
IRLR8103V/TO
VDDAX25_ENABLE
pg.2
1x2 0.100" Header
HEADER 2x1
J31
Q22
2
IRLR8103V/TO
Auxillary SERDES VDD
1
1
1
1
2
2
2
2
2
2
SERDES SUPPLIES
C57
R55
VDDAX25_ENABLE
3
1UF/SMT1206
10K/SMT0603
10K/SMT0603
C41
D
R57
VDDRX_ENABLE
1
1
1UF/SMT1206
C51
4
10K/SMT0603
VDDOB_ENABLE
R58
VDDTX_ENABLE
2
2
10K/SMT0603
R56
VDDP_ENABLE
5
C52
31
1UF/SMT1206
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 7. SERDES Supplies
10UF/SM_TANT_B
A
B
VCC
VCC
VCC
C63
10NF/SMT0603
VCC
VCC
VCC
VCC
VCC
5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SC-900FPBGA-BOARD1
VCC
U1E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C66
SC-900FPBGA
5
10NF/SMT0603
C67
L10
L21
M10
M21
N10
N21
P10
P21
U10
U21
V10
V21
W10
W21
Y10
Y21
K10
K11
K12
K13
K14
K17
K18
K19
K20
AA10
AA11
AA12
AA13
AA14
AA17
AA18
AA19
AA20
AA21
AA22
AA9
AB10
AB21
J10
J21
J22
J9
K22
K9
K21
VCC
C64
C65
VCC
C78
C79
C80
C81
10NF/SMT0603
VCC
VCC
VCC
C68
VCC
VCC
VCC
VCC
C69
VCC
C82
C83
VCC
C77
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
VCC
VCC
VCC
VCC
VCC
VCC
VCC_ENABLE
R59
VCC_ENABLE
10K/SMT0603
VCC
VCC
VCC
C61
4
VCC
VCC
VCC
1UF/SMT1206
4
C62
VCC
10UF/SM_TANT_B
VCC
VCC
VCC
VCC
VCC
VCC
1
VCC
2
PP1
100NF/SMT0603
Place close to U1
VCC
VCC
+
VCC
C74
Q26
IRLR8103V/TO
C70
pg.2
10NF/SMT0603
C71
10NF/SMT0603
C72
C73
10NF/SMT0603
C75
10NF/SMT0603
C76
1_0/1_2
C84
C85
C86
C88
C
C91
C92
C93
C94
C95
C96
C97
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C87
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C89
VCC
C106
C107
C108
C109
10NF/SMT0603
C110
100NF/SMT0603
C111
C98
C99
C102
C103
10NF/SMT0603
C90
100NF/SMT0603
D
C105
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
10NF/SMT0603
C100
100NF/SMT0603
C101
10NF/SMT0603
100NF/SMT0603
10NF/SMT0603
C104
100NF/SMT0603
32
Y19
Y20
N15
N16
N17
N18
N19
N20
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
U1F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
2
SC-900FPBGA
1
TP9
1
TP8
1
TP7
1
TP6
1
TP5
1
TP4
1
TP3
1
TP2
1
TP1
D a te :
Title
S iz e
B
1
S he e t
1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
Power/Bypass
DISTRIBUTED GND
PROBE POINTS
AROUND BOARD AREA
VSS
1
TP10
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
AA15
AA16
AK1
AK30
K15
K16
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
M11
M12
M13
M14
M15
M16
M17
M18
N12
N13
N11
N14
H1
K2
M3
N5
L4
M2
P6
H3
G4
Y4
AE1
AC2
AA3
AB4
AA5
AE8
AE6
AH5
AG9
AF11
AG12
AG6
AJ10
AJ27
AK26
AJ22
AF20
AJ25
AF23
AF22
AE27
AA27
AB29
Y29
Y26
AC30
F27
E27
F30
P25
H29
K29
R24
M28
J27
N26
E20
E21
F21
F23
D21
D20
G23
E18
C20
C11
A12
F8
E11
G8
D11
D10
H7
F10
E10
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
of
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
M19
M20
A1
A30
19
SC-900FPBGA-BOARD1
Rev
3.0
A
B
C
D
Figure 8. Power/Bypass
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
A
B
C
VCCIO1
VCCIO1
C140
10NF/SMT0603
C141
VCCIO18
5
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO18
VCCIO25
VCCIO
SC-900FPBGA
J19
J18
J16
J15
J17
J13
J12
J11
H9
H22
H21
J14
J20
H10
F20
C19
C12
F11
VCCIO18
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
SC-900FPBGA-BOARD1
4
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
U1C
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
PP2
VCCIO18
PP3
VCCIO25
3
PP4
R60
Q27
IRLR8103V/TO
VCCIO1
pg.2 VCCIO_ENABLE
VCCIO1
VCCIO1=>>
SELECT BETWEEN
2.5V or 3.3V
3
Place close to U1
VCCIO18
VCCIO25
VCCIO25
P22
R22
L23
L22
K24
K23
J24
N22
M22
J23
G30
J29
K27
N25
T22
AB24
AA23
AA24
AB23
Y24
W22
U22
V22
Y22
Y23
AA26
AA29
Y28
AC29
C112
1UF/SMT1206
4
AH6
AG11
AJ9
AE7
AD10
AC9
AC11
AC10
AB15
AB14
AB13
AB12
AB11
AD9
AD11
AC22
AC21
AB16
AB17
AB18
AB19
AB20
AC20
AD21
AD22
AD20
AG23
AG20
AJ23
AJ26
1
1
1
10K/SMT0603
VCCIO1
2
2
2
VCCIO_ENABLE
C179
5
L9
M9
N9
H2
N4
N6
J2
L2
H4
L8
K8
R9
P9
J7
K7
J8
W4
AB2
AD1
AA4
U9
V9
AA7
AA8
AB7
AB8
T9
Y7
Y8
W9
Y9
C142
C143
C145
C147
C150
C151
10NF/SMT0603
C158
100NF/SMT0603
C159
100NF/SMT0603
100NF/SMT0603
C161
100NF/SMT0603
C162
100NF/SMT0603
C163
100NF/SMT0603
10NF/SMT0603
J32
10NF/SMT0603
VCCIO25
10NF/SMT0603
10NF/SMT0603
C144
10NF/SMT0603
10NF/SMT0603
C146
10NF/SMT0603
C148
10NF/SMT0603
C149
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
C154
100NF/SMT0603
C155
100NF/SMT0603
C156
100NF/SMT0603
C157
100NF/SMT0603
C160
C176
10NF/SMT0603
C177
10NF/SMT0603
C178
D
C164
100NF/SMT0603
C165
100NF/SMT0603
C166
100NF/SMT0603
C167
100NF/SMT0603
C168
10NF/SMT0603
100NF/SMT0603
C169
100NF/SMT0603
C170
10NF/SMT0603
C171
10NF/SMT0603
C172
10NF/SMT0603
C173
10NF/SMT0603
C174
10NF/SMT0603
10NF/SMT0603
C175
10NF/SMT0603
C152
100NF/SMT0603
C153
33
C180
10NF/SMT0603
4
2
C181
3
1
2_5
3_3
10NF/SMT0603
VCCIO25
C115
1UF/SMT1206
+
VCCIO1
2
+
S iz e
B
D a te :
Title
+
+
VCCIO18
+
+
S he e t
VCCIO18 VCCIO18
R62
1
6
Q29
IRLR8103V/TO
VCCIO18=>>
VCCIO4, VCCIO5
1
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
VCCIO
2_5
+
VCCIO25 VCCIO25 VCCIO25 VCCIO25
R61
10K/SMT0603
Q28
IRLR8103V/TO
VCCIO_ENABLE
C118
1UF/SMT1206
10K/SMT0603
2
C128
C138
C130
VCCIO25=>>
VCCIO2, VCCIO3,
VCCIO6, VCCIO7
C131
10UF/SM_TANT_B
C127
10UF/SM_TANT_B
10UF/SM_TANT_B
10UF/SM_TANT_B
C139
10UF/SM_TANT_B
C129
10UF/SM_TANT_B
10UF/SM_TANT_B
VCCIO_ENABLE
of
1_8
19
Rev
3.0
A
B
C
D
Figure 9. VCCIO
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
A
B
C
10NF/SMT0603
C186
C185
C199
PP5
C195
10NF/SMT0603
JTAG
VCC Supply FB13
VCCJ
PP7
+1.8V
VCCJ
5
+2.5V
VCCJ
+3.3V
VCCJ
SELECTING VCCJ VOLTAGES
+
VCCAUX
Place close to U1
VCC12
C187
VCCJ
10NF/SMT0603
Place these capacitors
as close as physically
possible to device.
10NF/SMT0603
C182
VCC12
C183
C193
C203
1
2
10NF/SMT0603
C188
VCC12
100NF/SMT0603
D
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C218
C192
C202
C184
C194
10UF/SM_TANT_B
C189
3_3
2_5
1_8
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
1
2
100NF/SMT0603
C196
C204
BLM41PG471SN1L
C197
C190
VCC12
100NF/SMT0603
10NF/SMT0603
J46
HEADER 3x2
4
VCC1P2
VCC1P2
VCC1P2
VCC1P2
VCC1P2
VCC1P2
VCC1P2
VCC1P2
VCC1P2
RESP_ULC
10NF/SMT0603
C201
22PF/0603 Johanson 250-R15X220JV4
6
4
2
VCCL_LLC_A
VCCL_LLC_B
VCCL_LRC_A
VCCL_LRC_B
VCCL_ULC_A
VCCL_ULC_B
VCCL_URC_A
VCCL_URC_B
1_2
J23
pg.2
1x2 0.100" Header
HEADER 2x1
Q17
IRLR8103V/TO
VCC12_ENABLE
+
VCC12
1UF/SMT1206
3
2_5
2
J44
Q19
IRLR8103V/TO
VCCAUX
VCCAUX
VCCAUX
pg.2
1x2 0.100" Header
HEADER 2x1
PROBE_VCC pg.2
VCC1P2 Supply
For Config RAM
and VCCPLL
VCC12
PP17
PROBE_VCC
VCC12
AG4
AF5
AG27
AF26
E5
D4
E26
D27
SC-900FPBGA-BOARD1
Internal VCC can be measured
or can be used to trim VCC regulator
to compensate for IR drops on
board and within the device
AB9
AC8
H23
H15
AC23
R23
AB22
T8
H8
1
6
4
2
5
3
1
R67
2
1
VCC12
C219
4_02K_1%/SMT0603
RESP_URC
A29
R68
4_02K_1%/SMT0603
10K/SMT0603
VCCAUX_ENABLE
10UF/SM_TANT_B
C191
Auxillary VCC
for I/O
VCC_AUX
+
VCCAUX
C30
VCCJ
C25
1
1
U1D
R50
C205
5
3
1
10NF/SMT0603
C220
PROBE_GND
AE28
10UF/SM_TANT_B
100NF/SMT0603
100NF/SMT0603
VCCJ
10K/SMT0603
100NF/SMT0603
1UF/SMT1206
J25
XRES
SC-900FPBGA
R69
1K_1%/SMT0603
A2
2
22PF/0603 Johanson 250-R15X220JV4
PROBE_VCC
AD27
1
2
AE4
VCC12_ENABLE
C206
C26
C209
C221
C230
R52
VCCAUX_ENABLE
2
C210
C222
C231
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C211
C223
C232
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
C212
C224
C233
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C213
C225
2
C234
C214
C226
D a te :
S iz e
B
Title
C235
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
C215
C227
C238
H12
H11
H20
H19
M23
N24
M24
N23
U23
V23
V24
U24
W24
W23
AC18
AC17
AD17
AD18
AC19
AD19
AC13
AC14
AC12
AD13
AD14
AD12
V7
V8
U7
U8
W8
W7
M7
N8
M8
N7
VCCAUX
U1L
S he e t
1
7
of
VCCAUX
SC-900FPBGA-BOARD1
VCCAUX1
VCCAUX1
VCCAUX1
VCCAUX1
VCCAUX2
VCCAUX2
VCCAUX2
VCCAUX2
VCCAUX3
VCCAUX3
VCCAUX3
VCCAUX3
VCCAUX3
VCCAUX3
VCCAUX4
VCCAUX4
VCCAUX4
VCCAUX4
VCCAUX4
VCCAUX4
VCCAUX5
VCCAUX5
VCCAUX5
VCCAUX5
VCCAUX5
VCCAUX5
VCCAUX6
VCCAUX6
VCCAUX6
VCCAUX6
VCCAUX6
VCCAUX6
VCCAUX7
VCCAUX7
VCCAUX7
VCCAUX7
1
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
VCC1P2/Misc
C236
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
C216
C228
C237
VCC12
C239
2
10NF/SMT0603
3
100NF/SMT0603
FPGA SUPPLIES
4
C240
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
SC-900FPBGA
C241
5
10NF/SMT0603
34
100NF/SMT0603
19
Rev
2.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 10. VCCIP2
A
B
C
2_5
+
VTT_RIGHT
pg.13 VREF_RIGHT
3
3
1
2
2
VCCIO18
VREF_BOTTOM
HEADER 3x1
1
J56
5
4
2
5
4
2
5
6
7
VDDQ
VREF
SD
VDDQ
VREF
SD
1=>2 = External
3=>4 = VCCIO/2
3=>5 = GND
pg.15 VREF_BOTTOM
VREF_RIGHT
VCCIO25
10UF/SM_TANT_B
C248
D
1
HEADER 3x1
2
1UF/SMT1206
C249
R70
4_7K/SMT0603
C34
R78
4_7K/SMT0603
2
2_5
8
3
LP2996-SO8
VTT
VSENSE
U8
8
3
+
J52
HEADER 3x2
GND
NC
VTT_RIGHT_EXT
C262
+
pg.2 VTT_BOTTOM_EXT
VTT_BOTTOM
I_VTT_BOTTOM
R80
0R/SMT0603
VCCIO/2
pg.2
VTT
EXT
4
1
2
AC24
T25
W25
L24
T23
+
VTT_BOTTOM
+
VTT_5
VTT_5
VTT_5
VTT_6
VTT_6
VTT_6
VTT_7
VTT_7
AE9
AD16
AC15
W6
T7
AA6
P7
L7
VTT_LEFT
VTT_BOTTOM
VTT_LEFT
PP10
VTT_BOTTOM
pg.2 VTT_LEFT_EXT
3
+
VTT_LEFT
VTT pins should be connected to GND(3-5) when not used
in FPGA design
VTT_BOTTOM
J59
HEADER 3x2
PP9
SC-900FPBGA-BOARD1
VTT_4
VTT_4
VTT_4
VTT_3
VTT_3
VTT_3
VTT_2
VTT_2
U1H
VTT_BOTTOM
VTT_RIGHT
PP8
VTT_LEFT
Place close to U1
VTT_RIGHT
VTT_BOTTOM
AD24
AE17
AE18
VTT_RIGHT
C568
1000PF-0402SMT-Johanson 100R05W102FV4
C246
I_VTT_RIGHT
R72
0R/SMT0603
VTT_RIGHT
C243
SELECTING VTT VOLTAGES
LP2996-SO8
VTT
VSENSE
U12
100NF/SMT0603
C255
3
100NF/SMT0603
C253
C242
C257
GND
1
100NF/SMT0603
10NF/SMT0603
C256
1UF/SMT1206
10NF/SMT0603
1
1UF/SMT1206
AVIN
PVIN
100NF/SMT0603
C254
6
7
AVIN
PVIN
GND
1
100UF/ALCAP
2_5
100UF/ALCAP
100NF/SMT0603
C258
6
4
2
6
4
2
1
2
J48
C35
1
3
10UF/SM_TANT_B
C251
10UF/SM_TANT_B
C573
5
3
1
1
2
SC-900FPBGA
1UF/SMT1206
C250
1UF/SMT1206
C572
5
3
1
6
4
2
5
3
1
5
3
1
6
4
2
VTT_BOTTOM_EXT
C42
J50
HEADER 3x2
I_VTT_LEFT
VTT_LEFT
+
2
R73
0R/SMT0603
8
3
VTT
VSENSE
U9
100NF/SMT0603
1UF/SMT1206
C247
2_5
2
D a te :
S iz e
B
Title
SD
5
4
2
LP2996-SO8
VDDQ
VREF
2
J49
1
3
1
3
2_5
VREF_LEFT pg.17
S he e t
1
8
of
19
C570
1000PF-0402SMT-Johanson 100R05W102FV4
VCCIO25
VREF_LEFT
HEADER 3x1
2
1
R71
4_7K/SMT0603
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
VTT
C575
1000PF-0402SMT-Johanson 100R05W102FV4
C569
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C315
2_5
100NF/SMT0603
C263
100NF/SMT0603
C578
100UF/ALCAP
3
100NF/SMT0603
C260
100NF/SMT0603
C576
2
100NF/SMT0603
C261
100NF/SMT0603
C577
2
4
6
2
4
6
1
3
5
1
3
5
C36
10NF/SMT0603
C259
C244
100NF/SMT0603
C571
C245
100NF/SMT0603
C314
7
6
PVIN
AVIN
GND
1
4
10NF/SMT0603
5
10UF/SM_TANT_B
C252
10NF/SMT0603
35
10NF/SMT0603
C574
1UF/SMT1206
C264
VTT_RIGHT_EXT
10NF/SMT0603
C265
VTT_LEFT_EXT
10NF/SMT0603
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 11. VTT
A
B
C
C268
22PF/0603 Johanson 250-R15X220JV4
C293
VDDRX
C274
22PF/0603 Johanson 250-R15X220JV4
22PF/0603 Johanson 250-R15X220JV4
5
C296
C266
VDDRX
VDDP
22PF/0603 Johanson 250-R15X220JV4
22PF/0603 Johanson 250-R15X220JV4
VDDOB
C267
VDDTX
22PF/0603 Johanson 250-R15X220JV4
VDDIB
VDDIB
VDDRX
VDDIB
VDDAX25
VDDTX
VDDRX
VDDOB
2
3
4
5
J146
1
SMA_901_144_8
VDDRX
VDDIB
C3
C6
C7
C10
C4
C5
C8
C9
D6
E7
D8
E9
E6
D7
E8
D9
F24
F7
4
VDDRX
VDDOB
VDDIB
VDDRX
VDDIB
VDDRX
VDDIB
VDDRX
VDDIB
VDDRX
VDDIB
VDDRX
VDDOB
SC-900FPBGA
SERDES
SUPPLIES
SC-900FPBGA-BOARD1
A_VDDIB0_L
A_VDDIB1_L
A_VDDIB2_L
A_VDDIB3_L
A_VDDOB0_L
A_VDDOB1_L
A_VDDOB2_L
A_VDDOB3_L
A_VDDRX0_L
A_VDDRX1_L
A_VDDRX2_L
A_VDDRX3_L
A_VDDTX0_L
A_VDDTX1_L
A_VDDTX2_L
A_VDDTX3_L
A_VDDAX25_R
A_VDDAX25_L
VDDTX
VDDOB
VDDTX
3
VDDTX
VDDOB
C28
C25
C24
C21
C27
C26
C23
C22
D25
E24
D23
E22
E25
D24
E23
D22
D5
D26
VDDOB
A_VDDIB0_R
A_VDDIB1_R
A_VDDIB2_R
A_VDDIB3_R
A_VDDOB0_R
A_VDDOB1_R
A_VDDOB2_R
A_VDDOB3_R
A_VDDRX0_R
A_VDDRX1_R
A_VDDRX2_R
A_VDDRX3_R
A_VDDTX0_R
A_VDDTX1_R
A_VDDTX2_R
A_VDDTX3_R
A_VDDP_L
A_VDDP_R
VDDTX
VDDOB
VDDP
VDDTX
VDDRX
VDDOB
VDDTX
VDDOB VDDOB
VDDTX
VDDTX
C290
VDDIB
VDDRX
C269
VDDOB
VDDTX
C291
D
C276
C298
C277
C299
10NF/SMT0603
10NF/SMT0603
C278
C300
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
10NF/SMT0603
C279
C301
C280
C302
100NF/SMT0603
100NF/SMT0603
C281
C303
10NF/SMT0603
10NF/SMT0603
C282
C304
100NF/SMT0603
100NF/SMT0603
C283
C305
10NF/SMT0603
10NF/SMT0603
C284
C306
100NF/SMT0603
100NF/SMT0603
C285
C307
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C286
C308
C287
C309
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C288
C310
C289
C311
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
U1B
C312
VDDIB
10NF/SMT0603
100NF/SMT0603
Place these capacitors
as close as physically
possible to device.
C313
2
VDDRX
VDDAX25 VDDAX25
D a te :
S iz e
B
Title
C270
VDDTX
22PF/0603 Johanson 250-R15X220JV4
C292
2
VDDRX
VDDP VDDP
VDDTX
VDDTX
1
VDDIB
VDDIB
PP15
VDDP
VDDAX25
PP13
S he e t
1
9
of
19
PP16
PP14
VDDTX
PP12
VDDRX
PP11
Place close to U1
10NF/SMT0603
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
SERDES Analog Supplies
10NF/SMT0603
3
C273
4
100NF/SMT0603
C271
C294
C272
C295
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
C297
100NF/SMT0603
2
1
2
5
100NF/SMT0603
C275
1
2
1
1
2
1
2
1
36
2
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 12. SERDES Analog Supplies
22PF/0603 Johanson 250-R15X220JV4
A
B
C
GSRN
R98
PROGRAMN
PROGRAMN
VCCIO1
FPGA RESETN/GSRN
1
LSRN
FPGA LSR
FPGA LSRN
SW3
5
SW4
R99
3
3
VCCIO1
11
8
6
3
2Y
1Y
U17B
4A
4OE_N
3A
3OE_N
U17A
2A
2OE_N
1A
1OE_N
3_3
DONE
5
4
2
1
3
1
3
1
12
13
9
10
MAX6817
IN2
IN1
U18
SN74LVC125A/SO14
3_3
SN74LVC125A/SO14
4Y
3Y
3_3
2
4
Momentary Switch
B3F-1150
1
3
2
4
Momentary Switch
B3F-1150
1
2
4
Momentary Switch
3_3
B3F-1150
SW5
1
3
2
4
Momentary Switch
B3F-1150
1
SW2
R86
10K/SMT0603
DEDICATED FPGA
PROGRAMN, (RESETN)GSRN,
& LSRN, LSR(GPIO PINS)
CONTROL
pg.2 PROGRAMN
pg.2 GSRN
Q34
2N2222/SOT23
INITN
DONE indicator will light when
configuration is successfully
completed
LED-SMT1206_RED
4_7K/SMT0603
R93
220R/SMT0603
G
R
R94
D10
LED-SMT1206_GREEN
D9
OUT2
OUT1
VCCIO1
OUT2
OUT1
MAX6817
IN2
IN1
U16
R85
4
6
3_3
4
6
LSR
3_3 3_3
R95
R82
680R/SMT0603
R96
R83
3_3
C456
1
4.7K
TDI
RN1B
4.7K
3_3
C567
4
WRITE_PROT_N
20
19
18
17
16
15
14
13
12
11
CLOSED
IN A2
8
7
6
5
20
19
18
17
16
15
14
13
12
11
IN A2
U25
M25P80-FLASH
S#
VCC
Q HOLD#
W#
CLK
DI
GND
8
7
6
5
FLASH 2
1
2
3
4
1
3
100NF/SMT0603
Q_1
SCSN
Q_0
3_3
FLASH_DIS
RCLK
SI
3_3
3
1
FLASH_DIS
3_3
U24
IN A1
M25P80-FLASH
S#
VCC
Q HOLD#
W#
CLK
DI
GND
U26
TDA10H0SK1
10
9
8
7
6
5
4
3
2
1
OPEN
SW20
OUT Y2
OUT Y1
3_3
U14
IN A1
FLASH 1
1
2
3
4
10
9
8
7
6
5
4
3
2
1
4
6
OUT Y2
OUT Y1
3_3
EXBV8V472JV
4.7K
C316
FLASH
CFG MEMORY
SCSN_1
Q_1
SCSN_0
Q_0
WRITE_PROT_N
DATA1
WRITE_PROT_N
FLASH_DIS
CS0N
CS1
WRN
SCSN_0
SCSN_1
DATA0
NC7WZ16-MACO6A/Fairchild TinyLogic
TCK
TMS
R90
220R/SMT0603
LED-SMT1206_GREEN
D13
4
6
RN1D
4.7K
2
H5
G16
F22
G22
LSRN
LSR
SCSN
SI
F26
H16
GSRN
PROGRAMN
E4
F4
MODE2
MODE3
F6
MODE1
F5
G6
G5
F25
INITN
DONE
MODE0
CCLK
LOCAL_TMS
LOCAL_TCK
LOCAL_TDO
LOCAL_TDI
1
3
PT49C/LDCN
PT42D/VREF2_1
Flash 2
Open 1, 3, 5
Close 2, 4
2
DONE
INITN
2
3
VCC
GND
VCC
GND
HEADER 10
INITN
DONE
TCK
TMS
NC
ispEN_N
TDI
TDO
J68
2
3
4
5
6
8
9
10
7
1
7
1
2
1
0
2_5
G24
G25
H6
A18
B17
F16
J26
H25
2
3
4
DOUT
QOUT
RCLK
TMS
TDO
TDI
TCK
RDCFGN
3_3
1
QOUT
1 - M0
2 - M1
3 - M2
4 - M3
3
3
DOUT
1
RCLK
2
3
1
11
EXBV8V471JV
MODE3
MODE2
MODE1
2_5
DAT_OUT
PCM_CLK
EXBV8V472JV
2
MODE0
2
J73
3
1
J74
2
Connection to download cable VCC
connected to 3.3V
CCLK
MODE PIN
CONTROL
1
OPEN/SMT0603
R102
PT42B/DOUT
PT43A/QOUT
PT38C/RDY
TMS
TDO
TDI
TCK
RDCFGN
VCCIO1
FROM ISPVM CABLE
HEADER 3x1
3
1
INITN
DONE
TCK
TMS
NC
ispEN_N
TDI
TDO
HEADER 10
2
3
4
5
6
8
9
10
J64
TO JTAG SLAVE
Mode Select
3
1
J81
PROGRAMN
TMS
TCK
DONE
INITN
PROGRAMN
DAISY_TDO
1
0
2
1
0
8
1
0
5
1
0
3_3
2
R101
4_7K/SMT0603
DATA[0..7]
JTAG & ORCASTRA Intf.
3
SC-900FPBGA
DAISY_TDI
DAISY_TDO
SC-900FPBGA-BOARD1
PT49D/HDC
1
DAISY CHAIN
SELECTION
PT35D/DP3/PCLKC1_4/MPIWRPARITY3
RESETN
PROGRAMN
M3
M2
M1
M0
INITN
DONE
CCLK
U1I
J63
2
4
Writing Flash Devices
(SW20 settings)
Flash 1
Open 1, 2, 4
Close 3, 5
TDO
MASTER ONLY
1
2
C317
VCCIO1
1RN24A
2RN24B
3RN24C
4RN24D
1RN25A
2RN25B
3RN25C
4RN25D
8
7
6
5
8
7
6
5
4_7K/SMT0603
R100
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
D13
G12
D14
E13
E14
A13
A14
F14
G14
B13
B14
C13
C14
D15
E15
F15
G15
A15
B18
G17
G18
E16
E17
C17
C18
F18
B20
A20
A19
G13
H13
G11
E12
G9
U1K
SC-900FPBGA-BOARD1
PT25A/A17/MPIADDR31
PT25D/A16/MPIADDR30
PT25B/A15/MPIADDR29
PT27A/A14/MPIADDR28
PT27B/A13/MPIADDR27
PT28A/A12/MPIADDR26
PT28B/A11/MPIADDR25
PT29A/A10/MPIADDR24
PT29B/A9/MPIADDR23
PT31A/A8/MPIADDR22
PT31B/A7/MPIADDR21
PT32A/A6/MPIADDR20
PT32B/A5/MPIADDR19
PT33A/A4/MPIADDR18
PT33B/A3/MPIADDR17
PT33C/A2/MPIADDR16
PT33D/A1/MPIADDR15
PT35A/A0/MPIADDR14
PT43B/D0/MPIWRDATA0
PT45A/D1/MPIWRDATA1
PT45B/D2/MPIWRDATA2
PT45C/D3/MPIWRDATA3
PT45D/D4/MPIWRDATA4
PT46A/D5/MPIWRDATA5
PT46B/D6/MPIWRDATA6
PT46C/D7/MPIWRDATA7
PT49B/D8/MPIWRDATA8
PT47D/D9/MPIWRDATA9
PT47C/D10/MPIWRDATA10
PT27D/D11/MPIWRDATA11
PT27C/D12/MPIWRDATA12
PT25C/D13/MPIWRDATA13
PT23D/D14/MPIWRDATA14
PT23A/D15/MPIWRDATA15
SC-900FPBGA
PT23C/DP1/MPIWRPARITY1
PT38B/DP0/MPIWRPARITY0
MPIIRQN
PT23B/A21/MPIBURST
PT24B/A18/MPITSIZ0
PT24D/A19/MPITSIZ1
PT46D/WRN/MPIRWN
PT47A/RDN/MPISTRBN
PT38A/MPIACKN/MPITA
PT37A/MPICLK/PCLKT1_0/MPICLK
PT24A/MPITEAN/MPITEA
PT24C/A20/MPIBDIP
PT35B/MPIRTRYN/MPIRETRY
PT49A/CS1/CS1
PT47B/CS0N/CS0N
MPI
DATA/ADDR
3
1
3
1
1
2
J78
2
HEADER 3x1
Date:
Size
Title
B
J80
2 2
3 HEADER 3x1
3
1
Project
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
HEADER 17x2
J76
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
CS1
CS0N
WRN
WRN
MODE0
MODE1
MODE2
INITN
PROGRAMN
D12
C16
H24
G10
B12
F12
F19
D18
C15
B15
B11
F13
A16
B19
D19
3_3
1
Sheet
1
10
SC-900fpBGA Communications Platform Evaluation Board
Configuration/JTAG
3_3
DATA[0..7]
DATA0
DAT_OUT
DONE
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
CPU_CS
CPU_CS1
PCM_CLK
PCM-34 Pin CONNECTION
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
VCCJ
RN1C
NC7WZ16-MACO6A/Fairchild TinyLogic
This LED
indicates activity
on TDI.
R207
4_7K/SMT0603
2
7
TCK
3
6
TMS
4
5
TDI
VCCIO1
R209
4_7K/SMT0603
3
2
4_7K/SMT0603
R109
100NF/SMT0603
RN1A
8
TDO
R
5
VCC
D
R84
4_7K/SMT0603
R212
10K/SMT0603
C566
GND
2
5
VCC
GND
2
100NF/SMT0603
INITN indicator will light
if an error occurs during
configuration programming
R105
14
GND
7
C319
4_7K/SMT0603
4_7K/SMT0603
4_7K/SMT0603
VCC
R108
4_7K/SMT0603
100NF/SMT0603
C320
R97
VCCIO1
100NF/SMT0603
R103
100R/SMT0603
4_7K/SMT0603
4_7K/SMT0603
4_7K/SMT0603
5
VCC
2
GND
R104
100R/SMT0603
R106
4_7K/SMT0603
4_7K/SMT0603
R107
4_7K/SMT0603
4_7K/SMT0603
100NF/SMT0603
2
R208
4_7K/SMT0603
R232
10K/SMT0603
TEMP
AD5
TEMP
C318
5
VCC
R110
GND
100R/SMT0603
1
4_7K
4
SW6D
FPGA STATUS
INDICATORS
DONE, INITN
10NF/SMT0603
2
4_7K
8
CPU_CS
5
R210
10K/SMT0603
3
4_7K
RN4A
R213
10K/SMT0603
R211
10K/SMT0603
RN3 A
8
12
4
4_7K
1
470R
1
RN3 C
6
SW6B
9
RN3 B
7
SW6A
10
3
RN3 D
5
SW6C
7
2
470R
7
RN4B
4
3
470R
6
6
4
470R
5
RN4C
37
RN4D
CPU_CS1
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 13. Configuration/JTAG
100NF/SMT0603
A
B
C
3_3
10
9
8
7
6
5
4
3
2
1
100NF/SMT0603
R111
20
19
18
17
16
15
14
13
12
11
100NF/SMT0603
10UF/SM_TANT_B
Q_N
Q
2
3
4
5
J91
R122
1K/SMT0603
2
3
4
5
J92
3_3
10NF/SMT0603
C322
R113
130R/SMT0603
82R/SMT0603
R118
1_OSC_IN_P
1_OSC_IN_N
R117
82R/SMT0603
5
1
1
8
100NF/SMT0603
3_3
R112
130R/SMT0603
Y1
110-93-314-41-001
C323
R121
2_2K/SMT0603
10NF/SMT0603
SMA_901_144_8
C351
100NF/SMT0603
10
20
9
19
18
8
7
17
6
16
15
5
4
14
3
13
2
12
1
11
OPEN
CLOSED
TDA10H0SK1
SW8
+
C333
10UF/SM_TANT_B
1_6R/SMT0603
C332
100NF/SMT0603
C321
R126
100NF/SMT0603
REFCLK_EXT_IN_P_L
REFCLK_EXT_IN_N_L
1
SMA_901_144_8
92
89
88
87
85
43
44
45
86
39
38
C340
41
42
72
91
90
EXB2HV102JV
C339
100NF/SMT0603
REFB-
REFB+
LOCK
TEST1
TEST2
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
RESET
REFA-
REFA+
U19
ispCLK5020-100TQFP
3_3
100NF/SMT0603
C334
FB20
BLM41PG471SN1L
4
C330
GNDD_1
GNDD_2
GNDD_3
GNDD_4
GNDD_5
GNDD_6
GNDD_7
GNDD_8
GNDO_0
GNDO_1
GNDO_2
GNDO_3
GNDO_4
GNDO_5
GNDO_6
GNDO_7
GNDO_8
GNDO_9
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
32
33
34
35
36
37
46
93
6
10
14
18
22
54
58
62
66
70
5
4
9
8
13
12
17
16
21
20
53
52
57
56
61
60
65
64
69
68
100NF/SMT0603
C336
GP_CLOCK1_P
GP_CLOCK1_N
MSA_TXREFCLK_P
MSA_TXREFCLK_N
A_REFCLKP_L
A_REFCLKN_L
10NF/SMT0603 100NF/SMT0603
C329
VCCJ
10UF/SM_TANT_B
C133
MSA_TXREFCLK_P pg.13
MSA_TXREFCLK_N pg.13
A_REFCLKP_L pg.12
A_REFCLKN_L pg.12
+
3_3
C348
10
9
8
7
6
5
4
3
2
1
3_3
R116
10NF/SMT0603
C497
100NF/SMT0603
20
19
18
17
16
15
14
13
12
11
2
3
4
5
3
SMA_901_144_8
C352
100NF/SMT0603
10
20
9
19
8
18
7
17
6
16
5
15
4
14
3
13
2
12
1
11
OPEN CLOSED
TDA10H0SK1
SW7
C343
1_6R/SMT0603
C349
100NF/SMT0603
10UF/SM_TANT_B
J93
+
C496
R124
1K/SMT0603
1
C327
2
3
4
5
R123
2_2K/SMT0603
C344
FB21
10NF/SMT0603
Q_N
Q
J95
3_3
82R/SMT0603
R120
R127
92
89
88
87
85
43
44
45
86
39
38
72
41
42
2
3
4
5
6
8
9
10
INITN
DONE
TCK
TMS
NC
VCC
GND
ispEN_N
TDI
TDO
J98
REFB-
REFB+
LOCK
TEST1
TEST2
PLL_BYPASS
PS0
PS1
GOE
SGATE
REFSEL
OEX
OEY
RESET
REFA-
REFA+
U20
HEADER 8
7
1
ispCLOCK
Download
Connection
RXREFCLK_EXT_IN_N
91
90
EXB2HV102JV
D15
LED-SMT1206_ORANGE
O
RXREFCLK_EXT_IN_P
680R/SMT0603
3_3
C326
2_5
R115
130R/SMT0603
3_3
C325
2_OSC_IN_P
1
SMA_901_144_8
FB18
BLM41PG471SN1L
2_OSC_IN_N
R119
82R/SMT0603
1
8
Y2
110-93-314-41-001
R114
130R/SMT0603
C328
10NF/SMT0603
3
10NF/SMT0603
100NF/SMT0603
BLM41PG471SN1L
10NF/SMT0603
D14
LED-SMT1206_ORANGE
O
680R/SMT0603
3_3
14
C132
3_3
C331
C341
14
VDD
GND
7
C324
13
C335
15
31
GNDA
+
10
74
VCCJ
2_5
C342
10NF/SMT0603
12
RN5E
5
16
1K
RN5A
1
1K
RN5D
4
11
1K
RN5F
6
1K
RN5B
2
1K
RN5G
7
1K
RN5C
3
100NF/SMT0603
4
100NF/SMT0603
10
D
1K
9
1K
RN5H
8
3
7
11
15
19
51
55
59
63
67
TDI
TDO
TMS
TCK
47
71
30
VCCA
14
VDD
7
40
84
73
82
83
13
100NF/SMT0603
14
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_8
VCCO_9
RESERVED1
RESERVED3
RESERVED2
RESERVED4
11
REFVTT
80
95
81
96
2
+
3_3
2
C357
100NF/SMT0603
L10
1UH/SMT1206
ispCLK5020-100TQFP
3_3
100NF/SMT0603
C346
FB23
BLM41PG471SN1L
31
GNDA
GND
16
RN6A
1
15
1K
RN6B
2
1K
RN6C
3
9
1K
RN6H
8
1K
RN6D
4
Date:
Size
Title
B
C338
32
33
34
35
36
37
46
93
6
10
14
18
22
54
58
62
66
70
5
4
9
8
13
12
17
16
21
20
53
52
57
56
61
60
65
64
69
68
C354
C355
C356
100NF/SMT0603
GP_CLOCK2_N
100NF/SMT0603
GP_CLOCK2_P
R130
51R/SMT0603
SMA_901_144_8
J97
1
2
3
4
5
SMA_901_144_8
J96
1
2
3
4
5
R129
51R/SMT0603
SMA_901_144_8
J94
1
2
3
4
5
R128
51R/SMT0603
SMA_901_144_8
J90
1
2
3
4
5
R125
51R/SMT0603
Sheet
1
11
SC-900fpBGA Communications Platform Evaluation Board
Project
C353
MSA_RXREFCLK_P pg.13
MSA_RXREFCLK_N pg.13
SPI4_REFCLK pg.17
URC_PLLT pg.18
URC_PLLC pg.18
100NF/SMT0603
GP_CLOCK1_N
1
A_RXREFCLKP_L pg.12
A_RXREFCLKN_L pg.12
100NF/SMT0603
GP_CLOCK1_P
GP_CLOCK SIGNALS CAN
BE USED AS TRIGGERS
FOR TEST EQUIPMENT
A_RXREFCLKP_L
A_RXREFCLKN_L
URC_PLLT
URC_PLLC
GP_CLOCK2_P
GP_CLOCK2_N
MSA_RXREFCLK_P
MSA_RXREFCLK_N
SPI4_REFCLK
Clock Sources
GNDD_1
GNDD_2
GNDD_3
GNDD_4
GNDD_5
GNDD_6
GNDD_7
GNDD_8
GNDO_0
GNDO_1
GNDO_2
GNDO_3
GNDO_4
GNDO_5
GNDO_6
GNDO_7
GNDO_8
GNDO_9
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
100NF/SMT0603
C350
10NF/SMT0603 100NF/SMT0603
C337
VCCJ
74
VCCJ
VCCD1
VCCD2
NC1
NC2
NC3
NC4
NC5
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
1
2
23
24
25
26
27
28
29
48
49
50
75
76
77
78
79
94
97
98
99
100
1K
12
1K
RN6E
5
1K
RN6F
6
1K
RN6G
7
30
VCCA
5
TDI
TDO
TMS
TCK
84
73
82
83
40
3
7
11
15
19
51
55
59
63
67
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_5
VCCO_6
VCCO_7
VCCO_8
VCCO_9
RESERVED1
RESERVED3
RESERVED2
RESERVED4
REFVTT
80
95
81
96
47
71
VCCD1
VCCD2
NC1
NC2
NC3
NC4
NC5
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
38
1
2
23
24
25
26
27
28
29
48
49
50
75
76
77
78
79
94
97
98
99
100
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 14. Clock Sources
A
B
C
5
A_HDINN0_L
A_HDINP1_L
A_HDINN1_L
A_HDINP2_L
A_HDINN2_L
A_HDINP3_L
A_HDINN3_L
A_HDINP0_R
A_HDINN0_R
A_HDINP1_R
A_HDINN1_R
A_HDINP2_R
A_HDINN2_R
A_HDINP3_R
A_HDINN3_R
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
J136
J133
J131
J127
J125
J123
J121
J119
J117
J115
J113
J111
J109
J107
J102
J104
1
A_HDOUTP0_L
A_HDOUTN0_L
A_HDOUTP1_L
A_HDOUTN1_L
A_HDOUTP2_L
A_HDOUTN2_L
A_HDOUTP3_L
A_HDOUTN3_L
A_HDOUTP0_R
A_HDOUTN0_R
A_HDOUTP1_R
A_HDOUTN1_R
A_HDOUTP2_R
A_HDOUTN2_R
A_HDOUTP3_R
A_HDOUTN3_R
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
1
Rosenberger 32K153-400E3
4
EXTCLKP1I
EXTCLKP1O
EXTCLKP2I
A3
A4
A6
A5
A7
A8
A10
A9
B28
B27
B25
B26
B24
B23
B21
B22
A_HDOUTP0_L
A_HDOUTN0_L
A_HDOUTP1_L
A_HDOUTN1_L
A_HDOUTP2_L
A_HDOUTN2_L
A_HDOUTP3_L
A_HDOUTN3_L
A_HDINP0_R
A_HDINN0_R
A_HDINP1_R
A_HDINN1_R
A_HDINP2_R
A_HDINN2_R
A_HDINP3_R
A_HDINN3_R
NOTE: PLACE
TERMINATIONS
CLOSE TO
DEVICE.
A_RXREFCLKN_R
A_RXREFCLKP_R
A_REFCLKN_R
A_REFCLKP_R
U1A
R143
R136
R144
R142
3
SC-900FPBGA-BOARD1
A_HDOUTP0_R
A_HDOUTN0_R
A_HDOUTP1_R
A_HDOUTN1_R
A_HDOUTP2_R
A_HDOUTN2_R
A_HDOUTP3_R
A_HDOUTN3_R
A_HDINP0_R
A_HDINN0_R
A_HDINP1_R
A_HDINN1_R
A_HDINP2_R
A_HDINN2_R
A_HDINP3_R
A_HDINN3_R
1
1
B30
C30
B1
C1
B29
C29
B2
C2
F17
D16
D17
H17
H18
A17
EXTDONEI
EXTCLKP1I
EXTCLKP2I
EXTDONEO
EXTCLKP1O
EXTCLKP2O
A_REFCLKP_R
A_REFCLKN_R
A_RXREFCLKP_R
A_RXREFCLKN_R
EXTDONEO
EXTCLKP2I
EXTCLKP2O
EXTCLKP1I
EXTCLKP1O
EXTDONEI
A1
B1
D1
E1
A2
B2
D2
E2
A3
B3
D3
E3
A4
B4
D4
E4
J134
Rosenberger 32K153-400E3
J137
Rosenberger 32K153-400E3
1
J129
1
Rosenberger 32K153-400E3
J128
Rosenberger 32K153-400E3
A_REFCLKP_R
A_REFCLKN_R
A_REFCLKP_L
A_REFCLKN_L
A_RXREFCLKP_R
A_RXREFCLKN_R
A_RXREFCLKP_L
A_RXREFCLKN_L
PT38D/EXTDONEO
PT39A/EXTCLKP2I
PT39B/EXTCLKP2O
PT41A/EXTCLKP1I
PT41B/EXTCLKP1O
PT42A/EXTDONEI
SERDES
A_HDOUTP0_L
A_HDOUTN0_L
A_HDOUTP1_L
A_HDOUTN1_L
A_HDOUTP2_L
A_HDOUTN2_L
A_HDOUTP3_L
A_HDOUTN3_L
A_HDINP0_L
A_HDINN0_L
A_HDINP1_L
A_HDINN1_L
A_HDINP2_L
A_HDINN2_L
A_HDINP3_L
A_HDINN3_L
NOTE: PLACE
TERMINATIONS
CLOSE TO
DEVICE.
R141
A28
A27
A25
A26
A24
A23
A21
A22
B3
B4
B6
B5
B7
B8
B10
B9
EXTCLKP2O
A_HDINP0_L
A_HDINN0_L
A_HDINP1_L
A_HDINN1_L
A_HDINP2_L
A_HDINN2_L
A_HDINP3_L
A_HDINN3_L
A_HDOUTP0_R
A_HDOUTN0_R
A_HDOUTP1_R
A_HDOUTN1_R
A_HDOUTP2_R
A_HDOUTN2_R
A_HDOUTP3_R
A_HDOUTN3_R
R135
3
Replace with short if
used as Master
51R/SMT0603
A_HDINP0_L
100 ohm P/N matched differential pairs
J135
J132
J130
J126
J124
J122
J120
J118
J116
J114
J112
J110
J108
J106
J105
2
2
2
2
2
2
2
2
OPEN/SMT0603
OPEN/SMT0603
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
51R/SMT0603
2
2
2
2
2
51R/SMT0603
51R/SMT0603
SC-900FPBGA
2
2
39
2
J103
4
C1
C2
C3
C4
C1
C2
C3
C4
A_REFCLKN_L
ZPACK
A1
B1
D1
E1
A2
B2
D2
E2
A3
B3
D3
E3
A4
B4
D4
E4
ZP1
R139
A_REFCLKP_L pg.11
A_REFCLKN_L pg.11
NOTE: PLACE
R140 TERMINATIONS
CLOSE TO
DEVICE.
A_RXREFCLKP_L
A_RXREFCLKN_L
A_REFCLKP_L
51R/SMT0603
D
5
51R/SMT0603
2
2
R137
51R/SMT0603
Date:
Size
Title
B
R138
Sheet
1
12
SC-900fpBGA Communications Platform Evaluation Board
Project
SERDES
NOTE: PLACE
TERMINATIONS
CLOSE TO
DEVICE.
A_RXREFCLKP_L pg.11
A_RXREFCLKN_L pg.11
1
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 15. SERDES
51R/SMT0603
A
B
C
D
R149
1K_ADJ/SMT3MM
R148
C358
pg.8 VREF_RIGHT
R147
10NF/SMT0603
5
VREF_RIGHT
MSA_VREF1_2
1
3
5
1
3
5
J138
2
4
6
HEADER 3x2
2
4
6
TP13
TP14
TP12
TP11
R145
1K/SMT0603
TXMCLK_P
TXMCLK_N
RXMCLK_P
RXMCLK_N
MSA1D
megArray-84500-001
1 C28
1 C29
1 C13
1 C14
R150
1K/SMT0603
HEADER 14
VCCAUX
VREF_RIGHT pg.8
R146
1K_ADJ/SMT3MM
C359
10NF/SMT0603
VREF_RIGHT
MSA_VREF1_3
1
2
MSA_VREF1_2
J139
C360
DIGITAL OUTPUTS
300-pin
MSA
ANALOG SIGNALS
MSA_VREF1_3
TXPCLK_N
TXPCLK_P
TXPICLK_N
TXPICLK_P
TXRESET
RXRESET
I2CCLOCK
I2CDATA
RXMUTEDOUT
RXLCKREF
RXMCLKSEL
TXSKEWSEL0
TXSKEWSEL1
TXPICLKSEL
I2CAD0
I2CAD1
I2CAD2
MOD_RESET
TXPHSADJ0
TXPHSADJ1
TXLINETIMSEL
LLOOPENB
LSTUNE2
LSTUNE1
LSTUNE0
DLOOPENB
RXREFSEL
LSENABLE
TXREFSEL
RXRATESEL1
RXRATESEL0
TXRATESEL1
TXRATESEL0
RXMUTEPOCLK
RXMUTEMCLK
TXFIFO RES
K24
K6
K15
K18
B6
B9
B12
B18
B21
B27
D3
D6
D9
D12
D24
D27
H30
H27
H24
H21
H18
H6
F15
F21
F30
J3
K3
J21
K21
K9
K12
K27
T26
M25
AG29
AG28
E28
D28
4
TXRESET
RXRESET
I2CCLOCK
I2CDATA
RXMUTEDOUT
RXLCKREF
RXMCLKSEL
TXSKEWSEL0
TXSKEWSEL1
TXPICLKSEL
I2CAD0
I2CAD1
I2CAD2
MOD-RESET
TXPHSADJ0
TXPHSADJ1
TXLINETIMSEL
LLOOPENB
LSTUNE2
LSTUNE1
LSTUNE0
DLOOPENB
RXREFSEL
LSENABLE
TXREFSEL
RXRATESEL1
RXRATESEL0
TXRATESEL1
TXRATESEL0
RXMUTEPOCLK
RXMUTEMCLK
TXFIFO_RES
PR34C/VREF1_3
SC-900FPBGA-BOARD1
D29
D30
G28
F28
G27
H27
L27
M27
E29
E30
F29
G29
H30
J30
K30
L30
P28
R28
N28
N29
P29
R29
T28
U28
M29
N30
T29
U29
P30
R30
U27
V27
MSA_TX_P_00
MSA_TX_N_00
MSA_TX_P_01
MSA_TX_N_01
MSA_TX_P_02
MSA_TX_N_02
MSA_TX_P_03
MSA_TX_N_03
MSA_TX_P_04
MSA_TX_N_04
MSA_TX_P_05
MSA_TX_N_05
MSA_TX_P_06
MSA_TX_N_06
MSA_TX_P_07
MSA_TX_N_07
MSA_TX_P_08
MSA_TX_N_08
MSA_TX_P_09
MSA_TX_N_09
MSA_TX_P_10
MSA_TX_N_10
MSA_TX_P_11
MSA_TX_N_11
MSA_TX_P_12
MSA_TX_N_12
MSA_TX_P_13
MSA_TX_N_13
MSA_TX_P_14
MSA_TX_N_14
MSA_TX_P_15
MSA_TX_N_15
To XPNDR
TXPCLK_N
TXPCLK_P
TXREFCLK_N
TXREFCLK_P
TXPICLK_N
TXPICLK_P
300-pin
MSA
megArray-84500-001
TXDIN0P
TXDIN0N
TXDIN1P
TXDIN1N
TXDIN2P
TXDIN2N
TXDIN3P
TXDIN3N
TXDIN4P
TXDIN4N
TXDIN5P
TXDIN5N
TXDIN6P
TXDIN6N
TXDIN7P
TXDIN7N
TXDIN8P
TXDIN8N
TXDIN9P
TXDIN9N
TXDIN10P
TXDIN10N
TXDIN11P
TXDIN11N
TXDIN12P
TXDIN12N
TXDIN13P
TXDIN13N
TXDIN14P
TXDIN14N
TXDIN15P
TXDIN15N
MSA1B
A16
A17
A19
A20
A22
A23
A25
A26
C16
C17
C19
C20
C22
C23
C25
C26
E16
E17
E19
E20
E22
E23
E25
E26
G16
G17
G19
G20
G22
G23
G25
G26
TXPICLK_N
MSA_TXREFCLK_P
MSA_TXREFCLK_N
A28
A29
TX_REF_CLK
TXPICLK_P
G29
TXPCLK_N
E29
G28
TXPCLK_P
E28
MSA_TXREFCLK_P pg.11
MSA_TXREFCLK_N pg.11
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
TXPHSADJ0
TXPHSADJ1
TXLINETIMSEL
LLOOPENB
LSTUNE2
LSTUNE1
LSTUNE0
DLOOPENB
RXREFSEL
LSENABLE
TXREFSEL
RXRATESEL1
RXRATESEL0
TXRATESEL1
TXRATESEL0
RXMUTEPOCLK
RXMUTEMCLK
TXFIFO_RES
10
9
8
7
6
5
4
3
2
1
RXMUTEDOUT
RXLCKREF
RXMCLKSEL
TXSKEWSEL0
TXSKEWSEL1
TXPICLKSEL
I2CAD0
I2CAD1
I2CAD2
MOD-RESET
10
20
9
19
8
18
7
17
6
16
15
5
4
14
13
3
2
12
11
1
OPEN CLOSED
TDA10H0SK1
SW13
10
20
9
19
8
18
7
17
6
16
5
15
4
14
3
13
2
12
1
11
OPEN
CLOSED
TDA10H0SK1
SW11
10
20
9
19
18
8
7
17
6
16
15
5
4
14
3
13
2
12
1
11
OPEN
CLOSED
TDA10H0SK1
SW9
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
3_3
3
3_3
OBSERVE 300-PIN MSA KEEPOUT REGION
PR17A/URC_DLLT_IN_C/URC_DLLT_FB_D/TXD_0P
PR17B/URC_DLLC_IN_C/URC_DLLC_FB_D/TXD_0N
PR18A/URC_DLLT_IN_D/URC_DLLT_FB_C/TXD_1P
PR18B/URC_DLLC_IN_D/URC_DLLC_FB_C/TXD_1N
PR20A/TXD_2P
PR20B/TXD_2N
PR21A/TXD_3P
PR21B/TXD_3N
PR22A/TXD_4P
PR22B/TXD_4N
PR25A/TXD_5P
PR25B/TXD_5N
PR26A/PCLKT2_1/TXD_6P
PR26B/PCLKC2_1/TXD_6N
PR27A/PCLKT2_0/TXD_7P
PR27B/PCLKC2_0/TXD_7N
PR29A/PCLKT3_0/TXD_8P
PR29B/PCLKC3_0/TXD_8N
PR30A/TXD_9P
PR30B/TXD_9N
PR31A/TXD_10P
PR31B/TXD_10N
PR34A/TXD_11P
PR34B/TXD_11N
PR35A/TXD_12P
PR35B/TXD_12N
PR36A/TXD_13P
PR36B/TXD_13N
PR38A/TXD_14P
PR38B/TXD_14N
PR39A/TXD_15P
PR25C/VREF1_2
PR39B/TXD_15N
PB69D/LRC_DLLC_IN_D/LRC_DLLC_FB_C/SFI_REFCLK_N
PB69C/LRC_DLLT_IN_D/LRC_DLLT_FB_C/SFI_REFCLK_P
PR16B/URC_PLLC_IN_A/URC_PLLC_FB_B/SFI_TXCLK_N
SC-900FPBGA
VCCAUX
1K/SMT0603
1K/SMT0603
REG
C361
VCCIO/2
100NF/SMT0603
ADJUST
RXPOCLK_P
R151
I2CCLOCK
I2CDATA
RXPOCLK_N
R152
R26
V25
M26
Y25
U25
R25
PR42D/DIFFR_3
D24
D23
D22
D21
D20
D19
D18
ERRORED WHEN LIT
SFI4/XSBI
RX
U1O
2
D26
2
D25
SC-900FPBGA-BOARD1
D27
Date:
Size
Title
B
PR40A/RXD_0P
PR40B/RXD_0N
PR42A/RXD_1P
PR42B/RXD_1N
PR43A/RXD_2P
PR43B/RXD_2N
PR43C/RXD_3P
PR43D/RXD_3N
PR44A/RXD_4P
PR44B/RXD_4N
PR47A/RXD_5P
PR47B/RXD_5N
PR47C/RXD_6P
PR47D/RXD_6N
PR48A/RXD_7P
PR48B/RXD_7N
PR49A/RXD_8P
PR49B/RXD_8N
PR51A/RXD_9P
PR48C/I2CCLOCK
PR51B/RXD_9N
PR42C/I2CDATA
PR52A/RXD_10P
PR52B/RXD_10N
PR53A/RXD_11P
PR53B/RXD_11N
PR55A/RXD_12P
PR55B/RXD_12N
PR55C/LRC_DLLT_IN_E/LRC_DLLT_FB_F/RXD_13P
PR55D/LRC_DLLC_IN_E/LRC_DLLC_FB_F/RXD_13N
PR56A/RXD_14P
PR56B/RXD_14N
PR57C/LRC_PLLT_IN_B/LRC_PLLT_FB_A/RXD_15P
PR57D/LRC_PLLC_IN_B/LRC_PLLC_FB_A/RXD_15N
PR25D/DIFFR_2
PR29D/PCLKC3_1
PR29C/PCLKT3_1
D17
1K_1%/SMT0603
D16
LED-SMT1206_RED
R155
SELECTING VREF VOLTAGES
LED-SMT1206_RED
R156
100NF/SMT0603
NOTE: ROUTE DATA ALONG
WITH CLOCK SIGNAL NAMED
SFI_TX_[P/N]_CLK ON
LED-SMT1206_RED
R157
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2" Maximum
All traces length matched
50 ohms
Refer to 10Gb Transponder
Reference Document
www.300pinmsa.org
for PCB layout guidelines
LED-SMT1206_RED
R158
J1
J29
F3
F9
F18
D18
D21
B3
J28
B24
J19
H3
J10
J11
SFI4/XSBI
TX
PR16A/URC_PLLT_IN_A/URC_PLLT_FB_B/SFI_TXCLK_P
LED-SMT1206_RED
R159
SC-900FPBGA
U1P
R160
4
3
SW10 RX_RESET
SW12
4
TX_RESET
3
IN2
IN1
U21
3_3
OUT1
OUT2
TXRESET
RXRESET
MSA_RXREFCLK_P
MSA_RXREFCLK_N
A13
A14
RX_REF_CLK
RXPOCLK_P
RXPOCLK_N
E13
E14
NOTE: ROUTE DATA ALONG
WITH CLOCK SIGNAL NAMED
SFI_RX_[P/N]_CLK ON
1
Sheet
1
13
SC-900fpBGA Communications Platform Evaluation Board
Project
4
6
MAX6817
R153
R154
RXREFCLK_N
RXREFCLK_P
RXPOCLK_N
RXPOCLK_P
300-pin
MSA
megArray-84500-001
RXDOUT0P
RXDOUT0N
RXDOUT1P
RXDOUT1N
RXDOUT2P
RXDOUT2N
RXDOUT3P
RXDOUT3N
RXDOUT4P
RXDOUT4N
RXDOUT5P
RXDOUT5N
RXDOUT6P
RXDOUT6N
RXDOUT7P
RXDOUT7N
RXDOUT8P
RXDOUT8N
RXDOUT9P
RXDOUT9N
RXDOUT10P
RXDOUT10N
RXDOUT11P
RXDOUT11N
RXDOUT12P
RXDOUT12N
RXDOUT13P
RXDOUT13N
RXDOUT14P
RXDOUT14N
RXDOUT15P
RXDOUT15N
MSA1A
A1
A2
A4
A5
A7
A8
A10
A11
C1
C2
C4
C5
C7
C8
C10
C11
E1
E2
E4
E5
E7
E8
E10
E11
G1
G2
G4
G5
G7
G8
G10
G11
Transponder Intf
Momentary Switch
B3F-1150
2
1
3
1
NOTE: ROUTE DATA ALONG
WITH CLOCK SIGNAL NAMED
SFI_RX_[P/N]_CLK
MSA_RX_P_00
MSA_RX_N_00
MSA_RX_P_01
MSA_RX_N_01
MSA_RX_P_02
MSA_RX_N_02
MSA_RX_P_03
MSA_RX_N_03
MSA_RX_P_04
MSA_RX_N_04
MSA_RX_P_05
MSA_RX_N_05
MSA_RX_P_06
MSA_RX_N_06
MSA_RX_P_07
MSA_RX_N_07
MSA_RX_P_08
MSA_RX_N_08
MSA_RX_P_09
MSA_RX_N_09
MSA_RX_P_10
MSA_RX_N_10
MSA_RX_P_11
MSA_RX_N_11
MSA_RX_P_12
MSA_RX_N_12
MSA_RX_P_13
MSA_RX_N_13
MSA_RX_P_14
MSA_RX_N_14
MSA_RX_P_15
MSA_RX_N_15
FROM XPNDR
Momentary Switch
B3F-1150
2
1
R27
T27
V28
W28
T30
U30
V26
W26
V29
W29
V30
W30
Y27
W27
Y30
AA30
AA25
AB25
AD30
AE30
AB28
AC28
AD29
AE29
AF30
AG30
AB26
AC26
AC27
AD28
AD26
AC25
C362
Used to adjust the Input Voltage Reference
for input buffers
R161
100NF/SMT0603
3
4_7K/SMT0603
4
R162
RXTRACE
TXTRACE
RXPOWMON
RXSIGMON
LSBIASMON
LSPOWMON
LSTEMPMON
RXDTV
LSWAVMON
LSTWEAK
MODBIASMON
APDTEMPMON
APS_SENSE
APS_SET
ALM_INT
TXALM_INT
RXALM_INT
TXFIFOERR
RXPOWALM
RXSIGALM
LSBIASALM
LSTEMPALM
RXLOCKERR
TXLOCKERR
LSPOWALM
MODBIASALM
H15
J16
J14
K30
F6
F12
F24
F27
B15
B30
D30
J20
ALM_INT
TXALM_INT
RXALM_INT
TXFIFOERR
RXPOWALM
RXSIGALM
LSBIASALM
LSTEMPALM
RXLOCKERR
TXLOCKERR
LSPOWALM
MODBIASALM
RXSIGALM
220R/SMT0603
ALM_INT
220R/SMT0603
TXALM_INT
220R/SMT0603
RXALM_INT
220R/SMT0603
RXPOWALM
220R/SMT0603
MODBIASALM
220R/SMT0603
LSPOWALM
220R/SMT0603
LSTEMPALM
220R/SMT0603
1K_1%/SMT0603
LED-SMT1206_RED
R
R163
4_7K/SMT0603
5
220R/SMT0603
TXFIFOERR
220R/SMT0603
RXLOCKERR
220R/SMT0603
TXLOCKERR
220R/SMT0603
5
VCC
LSBIASALM
R
LED-SMT1206_RED
R
LED-SMT1206_RED
R
LED-SMT1206_RED
R
LED-SMT1206_RED
R
R164
R
LED-SMT1206_GREEN
R
LED-SMT1206_GREEN
R
R166
R
R165
G
GND
40
G
2
MSA_RXREFCLK_P pg.11
of
19
MSA_RXREFCLK_N pg.11
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 16. Transponder Interface
IN LOCK WHEN LIT
A
B
C
C379
NEG5V_DIG_ON_BRD
APS_DIGITAL_ON_BRD
5V_ANALOG_ON_BRD
NEG5_ANA_ON_BRD
3_3V_ANALOG_ON_BRD
3_3V_DIG_ON_BRD
1
4
7
10
13
16
220PF/0603 Kemet C0603224Z3ACTU
82K/SMT0603
C392
5
HEADER 6x3
J141A
3_3
1
1
1
4
2
U22
REF
FREQ
GND
C364
MAX1846
FB
PGND
CS
EXT
5
7
8
9
L15
J141B
ELKE100FA/SMT3218
ELKE100FA/SMT3218
ELKE100FA/SMT3218
ELKE100FA/SMT3218
ELKE100FA/SMT3218
2
5
8
11
14
17
L14
L13
L12
C388
100NF/SMT0603
3
C395
390PF Kemet C0603C391K5RACTU
L16
1
1
HEADER 6x3
3_3
5_0_IN
NEG5V_DIG_ON_BRD
1_8
R170
10
IN
1
VL
COMP
3
680UF/ALCAP
22K/SMT0603
R167
C401
C431
NEG5_ANA_ON_BRD
+
1000PF Kemet C0603C102K5RACTU
APS_DIGITAL_ON_BRD
3
3
3
C447
C449
C451
NEG5_2V_DIG
APS_DIGITAL
5V_ANALOG
NEG5_2V_ANA
3_3V_ANALOG
3_3V_DIG
+
3_3V_DIG_ON_BRD
+
3_3V_ANALOG_ON_BRD
+
5V_ANALOG_ON_BRD
6.8UH/UP4-6R8
HEADER 6x3
J141C
40_2K 1%/SMT0603
3
6
9
12
15
18
NEG5V_DIG_EXT
APS_DIGITAL_EXT
5V_ANALOG_EXT
NEG5V_ANA_EXT
3_3V_ANALOG_EXT
3_3V_DIG_EXT
J140
680UF/ALCAP
C372
1
2
3
4
5
6
7
J2
J4
J5
J6
J7
J8
J9
J12
J13
J15
J17
J18
J22
J23
J24
J25
J26
J27
J30
H9
H12
G13
G14
D15
Q37
R173
220R/SMT0603
EXTERNAL
MSA
POWER
1
10K/SMT0603
R179
LED-SMT1206_GREEN
D34
5_0_IN
1.8V
2N2222/SOT23
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NEG5_2V_ANA
megArray-84500-001
TRM BLK ED120/7DS
TB4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HEADER 24
R171
10K_1%/SMT0603
R169
4
R168
0.02R 0.5W/DALE WSL-2010-R020F
5V_ANALOG
K1
K2
K16
K17
300-pin
MSA
R175
165R/SMT0603
R176
165R/SMT0603
R177
220R/SMT0603
D32
LED-SMT1206_GREEN
NEG5_2V_ANA
3_3V_DIG
LED-SMT1206_GREEN
D31
NEG 5V
ANALOG
3.3V
DIGITAL
LED-SMT1206_GREEN
D30
3_3V_ANALOG
3
MSA POWER SUPPLY GOOD
R174
220R/SMT0603
LED-SMT1206_GREEN
D29
5V_ANALOG
5V
3.3V
ANALOG ANALOG
NEG5_2V_DIG
R178
220R/SMT0603
D33
LED-SMT1206_GREEN
NEG5_2V_DIG
NEG 5V
DIGITAL
5V_ANALOG
APS_DIGITAL
5V_ANALOG
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
5V_ANALOG
5V_ANALOG
5V_ANALOG
5V_ANALOG
5V_ANALOG
5V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
3_3V_DIG
1
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
NEG5_2V_DIG
10NF/SMT0603
10NF/SMT0603
C391
APS_DIGITAL
C417
C433
3
G3
G6
G9
G12
G15
G18
G21
G24
G27
G30
E3
E6
E9
E12
E15
E18
E21
E24
E27
E30
D1
D2
D4
D5
D7
D8
D10
D11
D13
D14
D16
D17
D19
D20
D22
D23
D25
D26
D28
D29
C3
C6
C9
C12
C15
C18
C21
C24
C27
C30
B1
B2
B4
B5
B7
B8
B10
B11
B13
B14
B16
B17
B19
B20
B22
B23
B25
B26
C396
C403
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
2
100NF/SMT0603
R172
39K/SMT0603
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C389
C374
C397
C404
C418
C434
MSA1C
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
L11
C368
C375
C381
C405
C419
C435
NEG5V_DIG_ON_BRD
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
Date:
Size
Title
100NF/SMT0603
D
82NF/0603 Kemet C06033C824K8PACTU
C369
C376
C382
C406
C420
B
C436
6
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
B540C-13
C421
Sheet
1
14
SC-900fpBGA Communications Platform Evaluation Board
Project
300-Pin MSA Power
C437
NEG5V
100NF/SMT0603
100NF/SMT0603
D28
C422
C438
5
6
7
8
C424
FDS6375
10NF/SMT0603
10NF/SMT0603
2
2
2
2
2
C390
C394
C383
C407
10NF/SMT0603
10NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C398
C409
C423
C439
680UF/ALCAP
C365
C450
100NF/SMT0603
100NF/SMT0603
C366
C373
C371
C378
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
C367
C393
C370
C377
C384
C408
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
C400
C430
C446
C448
10NF/SMT0603
Q36
C440
1UF/SMT1206
1UF/SMT1206
1UF/SMT1206
1UF/SMT1206
1UF/SMT1206
C410
10NF/SMT0603
10NF/SMT0603
C385
10NF/SMT0603
10NF/SMT0603
10NF/SMT0603
10UF/SM_TANT_B
10UF/SM_TANT_B
10UF/SM_TANT_B
10UF/SM_TANT_B
10UF/SM_TANT_B
C425
1
2
3
4
G
3
2
C426
+
APS_DIGITAL
100NF/SMT0603
+
C441
C363
100NF/SMT0603
5V_ANALOG
5V_ANALOG
5V_ANALOG
5V_ANALOG
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
NEG5_2V_ANA
10NF/SMT0603
0.47UF/0603 Kemet C0603C472K5RACTU
C442
3_3V_ANALOG
K29
K28
K26
K25
K14
K13
K11
K10
G
C427
K4
K5
K7
K8
K19
K20
K22
K23
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
NEG5_2V_DIGI
100NF/SMT0603
5_0_IN
C443
3_3V_DIG
F29
F28
F26
F25
F14
F13
F11
F10
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
100NF/SMT0603
2
10NF/SMT0603
3
100NF/SMT0603
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
3_3V_ANALOG
G
C411
100NF/SMT0603
C412
C386
100NF/SMT0603
10NF/SMT0603
C413
C399
10NF/SMT0603
C387
100NF/SMT0603
100NF/SMT0603
C414
C428
F4
F5
F7
F8
F19
F20
F22
F23
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
ANALOG_GND
H23
H22
H20
H19
H17
H16
H14
H13
H11
H10
H8
H7
C429
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
3_3V_DIGITAL
FRAME_GND
FRAME_GND
FRAME_GND
FRAME_GND
FRAME_GND
FRAME_GND
FRAME_GND
FRAME_GND
10NF/SMT0603
APS_DIGITAL
H29
H28
H26
H25
H5
H4
H2
H1
C415
C380
C402
C416
C432
100NF/SMT0603
F1
F2
F16
F17
G
10NF/SMT0603
C444
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
APS_DIGITAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A30
A27
A24
A21
A18
A15
A12
A9
A6
A3
B29
B28
G
+
41
G
100NF/SMT0603
C445
4
100NF/SMT0603
+
5
10NF/SMT0603
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 17. 300-Pin MSA Power
A
B
1
3
5
2
4
6
J147
MC_VREF_4
5
J145
R187
MemIntf_DQS[0..7]
R183
0R/SMT0603
MC_VREF_5
MC_VREF_4
MemIntf_RAS#
MemIntf_CAS#
MemIntf_WE#
MemIntf_K
MemIntf_K#
MemIntf_DQS0
MemIntf_DQS1
MemIntf_DQS2
MemIntf_DQS3
MemIntf_DQS4
MemIntf_DQS5
MemIntf_DQS6
MemIntf_DQS7
R180
51R/SMT0603
R199
0R/SMT0603
AH13
AG19
AE24
AJ1
AF4
AE5
AK24
AK25
AH10
AF13
AJ11
AK8
AK20
AF18
AJ20
AK22
AH1
MemIntf_A0 AG3
MemIntf_A1 AH2
MemIntf_A2 AD6
MemIntf_A3 AJ2
MemIntf_A4 AK2
MemIntf_A5 AD7
MemIntf_A6 AD8
MemIntf_A7 AF7
MemIntf_A8 AF6
MemIntf_A9 AH4
MemIntf_A10 AG5
MemIntf_A11 AF8
MemIntf_A12 AG8
4
ADJUST
VCCIO/2
REG
1
2
SELECTING VREF VOLTAGES
1K_ADJ/SMT3MM
R185
2
3
4
5
1
SMA_901_144_8
R182
VCCIO18
MemIntf_DQ63
MemIntf_DQ62
MemIntf_DQ61
MemIntf_DQ60
MemIntf_DQ59
MemIntf_DQ58
MemIntf_DQ57
MemIntf_DQ56
MemIntf_DQ55
MemIntf_DQ54
MemIntf_DQ53
MemIntf_DQ52
MemIntf_DQ51
MemIntf_DQ50
MemIntf_DQ49
MemIntf_DQ48
MemIntf_DQ47
MemIntf_DQ46
MemIntf_DQ45
MemIntf_DQ44
MemIntf_DQ43
MemIntf_DQ42
MemIntf_DQ41
MemIntf_DQ40
MemIntf_DQ39
MemIntf_DQ38
MemIntf_DQ37
MemIntf_DQ36
MemIntf_DQ35
MemIntf_DQ34
MemIntf_DQ33
MemIntf_DQ32
MemIntf_DQ31
MemIntf_DQ30
MemIntf_DQ29
MemIntf_DQ28
MemIntf_DQ27
MemIntf_DQ26
MemIntf_DQ25
MemIntf_DQ24
MemIntf_DQ23
MemIntf_DQ22
MemIntf_DQ21
MemIntf_DQ20
MemIntf_DQ19
MemIntf_DQ18
MemIntf_DQ17
MemIntf_DQ16
MemIntf_DQ15
MemIntf_DQ14
MemIntf_DQ13
MemIntf_DQ12
MemIntf_DQ11
MemIntf_DQ10
MemIntf_DQ9
MemIntf_DQ8
MemIntf_DQ7
MemIntf_DQ6
MemIntf_DQ5
MemIntf_DQ4
MemIntf_DQ3
MemIntf_DQ2
MemIntf_DQ1
MemIntf_DQ0
Used to adjust the Input Voltage Reference
for SSTL input buffers
2
4
6
VREF_BOTTOM
HEADER 3x2
1
3
5
VREF_BOTTOM pg.8
MC_VREF_5
pg.8
194
192
182
180
191
189
181
179
176
174
160
158
175
173
159
157
154
152
142
140
153
151
143
141
136
134
126
124
137
135
125
123
76
74
64
62
75
73
63
61
58
56
46
44
57
55
45
43
38
36
22
20
37
35
25
23
16
14
6
4
19
17
7
5
OBSERVE FUTURE PLUS KEEPOUT REGION
R186
1K_ADJ/SMT3MM
R184
R181
VCCIO18
MemIntf_DQS0
MemIntf_DM7
MemIntf_DM6
MemIntf_DM5
MemIntf_DM4
MemIntf_DM3
MemIntf_DM2
MemIntf_DM1
MemIntf_DM0
MemIntf_CE1#
MemIntf_CE0#
MemIntf_K#_COPY
MemIntf_K_COPY
MemIntf_K#
MemIntf_K
MemIntf_CAS#
MemIntf_BA1
MemIntf_BA0
MemIntf_A12
MemIntf_A11
MemIntf_A10
MemIntf_A9
MemIntf_A8
MemIntf_A7
MemIntf_A6
MemIntf_A5
MemIntf_A4
MemIntf_A3
MemIntf_A2
MemIntf_A1
MemIntf_A0
MemIntf_DQS1
MemIntf_DQS2
MemIntf_DQS3
MemIntf_DQS4
MemIntf_DQS5
MemIntf_DQS6
MemIntf_DQS7
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
PB3B/LLC_PLLC_IN_A/LLC_PLLC_FB_B/MC_RAS#
PB3C/LLC_DLLT_IN_C/LLC_DLLT_FB_D/MC_CAS#
PB3D/LLC_DLLC_IN_C/LLC_DLLC_FB_D/MC_WE#
PB52A/PCLKT4_3/MC_K
PB52B/PCLKC4_3/MC_K#
PB20A/PCLKT5_3/MC_DQS0
PB20C/PCLKT5_4/MC_DQS1
PB23A/PCLKT5_0/MC_DQS2
PB24A/PCLKT5_1/MC_DQS3
PB46A/PCLKT4_2/MC_DQS4
PB47A/PCLKT4_1/MC_DQS5
PB49A/PCLKT4_0/MC_DQS6
PB51A/PCLKT4_5/MC_DQS7
SC-900FPBGA-BOARD1
PB23D/VREF2_5/MC_VREF1
PB49C/VREF2_4/MC_VREF2
PB67C/VREF1_4
MemIntf_DM[0..7]
3
SC-900FPBGA
3
Memory
Controller
PB3A/LLC_PLLT_IN_A/LLC_PLLT_FB_B/MC_REFCLK
PB4A/LLC_DLLT_IN_D/LLC_DLLT_FB_C/MC_ADDR0
PB4B/LLC_DLLC_IN_D/LLC_DLLC_FB_C/MC_ADDR1
PB4C/MC_ADDR2
PB5A/MC_ADDR3
PB5B/MC_ADDR4
PB5C/MC_ADDR5
PB5D/VREF1_5/MC_ADDR6
PB7A/MC_ADDR7
PB7B/MC_ADDR8
PB8A/MC_ADDR9
PB8B/MC_ADDR10
PB9A/MC_ADDR11
PB9B/MC_ADDR12
U1J
MemIntf_ODT1
MemIntf_ODT0
AK7
AK6
PB21B/PCLKC5_5/MC_ODT_1
PB21A/PCLKT5_5/MC_ODT_0
MemIntf_CS0#
MemIntf_CS1#
MemIntf_K_COPY
MemIntf_K#_COPY
AJ3
AH3
AG26
AF27
PB11B/MC_CS0#
PB11A/MC_CS1#
PB65A/MC_CS2#
PB65B/MC_CS3#
MemIntf_DM7
MemIntf_DM6
MemIntf_DM5
MemIntf_DM4
MemIntf_DM3
MemIntf_DM2
MemIntf_DM1
MemIntf_DM0
AG21
AJ21
AK19
AK16
AH12
AJ12
AK5
AK3
MemIntf_BA0
MemIntf_BA1
AF9
AE10
PB11C/MC_BA0
PB11D/MC_BA1
PB55A/MC_DM7
PB49B/PCLKC4_0/MC_DM6
PB41B/MC_DM5
PB37A/MC_DM4
PB31A/MC_DM3
PB23B/PCLKC5_0/MC_DM2
PB16B/MC_DM1
PB12A/MC_DM0
200-Pin SODIMM
C581
MemIntf_CS1#
MemIntf_CS0#
MemIntf_RAS#
MemIntf_ODT1
MemIntf_ODT0
CN1A
MemIntf_A[0:12]
C461
PB59B/MC_DQ63
PB59A/MC_DQ62
PB57B/MC_DQ61
PB57A/MC_DQ60
PB56C/MC_DQ59
PB56B/MC_DQ58
PB56A/MC_DQ57
PB55B/MC_DQ56
PB53B/MC_DQ55
PB53A/MC_DQ54
PB52D/PCLKC4_4/MC_DQ53
PB52C/PCLKT4_4/MC_DQ52
PB51D/MC_DQ51
PB51C/DIFFR_4/MC_DQ50
PB51B/PCLKC4_5/MC_DQ49
PB49D/MC_DQ48
PB47B/PCLKC4_1/MC_DQ47
PB46B/PCLKC4_2/MC_DQ46
PB43B/MC_DQ45
PB43A/MC_DQ44
PB42D/MC_DQ43
PB42C/MC_DQ42
PB42B/MC_DQ41
PB42A/MC_DQ40
PB41A/MC_DQ39
PB38D/MC_DQ38
PB39B/MC_DQ37
PB39A/MC_DQ36
PB38C/MC_DQ35
PB38B/MC_DQ34
PB38A/MC_DQ33
PB37B/MC_DQ32
PB35A/MC_DQ31
PB33B/MC_DQ30
PB33A/MC_DQ29
PB32B/MC_DQ28
PB32A/MC_DQ27
PB31D/MC_DQ26
PB31C/MC_DQ25
PB31B/MC_DQ24
PB29B/MC_DQ23
PB29A/MC_DQ22
PB28B/MC_DQ21
PB28A/MC_DQ20
PB25B/PCLKC5_2/MC_DQ19
PB25A/PCLKT5_2/MC_DQ18
PB24B/PCLKC5_1/MC_DQ17
PB23C/MC_DQ16
PB21D/MC_DQ15
PB21C/DIFFR_5/MC_DQ14
PB20D/PCLKC5_4/MC_DQ13
PB20B/PCLKC5_3/MC_DQ12
PB19B/MC_DQ11
PB19A/MC_DQ10
PB17B/MC_DQ9
PB17A/MC_DQ8
PB16A/MC_DQ7
PB15D/MC_DQ6
PB15C/MC_DQ5
PB15B/MC_DQ4
PB15A/MC_DQ3
PB13B/MC_DQ2
PB13A/MC_DQ1
PB12B/MC_DQ0
PB64B/MC_DQ71
PB64A/MC_DQ70
AH25
AH24
AE23
AD23
AH21
AH23
AH22
AG22
AF21
AE21
AE20
AE19
AH20
AH19
AK23
AF19
AG18
AK21
AJ19
AJ18
AG17
AF17
AH18
AH17
AK18
AF16
AG16
AH16
AE16
AJ17
AJ16
AK17
AK14
AJ15
AJ14
AK13
AK12
AE15
AD15
AJ13
AG15
AH15
AK11
AK10
AG14
AH14
AK9
AG13
AF15
AF14
AE14
AH11
AJ8
AJ7
AJ6
AJ5
AK4
AE13
AE12
AH8
AH7
AF10
AE11
AJ4
MemIntf_DQ63
MemIntf_DQ62
MemIntf_DQ61
MemIntf_DQ60
MemIntf_DQ59
MemIntf_DQ58
MemIntf_DQ57
MemIntf_DQ56
MemIntf_DQ55
MemIntf_DQ54
MemIntf_DQ53
MemIntf_DQ52
MemIntf_DQ51
MemIntf_DQ50
MemIntf_DQ49
MemIntf_DQ48
MemIntf_DQ47
MemIntf_DQ46
MemIntf_DQ45
MemIntf_DQ44
MemIntf_DQ43
MemIntf_DQ42
MemIntf_DQ41
MemIntf_DQ40
MemIntf_DQ39
MemIntf_DQ38
MemIntf_DQ37
MemIntf_DQ36
MemIntf_DQ35
MemIntf_DQ34
MemIntf_DQ33
MemIntf_DQ32
MemIntf_DQ31
MemIntf_DQ30
MemIntf_DQ29
MemIntf_DQ28
MemIntf_DQ27
MemIntf_DQ26
MemIntf_DQ25
MemIntf_DQ24
MemIntf_DQ23
MemIntf_DQ22
MemIntf_DQ21
MemIntf_DQ20
MemIntf_DQ19
MemIntf_DQ18
MemIntf_DQ17
MemIntf_DQ16
MemIntf_DQ15
MemIntf_DQ14
MemIntf_DQ13
MemIntf_DQ12
MemIntf_DQ11
MemIntf_DQ10
MemIntf_DQ9
MemIntf_DQ8
MemIntf_DQ7
MemIntf_DQ6
MemIntf_DQ5
MemIntf_DQ4
MemIntf_DQ3
MemIntf_DQ2
MemIntf_DQ1
MemIntf_DQ0
AF25 MemIntf_CE1#
AG25 MemIntf_CE0#
2
SODIMM_VTT
SODIMM_VTT
VTT
MemIntf_ODT1
MemIntf_ODT0
MemIntf_CE1#
MemIntf_CE0#
A3
B3
C3
D3
E3
F3
G3
H3
J3
A3
B3
C3
D3
E3
F3
G3
H3
J3
R1=50 Ohm
DIMM
R1=50 Ohm
X1
R1
R1
R1
U1 Pin
R1
2
Date:
B
A1
B1
C1
D1
E1
F1
G1
H1
J1
MemIntf_WE#
MemIntf_RAS#
MemIntf_CAS#
MemIntf_BA1
MemIntf_BA0
MemIntf_CS1#
MemIntf_CS0#
Termination
at end of line
RP2
A1
B1
C1
D1
E1
F1
G1
H1
J1
MemIntf_A9
MemIntf_A10
MemIntf_A11
MemIntf_A12
MemIntf_A0
MemIntf_A1
MemIntf_A2
MemIntf_A3
MemIntf_A4
MemIntf_A5
MemIntf_A6
MemIntf_A7
MemIntf_A8
VSENSE_VTT_SODIMM pg.16
1
Sheet
1
15
SC-900fpBGA Communications Platform Evaluation Board
Project
DDR2 Memory Controller/SODIMM
MemIntf_A[0:12]
Size
Title
A1
B1
C1
D1
E1
F1
G1
H1
J1
VSENSE_VTT_SODIMM
RP1
A1
B1
C1
D1
E1
F1
G1
H1
J1
X1
needs to be matched length
for all traces
X2
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
CTS-RT1402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
VSENSE_VTT_SODIMM
ALL Memory controller
buses, clocks, and control
traces must be 50 Ohm
Transmission lines
100NF/SMT0603
4
100NF/SMT0603
C459
MemIntf_WE#
C462
109
85
50
163
120
69
83
116
84
86
195
197
200
198
115
110
108
119
114
186
188
167
169
146
148
129
131
68
70
49
51
29
31
11
13
185
170
147
130
67
52
26
10
80
79
166
164
32
30
113
106
107
89
90
105
91
93
92
94
97
98
99
100
101
102
MC_VREF_BANK5
C
WE#
NC/BA2
NC
NC
NC
NC
NC
NC
NC
NC
SDA
SCL
SA1
SA0
S1#
S0#
RAS#
ODT1
ODT0
DQS7#
DQS7
DQS6#
DQS6
DQS5#
DQS5
DQS4#
DQS4
DQS3#
DQS3
DQS2#
DQS2
DQS1#
DQS1
DQS0#
DQS0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
CKE1
CKE0
CK1#
CK1
CK0#
CK0
CAS#
BA1
BA0
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MC_VREF_BANK4
10NF/SMT0603
C460
200-Pin SODIMM
1K/SMT0603
1K/SMT0603
CN1C
10NF/SMT0603
C454
10NF/SMT0603
D
10NF/SMT0603
100NF/SMT0603
E2
All ADDRESS & DATA
lines should be
equal lengths and
length matched with
the K & K#/K COPY and K# COPY
The K, K# andf K COPY and K# COPY
Need to be routed as 100 ohm coupled clock pairs
C464
5
1K/SMT0603
1K/SMT0603
MemIntf_A[0:12]
100NF/SMT0603
C582
100NF/SMT0603
MemIntf_DQ[0:63]
C463
100NF/SMT0603
J2
J2
J2
C452
C457
H2
H2
J2
10NF/SMT0603
10NF/SMT0603
C458
D2
F2
C453
100NF/SMT0603
G2
G2
G2
H2
H2
C455
100NF/SMT0603
F2
F2
G2
B2
C2
C2
E2
D2
E2
F2
B2
B2
D2
E2
A2
A2
C2
A2
B2
42
A2
MemIntf_DM[0..7]
D2
MemIntf_DQS[0..7]
C2
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 18. DDR2 Memory Controller/SODIMM
MemIntf_DQ[0:63]
43
A
B
C
D
CN1B
5
1_8
1_8
+
1_8
4
SODIMM VDD
C486
1UF/SMT1206
VDDSPD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
118
117
112
104
103
111
96
95
88
87
82
81
1_8
Place caps close to SODIMM Connector
199
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
132
128
127
122
121
200-Pin SODIMM
C467
10NF/SMT0603
C468
100NF/SMT0603
C469
10NF/SMT0603
C471
C472
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
3
3
1_8
1
3
2
J148
2
HEADER 3x1
1
3
SODIMM_VREF
2_5
2_5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VREF
4
R188
VDDQ
VREF
SD
U23
LP2996-SO8
5
2
4
SODIMM_VREF
C476
1UF/SMT1206
VTT
VSENSE
6
7
AVIN
PVIN
OBSERVE FUTURE PLUS KEEPOUT REGION
C474
10NF/SMT0603
C470
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
78
77
72
71
66
65
60
59
54
53
48
47
42
41
40
39
34
33
28
27
24
21
18
15
12
9
8
3
2
1
100NF/SMT0603
GND
5
C473
10NF/SMT0603
C479
100NF/SMT0603
C485
10UF/SM_TANT_B
C480
100NF/SMT0603
C481
10NF/SMT0603
C482
100NF/SMT0603
4_7K/SMT0603
C475
1
C465
10NF/SMT0603
C477
C466
8
3
1_8
100NF/SMT0603
C478
100NF/SMT0603
2
C487
+
2
47UF/SM_TANT_B
C483
+
D a te :
S iz e
B
Title
100NF/SMT0603
VSENSE_VTT_SODIMM
S he e t
1
16
of
VSENSE_VTT_SODIMM pg.15
1
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
SODIMM Power/VTT
C489 +
R189
0R/SMT0603
SODIMM_VTT
C488
100UF/ALCAP
1UF/SMT1206
10UF/SM_TANT_B
19
Rev
3.0
A
B
C
D
Figure 19. SODIMM Power/VTT
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
A
B
C
D
R200
5
1K/SMT0603
10NF/SMT0603
C493
pg.8 VREF_LEFT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
TO SC
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
1
3
5
2
4
6
J149
HEADER 3x2
1
3
5
TDAT_N9
TDAT_N11
TDAT_N13
TDAT_N15
TDAT_N1
TDAT_N3
TDAT_N5
TDAT_N7
TDCLK_N
TDAT_P9
TDAT_P11
TDAT_P13
TDAT_P15
TDAT_P1
TDAT_P3
TDAT_P5
TDAT_P7
TDCLK_P
TCTL_N
TSTAT1_P
TCTL_P
TSCLK_P
TSTAT0_P
TDAT_N8
TDAT_N10
TDAT_N12
TDAT_N14
TDAT_N0
TDAT_N2
TDAT_N4
TDAT_N6
TDAT_P8
TDAT_P10
TDAT_P12
TDAT_P14
TDAT_P0
TDAT_P2
TDAT_P4
TDAT_P6
2
4
6
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RCTL_P
R202
1K/SMT0603
10NF/SMT0603
C494
RDCLK_N
RDAT_N7
RDAT_N5
RDAT_N3
RDAT_N1
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VHDM2
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
MOLEX-VHDM-74057-002
FROM SC
TDAT_P0
TDAT_P1
TDAT_P2
TDAT_P3
TDAT_P4
TDAT_P5
TDAT_P6
TDAT_P7
TDAT_P8
TDAT_P9
TDAT_P10
TDAT_P11
TDAT_P12
TDAT_P13
TDAT_P14
TDAT_P15
TDCLK_P
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
4
ADJUST
VCCAUX/2
REG
1
2
SELECTING VREF VOLTAGES
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
RDAT_N15
RDAT_N13
RDAT_N11
RDAT_N9
RDCLK_P
RDAT_P7
RDAT_P5
RDAT_P3
RDAT_P1
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
RDAT_P15
RDAT_P13
RDAT_P11
RDAT_P9
RSTAT1_P
RCTL_N
RSTAT0_P
RSCLK_P
RDAT_N6
RDAT_N4
RDAT_N2
RDAT_N0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
RDAT_N14
RDAT_N12
RDAT_N10
RDAT_N8
RDAT_P6
RDAT_P4
RDAT_P2
RDAT_P0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
RDAT_P14
RDAT_P12
RDAT_P10
RDAT_P8
NC8
NC7
GND
GND
NC6
GND
NC5
GND
NC4
GND
D16P/CLKP
GND
NC3
GND
NC2
GND
D15P
GND
D14P
GND
D13P
GND
D12P
GND
D11P
GND
D10P
GND
D9P
GND
D8P
GND
D7P
GND
D6P
GND
D5P
GND
D4P
GND
D3P
GND
D2P
GND
D1P
GND
D0P
GND
NC1
GRD
VREF_LEFT pg.8
ASP65067-01
NC16
NC15
GND
GND
NC14
GND
NC13
GND
NC12
GND
D16N/CLKN
GND
NC11
GND
NC10
GND
D15N
GND
D14N
GND
D13N
GND
D12N
GND
D11N
GND
D10N
GND
D9N
GND
D8N
GND
D7N
GND
D6N
GND
D5N
GND
D4N
GND
D3N
GND
D2N
GND
D1N
GND
D0N
GND
NC9
GND
1K_ADJ/SMT3MM
R201
R198
1K/SMT0603
VCCAUX
VREF_LEFT
SPI4_VREF_BANK7
99
97
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
Used to adjust the Common Mode Level(1.2V Nom.)
for LVDS output buffers
R197
1K/SMT0603
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCCAUX
VREF_LEFT
SPI4_VREF_BANK6
1K_ADJ/SMT3MM
R196
VHDM1
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
MOLEX-VHDM-74057-002
TDAT_N0
TDAT_N1
TDAT_N2
TDAT_N3
TDAT_N4
TDAT_N5
TDAT_N6
TDAT_N7
TDAT_N8
TDAT_N9
TDAT_N10
TDAT_N11
TDAT_N12
TDAT_N13
TDAT_N14
TDAT_N15
TDCLK_N
To
SC
PL-4 Tx Bus
Locate close to U1
AC4
AD4
VHDM1
AF2
AG2
AF1
AG1
TSCLK_P
TSCLK_N
TSTAT0_P
TSTAT0_N
P8
R8
TDCLK_P
TDCLK_N
TSTAT1_P
TSTAT1_N
J6
J5
K4
J4
K5
K6
E1
D1
L5
M5
R7
R6
T3
R3
R5
R4
U3
V3
T5
T4
V1
W1
V5
V4
Y1
AA1
Y3
W3
Y5
Y6
AD2
AE2
AC3
AD3
TDAT_P0
TDAT_N0
TDAT_P1
TDAT_N1
TDAT_P2
TDAT_N2
TDAT_P3
TDAT_N3
TDAT_P4
TDAT_N4
TDAT_P5
TDAT_N5
TDAT_P6
TDAT_N6
TDAT_P7
TDAT_N7
TDAT_P8
TDAT_N8
TDAT_P9
TDAT_N9
TDAT_P10
TDAT_N10
TDAT_P11
TDAT_N11
TDAT_P12
TDAT_N12
TDAT_P13
TDAT_N13
TDAT_P14
TDAT_N14
TDAT_P15
TDAT_N15
TCTL_P
TCTL_N
RDAT_N0
RDAT_N1
RDAT_N2
RDAT_N3
RDAT_N4
RDAT_N5
RDAT_N6
RDAT_N7
RDAT_N8
RDAT_N9
RDAT_N10
RDAT_N11
RDAT_N12
RDAT_N13
RDAT_N14
RDAT_N15
RDCLK_N
From
SC
PL-4 Rx Bus
U1N
ASP65067-01
NC16
NC15
GND
GND
NC14
GND
NC13
GND
NC12
GND
D16N/CLKN
GND
NC11
GND
NC10
GND
D15N
GND
D14N
GND
D13N
GND
D12N
GND
D11N
GND
D10N
GND
D9N
GND
D8N
GND
D7N
GND
D6N
GND
D5N
GND
D4N
GND
D3N
GND
D2N
GND
D1N
GND
D0N
GND
NC9
GND
NC8
NC7
GND
GND
NC6
GND
NC5
GND
NC4
GND
D16P/CLKP
GND
NC3
GND
NC2
GND
D15P
GND
D14P
GND
D13P
GND
D12P
GND
D11P
GND
D10P
GND
D9P
GND
D8P
GND
D7P
GND
D6P
GND
D5P
GND
D4P
GND
D3P
GND
D2P
GND
D1P
GND
D0P
GND
NC1
GRD
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
VHDM2
C579
100NF/SMT0603
SC-900FPBGA-BOARD1
3
C580
100NF/SMT0603
SPI4_VREF_BANK7
C490
100NF/SMT0603
SPI4_VREF_BANK6
PL57A/LLC_DLLT_IN_F/LLC_DLLT_FB_E/SPI_RSCLKP
PL57B/LLC_DLLC_IN_F/LLC_DLLC_FB_E/SPI_RSCLKN
PL55A/SPI_RSTATP1
PL55B/SPI_RSTATN1
PL53A/SPI_RSTATP0
PL53B/SPI_RSTATN0
PL27C/PCLKT7_2/DEBUG_BUS14/SPI_IN_RDCLKP
PL27D/PCLKC7_2/DEBUG_BUS15/SPI_IN_RDCLKN
RSTAT0_N
RSTAT1_N
TSTAT0_N
TSTAT1_N
RCTL_N
TCTL_N
RSCLK_N
TSCLK_N
VHDM3
C492
100NF/SMT0603
RSTAT0_P
RSTAT0_N
RSTAT1_P
RSTAT1_N
RSCLK_P
RSCLK_N
SPI4_REFCLK
AB6
AC5
AE3
AF3
AC6
AC7
P4
RDCLK_P
RDCLK_N
L1
M1
99
97
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
ASP65067-01
NC16
NC15
GND
GND
NC14
GND
NC13
GND
NC12
GND
D16N/CLKN
GND
NC11
GND
NC10
GND
D15N
GND
D14N
GND
D13N
GND
D12N
GND
D11N
GND
D10N
GND
D9N
GND
D8N
GND
D7N
GND
D6N
GND
D5N
GND
D4N
GND
D3N
GND
D2N
GND
D1N
GND
D0N
GND
NC9
GND
2
Date:
Size
Title
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
pg.11
NC8
NC7
GND
GND
NC6
GND
NC5
GND
NC4
GND
D16P/CLKP
GND
NC3
GND
NC2
GND
D15P
GND
D14P
GND
D13P
GND
D12P
GND
D11P
GND
D10P
GND
D9P
GND
D8P
GND
D7P
GND
D6P
GND
D5P
GND
D4P
GND
D3P
GND
D2P
GND
D1P
GND
D0P
GND
NC1
GRD
SPI4_REFCLK
2
ASP3
All SPI4/PL4
signals must be routed
50 Ohm Transmission
lines
PL30C/PCLKT6_3/SPI_REFCLKIN
PL57C/LLC_PLLT_IN_B/LLC_PLLT_FB_A/SPI_TSCLKP
PL57D/LLC_PLLC_IN_B/LLC_PLLC_FB_A/SPI_TSCLKN
PL56A/SPI_TSTATP1
PL56B/SPI_TSTATN1
PL55C/LLC_DLLT_IN_E/LLC_DLLT_FB_F/SPI_TSTATP0
PL55D/LLC_DLLC_IN_E/LLC_DLLC_FB_F/SPI_TSTATN0
PL27A/PCLKT7_0/DEBUG_BUS1/SPI_OUT_TDCLKP
PL27B/PCLKC7_0/DEBUG_BUS0/SPI_OUT_TDCLKN
RDAT_P0
RDAT_N0
RDAT_P1
RDAT_N1
RDAT_P2
RDAT_N2
RDAT_P3
RDAT_N3
RDAT_P4
RDAT_N4
RDAT_P5
RDAT_N5
RDAT_P6
RDAT_N6
RDAT_P7
RDAT_N7
RDAT_P8
RDAT_N8
RDAT_P9
RDAT_N9
RDAT_P10
RDAT_N10
RDAT_P11
RDAT_N11
RDAT_P12
RDAT_N12
RDAT_P13
RDAT_N13
RDAT_P14
RDAT_N14
RDAT_P15
RDAT_N15
RCTL_P
RCTL_N
D3
D2
E3
E2
F3
G3
G2
G1
K3
L3
F2
F1
J1
K1
N2
N1
N3
P3
P2
R2
P1
R1
T2
U2
T1
U1
U4
U5
V2
W2
Y2
AA2
AB1
AC1
Control/
Status
PL16A/ULC_PLLT_IN_A/ULC_PLLT_FB_B/DEBUG_BUS11/SPI_OUT_DATP0
PL16B/ULC_PLLC_IN_A/ULC_PLLC_FB_B/DEBUG_BUS10/SPI_OUT_DATN0
PL17A/ULC_DLLT_IN_C/ULC_DLLT_FB_D/DEBUG_BUS9/SPI_OUT_DATP1
PL17B/ULC_DLLC_IN_C/ULC_DLLC_FB_D/DEBUG_BUS8/SPI_OUT_DATN1
PL18A/ULC_DLLT_IN_D/ULC_DLLT_FB_C/SPI_OUT_DATP2
PL18B/ULC_DLLC_IN_D/ULC_DLLC_FB_C/SPI_OUT_DATN2
PL20A/SPI_OUT_DATP3
PL20B/SPI_OUT_DATN3
PL25A/TESTCFGN/SPI_OUT_DATP4
PL25B/DEBUG_BUS7/SPI_OUT_DATN4
PL22A/SPI_OUT_DATP5
PL22B/SPI_OUT_DATN5
PL26A/PCLKT7_1/DEBUG_BUS3/SPI_OUT_DATP6
PL26B/PCLKC7_1/DEBUG_BUS2/SPI_OUT_DATN6
PL29A/PCLKT6_0/SPI_OUT_DATP7
PL29B/PCLKC6_0/SPI_OUT_DATN7
PL30A/SPI_OUT_DATP8
PL30B/SPI_OUT_DATN8
PL31A/SPI_OUT_DATP9
PL31B/SPI_OUT_DATN9
PL34A/SPI_OUT_DATP10
PL34B/SPI_OUT_DATN10
PL35A/SPI_OUT_DATP11
PL35B/SPI_OUT_DATN11
PL38A/SPI_OUT_DATP12
PL38B/SPI_OUT_DATN12
PL40A/SPI_OUT_DATP13
PL40B/SPI_OUT_DATN13
PL43A/SPI_OUT_DATP14
PL43B/SPI_OUT_DATN14
PL47A/SPI_OUT_DATP15
PL47B/SPI_OUT_DATN15
PL48A/SPI_OUT_TCTLP
PL48B/SPI_OUT_TCTLN
RDAT_P0
RDAT_P1
RDAT_P2
RDAT_P3
RDAT_P4
RDAT_P5
RDAT_P6
RDAT_P7
RDAT_P8
RDAT_P9
RDAT_P10
RDAT_P11
RDAT_P12
RDAT_P13
RDAT_P14
RDAT_P15
RDCLK_P
SC-900FPBGA
SPI4
PL16C/DEBUG_BUS13/SPI_IN_DATP0
PL16D/SPI_IN_DATN0
PL17C/ULC_PLLT_IN_B/ULC_PLLT_FB_A/SPI_IN_DATP1
PL17D/ULC_PLLC_IN_B/ULC_PLLC_FB_A/SPI_IN_DATN1
PL18C/DEBUG_BUS12/SPI_IN_DATP2
PL18D/VREF2_7/DEBUG_BUS6/SPI_IN_DATN2
PL22C/SPI_IN_DATP3
PL22D/SPI_IN_DATN3
PL21A/SPI_IN_DATP4
PL21B/SPI_IN_DATN4
PL29C/PCLKT6_1/SPI_IN_DATP5
PL29D/PCLKC6_1/SPI_IN_DATN5
PL31C/PCLKT6_2/SPI_IN_DATP6
PL31D/PCLKC6_2/SPI_IN_DATN6
PL34C/VREF1_6/SPI_IN_DATP7
PL34D/SPI_IN_DATN7
PL36A/SPI_IN_DATP8
PL36B/SPI_IN_DATN8
PL39A/SPI_IN_DATP9
PL39B/SPI_IN_DATN9
PL42A/SPI_IN_DATP10
PL42B/SPI_IN_DATN10
PL43C/SPI_IN_DATP11
PL43D/SPI_IN_DATN11
PL44A/SPI_IN_DATP12
PL44B/SPI_IN_DATN12
PL47C/SPI_IN_DATP13
PL47D/SPI_IN_DATN13
PL49A/SPI_IN_DATP14
PL49B/SPI_IN_DATN14
PL51A/SPI_IN_DATP15
PL51B/SPI_IN_DATN15
PL52A/SPI_IN_RCTLP
PL52B/SPI_IN_RCTLN
99
97
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
3
PL35C/VREF2
ASP2
0R/SMT0603
4
PL42C/VREF_REFCLK
0R/SMT0603
ASP1
PL25C/VREF1_7/DEBUG_BUS5
L6
R191
U6
0R/SMT0603
5
PL25D/DIFFR_7/DEBUG_BUS4
M6
1K_1%/SMT0603
V6
R193
T6
R190
PL42D/DIFFR_6
R194 1K_1%/SMT0603
44
R192
B
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Sheet
1
17
SC-900fpBGA Communications Platform Evaluation Board
Project
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
MOLEX-VHDM-74057-002
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
VHDM3
SPI4 Interface
RSTAT0_P
RSTAT1_P
TSTAT0_P
TSTAT1_P
RCTL_P
TCTL_P
RSCLK_P
TSCLK_P
1
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 20. SPI4 Interface
A
B
100R/SMT0603
J181
Rosenberger 32K153-400E3
LVDS_OUTN
1
R205
LVDS_OUTP
5
14 RN11C
13 RN11D
3
4
13 RN12D
8
7
6
9 RN13H
10 RN13G
11 RN13F
12 RN13E
13 RN13D
4
5
14 RN13C
3
8
15 RN13B
9 RN12H
16 RN13A
10 RN12G
7
2
11 RN12F
6
1
12
5
LVDS OUT
PR57[A:B]
J152B
HEADER 24x3
EXB2HV471JV
470R
14 RN12C
4
RN12E
15 RN12B
3
9 RN11H
8
2
10 RN11G
16 RN12A EXB2HV471JV
470R
11 RN11F
6
7
1
12
5
EXB2HV471JV
470R
PCLK2[T:C]
100-ohm
Differential Coupled
PCB Traces
1
J182
Rosenberger 32K153-400E3
15 RN11B
RN11E
16 RN11A
1
2
PR27[C:D]
1
SW19A
3
SW19B
12
4
SW19C
10
6
SW19D
9
6
SW18D
4
SW18C
3
SW18B
J154
Rosenberger 32K153-400E3
J153
LVDS_INP
1
Rosenberger 32K153-400E3
LVDS_INN
1
7
7
9
1
SW17A
1
SW16A
1
SW15A
1
SW14A
1
SW18A
3
SW17B
12
4
SW17C
10
6
SW17D
9
3
SW16B
12
4
SW16C
10
3
SW15B
12
4
SW15C
10
6
SW16D
9
3
SW14B
12
4
SW14C
10
6
SW15D
2
2
C
7
7
7
9
6
SW14D
9
8
12
11
1
0
2
D
7
1
0
5
1
0
8
8
5
1
0
5
1
0
5
1
0
8
8
8
5
1
0
5
1
0
2
1
0
2
1
0
1
0
1
0
11
1
0
11
1
0
1
0
2
1
0
1
0
1
0
2
1
0
11
1
0
11
11
2
1
0
2
1
0
2
1
0
1
0
DIP SWITCHES
AK15
AJ28
AH28
AE25
AE26
AD25
H26
G26
L25
L26
J28
H28
P27
L29
M30
U26
T24
AB27
H14
AB5
W5
AK28
AF24
AG24
R214
51R/SMT0603
U1M
R216
51R/SMT0603
J164
Rosenberger 32K153-400E3
LRC_DLLT
1
LRC_DLLC
PB68[A:B]
DLL INPUTS
4
R217
51R/SMT0603
1
NC
OUT
GND
VCC
Y4
50MHz Oscillator
VCC1-B0B-50M000
1
3
URC_PLLC pg.11
URC_PLLT pg.11
ORANGE4
ORANGE3
ORANGE2
ORANGE1
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
YELLOW5
YELLOW4
YELLOW3
YELLOW2
YELLOW1
RED5
RED4
RED3
22R/SMT0603
R204
LEDS
RED2
RED1
J162
Rosenberger 32K153-400E3
URC_PLLC
URC_PLLT
LRC_PLLC
LRC_PLLT
LRC_DLLC
LRC_DLLT
K26
K25
AH30
AJ30
AH29
AJ29
B16
50_OHM_1
50_OHM_2
50_OHM_3
50_OHM_4
LVDS_OUTP
LVDS_OUTN
LVDS_INP
LVDS_INN
AH27
AH26
AE22
AK29
AF29
AF28
P26
N27
50-ohm Single-ended Traces
R215
51R/SMT0603
1
J161
Rosenberger 32K153-400E3
SC-900FPBGA-BOARD1
SC-900FPBGA
PT37B/PCLKC1_0
PR17D/URC_PLLC_IN_B/URC_PLLC_FB_A
PR17C/URC_PLLT_IN_B/URC_PLLT_FB_A
PB69B/LRC_PLLC_IN_A/LRC_PLLC_FB_B
PB69A/LRC_PLLT_IN_A/LRC_PLLT_FB_B
PB68B/LRC_DLLC_IN_C/LRC_DLLC_FB_D
PB68A/LRC_DLLT_IN_C/LRC_DLLT_FB_D
PB61B
PB61A
PB60C
PB60B
PR57A/LRC_DLLT_IN_F/LRC_DLLT_FB_E
PR57B/LRC_DLLC_IN_F/LRC_DLLC_FB_E
PR27C/PCLKT2_2
PR27D/PCLKC2_2
J152C
HEADER 24x3
General Purpose
IO Pins
PB35B
PB67A
PB67B
PB67D
PB68C
PB68D
PR16C
PR16D
PR18C
PR18D/VREF2_2
PR22C
PR22D
PR30C/PCLKT3_3
PR31C/PCLKT3_2
PR31D/PCLKC3_2
PR34D
PR35C
PR51D/VREF2_3
PT31C/VREF1_1
PL51D/VREF2_6/MC_CS4#
PL48C/MC_CS5#
PB60A/MC_DM8
PB63A/MC_DQ68
PB63B/MC_DQ69
J163
Rosenberger 32K153-400E3
LRC_PLLT
1
LRC_PLLC
PB69[A:B]
PLL INPUTS
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
J152A
HEADER 24x3
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
SWITCH8
SWITCH9
SWITCH10
SWITCH11
SWITCH12
SWITCH13
SWITCH14
SWITCH15
SWITCH16
SWITCH17
SWITCH18
SWITCH19
SWITCH20
SWITCH21
SWITCH22
SWITCH23
SWITCH24
2
10
2
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
2
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
2
4
2
4
L18
3_3
1UH/SMT1206
C495
100NF/SMT0603
R203
1_6R/SMT0603
3
ORANGE1
BLUE1
GREEN1
YELLOW1
RED1
3
RN15A
RN17C
RN17H
91
14
1
5
12
1
EXB2HV103JV
10K
RN19E
EXB2HV103JV
10K
8
EXB2HV103JV
10K
3
6
11
1
EXB2HV103JV
10K
RN15F
1
1
16
EXB2HV103JV
10K
LED-SMT1206_RED
D35
RN14A
EXB2HV221JV
220R
RN14F
EXB2HV221JV
220R
LED-SMT1206_YELLOW
D40
LED-SMT1206_GREEN
D45
RN16C
EXB2HV221JV
220R
RN16H
EXB2HV221JV
220R
TP79
TP81
R222
51R/SMT0603
1
1
PB61[A:B]
R218
OPEN/SMT0603
50_OHM_2
R223
51R/SMT0603
R219
OPEN/SMT0603
50_OHM_1
ORANGE2
BLUE2
GREEN2
YELLOW2
RED2
RN17D
RN19A
16
1
13
1
11
1
6
EXB2HV103JV
10K
RN19F
EXB2HV103JV
10K
1
EXB2HV103JV
10K
4
7
10
1
EXB2HV103JV
10K
RN15G
2
15
1
EXB2HV103JV
10K
RN15B
J165
Rosenberger 32K153-400E3
J166
Rosenberger 32K153-400E3
2
LED-SMT1206_RED
D36
RN14B
EXB2HV221JV
220R
RN14G
EXB2HV221JV
220R
LED-SMT1206_YELLOW
D41
LED-SMT1206_GREEN
D46
RN16D
EXB2HV221JV
220R
RN18A
EXB2HV221JV
220R
TP80
TP82
1
RN15C
RN19B
15
1
10
1
7
EXB2HV103JV
10K
RN19G
EXB2HV103JV
10K
2
5
12
1
EXB2HV103JV
10K
RN17E
8
91
EXB2HV103JV
10K
RN15H
14
3
1
EXB2HV103JV
10K
2
J167
Rosenberger 32K153-400E3
J168
Rosenberger 32K153-400E3
ORANGE3
BLUE3
GREEN3
YELLOW3
RED3
PB60C:D]
R220
OPEN/SMT0603
50_OHM_4
R225
51R/SMT0603
R221
OPEN/SMT0603
50_OHM_3
R224
51R/SMT0603
1
LED-SMT1206_ORANGE
D56
RN18F
EXB2HV221JV
220R
Q59
2N2222/SOT23
5_0_IN
Q54
2N2222/SOT23
LED-SMT1206_BLUE
D51
5_0_IN
Q49
2N2222/SOT23
5_0_IN
Q44
2N2222/SOT23
5_0_IN
Q39
2N2222/SOT23
5_0_IN
LED-SMT1206_GREEN
D47
RN16E
EXB2HV221JV
220R
RN18B
EXB2HV221JV
220R
LED-SMT1206_ORANGE
D57
RN18G
EXB2HV221JV
220R
Date:
B
ORANGE4
BLUE4
GREEN4
YELLOW4
RED4
RN15D
RN17F
RN19C
14
1
11
1
8
91
EXB2HV103JV
10K
RN19H
EXB2HV103JV
10K
3
EXB2HV103JV
10K
6
1
16
1
EXB2HV103JV
10K
RN17A
4
13
1
EXB2HV103JV
10K
LED-SMT1206_RED
D38
RN14D
EXB2HV221JV
220R
RN16A
EXB2HV221JV
220R
LED-SMT1206_GREEN
D48
RN16F
EXB2HV221JV
220R
RN18C
EXB2HV221JV
220R
RN18H
EXB2HV221JV
220R
BLUE5
GREEN5
YELLOW5
LED-SMT1206_ORANGE
D58
Q61
2N2222/SOT23
5_0_IN
Q56
2N2222/SOT23
LED-SMT1206_BLUE
D53
5_0_IN
Q51
2N2222/SOT23
5_0_IN
RED5
LED-SMT1206_YELLOW
D43
Q46
2N2222/SOT23
5_0_IN
Q41
2N2222/SOT23
5_0_IN
RN17G
RN19D
M4
P5
J3
AB3
AH9
AG7
AK27
AJ24
AA28
P24
K28
P23
L28
E19
G21
G20
G19
F9
A11
G7
AC16
AB30
AF12
AG10
13
1
10
1
Sheet
RN14E
EXB2HV221JV
220R
LED-SMT1206_RED
D39
RN16B
EXB2HV221JV
220R
LED-SMT1206_YELLOW
D44
LED-SMT1206_GREEN
D49
RN16G
EXB2HV221JV
220R
RN18D
EXB2HV221JV
220R
Q57
2N2222/SOT23
1
18
of
19
LED-SMT1206_BLUE
D54
5_0_IN
Q52
2N2222/SOT23
5_0_IN
Q47
2N2222/SOT23
5_0_IN
Q42
2N2222/SOT23
5_0_IN
SC-900FPBGA-BOARD1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
U1G
EXB2HV103JV
10K
4
EXB2HV103JV
10K
7
2
15
1
EXB2HV103JV
10K
RN17B
5
12
1
EXB2HV103JV
10K
RN15E
1
SC-900fpBGA Communications Platform Evaluation Board
Project
FPGA Test
Q60
2N2222/SOT23
5_0_IN
Q55
2N2222/SOT23
LED-SMT1206_BLUE
D52
5_0_IN
Q50
2N2222/SOT23
5_0_IN
Size
RN14H
EXB2HV221JV
220R
LED-SMT1206_YELLOW
D42
Q45
2N2222/SOT23
5_0_IN
Title
LED-SMT1206_RED
D37
RN14C
EXB2HV221JV
220R
Q40
2N2222/SOT23
5_0_IN
LEDS CAN BE DRIVEN BY ANY SINGLE
ENDED IO TYPE.
50-ohm Single-ended
Terminated PCB Traces
LED-SMT1206_ORANGE
D55
RN18E
EXB2HV221JV
220R
Q58
2N2222/SOT23
5_0_IN
Q53
2N2222/SOT23
LED-SMT1206_BLUE
D50
5_0_IN
Q48
2N2222/SOT23
5_0_IN
Q43
2N2222/SOT23
5_0_IN
Q38
2N2222/SOT23
5_0_IN
1
16
R
3
2
6
11
Y
3
2
3
14
G
3
2
8
9
B
3
2
5
12
O
3
5
2
2
2
1
1
2
15
R
3
2
7
10
Y
3
2
4
13
G
3
2
1
16
B
3
2
6
11
O
3
2
1
1
2_5
2
2
3
14
R
3
2
8
9
Y
3
2
5
12
G
3
2
2
15
B
3
2
7
10
O
3
2
4
13
R
3
2
1
16
Y
3
2
6
11
G
3
2
3
14
B
3
2
8
9
O
3
2
5
12
R
3
2
2
15
Y
3
2
7
10
G
3
2
4
13
B
3
2
45
SC-900FPBGA
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 21. FPGA Test
46
A
B
C
D
VCCIO1
C510
C522
VCCIO2
C534
VCCIO3
VCCIO4
C520
C532
C549
VCCIO6
VCCIO7
C540
5
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C539
VCCIO25
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C548
VCCIO25
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C531
VCCIO5
VCCIO18
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C519
VCCIO18
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C533
VCCIO25
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C521
VCCIO25
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C509
VCCIO1
VCCIO
VCC12
C538
C547
C513
C526
C551
C552
C541
VDDIB
VCC
C553
C542
VDDOB
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C525
VDDP
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C512
VDDRX
C559
C560
C561
100NF/SMT0603
1000PF-0402SMT-Johanson 100R05W102FV4
10NF/SMT0603
100NF/SMT0603
C558
VCC
C544
VDDTX
VCC Core
C543
VDDRX
100NF/SMT0603
1000PF-0402SMT-Johanson 100R05W102FV4
10NF/SMT0603
100NF/SMT0603
C550
C503
C515
C529
C555
VDDP
C556
VCC
C557
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C528
VDDAX25
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C514
VDDTX
C563
C564
C565
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
100NF/SMT0603
10NF/SMT0603
C562
VCC
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
10NF/SMT0603
100NF/SMT0603
C554
C545
C505
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C504
VDDOB
4
3
All 65 capacitors on this page shall be placed directly
under the U1 BGA
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C546
VCC12
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C537
VCC1P2
and VCCPLL
C502
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
SERDES Power
22PF/0402Johanson 250-R07S220FV4
VDDIB
22PF/0402Johanson 250-R07S220FV4
3
22PF/0402Johanson 250-R07S220FV4
4
22PF/0402Johanson 250-R07S220FV4
5
22PF/0402Johanson 250-R07S220FV4
2
2
C506
VCCAUX
C517
C530
C536
D a te :
S iz e
C
Title
C508
C518
C524
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C523
VCCAUX
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C511
VCCAUX
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C507
VCCAUX
Wednesday, November 23, 2005
1
S he e t
19
P roje c t
SC-900fpBGA Communications Platform Evaluation Board
BGA Decoupling
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C535
VCCAUX
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C527
VCCAUX
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C516
VCCAUX
1000PF-0402SMT-Johanson 100R05W102FV4
100NF/SMT0603
C501
VCCAUX
1
of
19
Rev
3.0
A
B
C
D
Lattice Semiconductor
LatticeSC Communications Platform
Evaluation Board: LFSC25E-H-EV User’s Guide
Figure 22. BGA Decoupling