OR4E FPGA Ver 2.0 1 4/1/2002 Lattice Semiconductor Corp Series 4 FPGA Evaluation Board Diagram Revision 2.0 OR4E FPGA Ver 2.0 2 4/1/2002 Lattice Semiconductor Corp JTAG Programming Connection J55 Schematic page 4 An 8-pin connection to the JTAG interface used for programming. JTAG Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Vdd TDI TMS TCK TDO Rd_Cfg_n Init_n GND Serial Programming Connection J57 Schematic page 4 A 7-pin serial connector used for configuration through the serial mode interface Serial Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Vdd cclk D0 Done Prog nc GND General-purpose I/O Header Connections J1, J2, J3, J4, J6, J7, J10 ,J12, J13 Schematic page 5 Standard 0.100 headers are provided for interconnecting points on the board. This can be accomplished with 0.100 IDC connectors and ribbon cable for bus connections or 0.025 pin socket patch cords(such as Pomona Electronics #5948 www.pomonaelectronics.com) Differential I/O Headers J5, J9, J15, J19, J18 Schematic page 5 Additional 0.100 headers are provided in a 3-pin configuration to provide access to differential LVPECL or LVDS I/O. The 3-pin assemblies provide a center position ground. The headers accept connections to a 3-pin cable assembly such as P/N HDN1610-01 manufactured by W.L. Gore (www.wlgore.com). OR4E FPGA Ver 2.0 3 4/1/2002 Lattice Semiconductor Corp Power Supply Modes Schematic page 1 a) Bench Supply ONLY. +5V, 3.3V, 2.5V, 1.5V applied through corresponding banana jacks. J101 in 2-3 position. b) Wall Adapter ONLY. +5V applied through barrel jack. +3.3V, 2.5V, and 1.5V regulated from +5V. J101 in 1-2 position. c) +5V Bench Supply ONLY. +5V applied through +5V banana jack. +3.3V, 2.5V, and 1.85V regulated from +5V. J101 in 1-2 position. d) Wall Adapter and Bench Supply COMBO. +5V applied through barrel connector. +3.3V, 2.5, 1.5V applied through corresponding banana jacks. J101 in 2-3 position. Selecting VDDIO Levels J64, J59, J63, J69, J72, J77, J73, J68 Schematic page 2 8 independent voltages can be applied to the proper device banks through a 2x3 header and a 2position shunt. By placing the shunt across the appropriate pins of the header the VDDIO can be sourced from the board to be 1.5V, 2.5V, 3.3V or driven externally through a banana jack. Settings are as follows: Pin 1 – 3 = 3.3V Pin 3 - 5 = 2.5V Pin 4 – 6 = 1.5V Pin 2 – 4 = External Voltage References and Terminating Voltages J42, J49, J53 Schematic page 2 Connections between banana jacks(J45,J52, J139) VR1, VR2, and VTT are available to an adjacent 2x4 0.100 header. These are used for provided VREF and terminating connections for specific IO settings. Dip Switch Pull-Up Voltage J119 Schematic page 7 a) 1-2 Position: Resistors are pulled-up to +3.3V. b) 2-3 Position: Resistors are pulled-up to local applied banana jack voltage. OR4E FPGA Ver 2.0 4 4/1/2002 Lattice Semiconductor Corp Oscillator Connections to SMA J28 and SMA J38 Output Source Schematic page 4 J24 settings a) 1-2 Position: Output of Y1 connected to SMA J28. b) 2-3 Position: Output of Y2 (15MHz XO) connected to SMA J28. J34 settings a) 1-2 Position: Output of Y3 connected to SMA J38. b) 2-3 Position: Output of Y4 (66MHz XO) connected to SMA J38. SMA Connections Schematic page 4/7 Each input SMA has an on-board termination scheme that is foot printed but not stuffed. These SMA connectors provide differential input to the PLL clocks as well as differential or singleended connections to the primary clock pins. LEDs J46 Schematic page 4 A standard 2x8 0.100 header connects to LEDs. When a jumper cable is used, output from the OR4E device can drive these LEDs to display a pattern. The connections are: J5 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 OR4E FPGA Ver 2.0 red LED red LED red LED red LED yellow LED yellow LED yellow LED yellow LED green LED green LED green LED green LED red LED red LED red LED red LED 5 4/1/2002 Lattice Semiconductor Corp Chip Select Control J23 Schematic page 4 J23 and J27 provide chip select control over the OR4E. If un-shunted the onboard OR4E will be, by default, selected. However, CS can be taken away by shunting either J23, or J27. DATA0 Control JJ36 Schematic page 8 J36 Provides control over OR4E DATA0 input source. On the OR4E evaluation board (r2), there are three devices inherently capable of driving DATA0: The Serial Port, Parallel Port, and the Windriver MPC860 development daughter-board. J36 segments DATA0 into DATA0_A and DATA0_B: a) 1-2 Position: DATA0 is connected to the MPC860 daughter-board. b) 2-3 Position: DATA0 is connected to the Serial and Parallel port. Microprocessor Interface JJ1113, J1114, J1115 Schematic page 8 96-pin headers are provided to mate directly with the 860 bus to communicate to a Windriver(www.windriver.com) MPC860 development board. J16, J17, J21 Schematic page 8 Headers are provided to observe signals of the PowerPC interface. Parallel Port Voltage Stepdown and Buffer Control J54 Schematic page 4 The Parallel Port is designed to be externally driven to 5V levels. The OR4E's inputs are not 5V tolerant. U2 is responsible for shifting 5V levels to approx. 3.3V levels and isolating the parallel interface when not in use. When using the Parallel Port, J54 must be shunted to activate the Buffer IC U2. 5V power to the Parallel Port is assumed to come from the driving device (cable). However, if onboard +5V is to be used L7 must be removed and placed in the L5 position. This option not supported by the device programming software. OR4E FPGA Ver 2.0 6 4/1/2002 Lattice Semiconductor Corp 5 4 3 2 1 J58 J59 1 2 3 VDDIO1 +2.5V SELECTING VDDIO VOLTAGES BANANA Red Banana Jack 111-0102-001 C132 47UF 1 +3.3V 6 5 4 +3.3V BANANA VDDio VDDio +2.5V +1.5V TSW-103-07-T-D 2x3 0.100" HDR C15 C16 C17 C18 C19 VDDIO1 +1.5V 100NF 100NF 100NF 100NF 100NF +1.5V TSW-108-07-T -S 1x8 0.100" Header +1.5V 100NF 100NF 100NF C20 100NF 100NF 100NF 100NF C22 C24 C26 C28 C23 C25 C27 D J61 8 7 6 5 4 3 2 1 +3.3V +1.5V 47UF C21 J60 47UF 8 7 6 5 4 3 2 1 D +1.5V J73 +2.5V C75 +3.3V BANANA VDDio VDDio +2.5V +1.5V 6 5 4 100NF C76 100NF C77 AK6 AL2 Y16 Y17 Y18 Y19 AA16 AA17 VDDIO6 +1.5V BOT LEFT [BL/6] VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 VDDIO6 OR4E VSS BLOCK 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 J76 8 7 6 5 4 3 2 1 47UF 100NF 100NF 100NF 100NF C138 C82 C83 C84 C85 TSW-103-07-T -D 2x3 0.100" HDR AK5 AL3 AM1 AM2 AM4 AN3 AP3 9 10 11 12 13 14 15 16 A 1 T22 T21 T20 T15 T14 T13 C36 C37 C38 C133 100NF 100NF 100NF 47UF +3.3V F30 E29 +1.5V VREF_3_01 VREF_3_02 VREF_3_03 VREF_3_04 VREF_3_05 VREF_3_06 VREF_3_07 VREF_3_08 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C46 100NF 1 C49 100NF U18 U19 V1 T16 R22 R21 U17 T17 T18 T19 U16 Red Banana Jack 111-0102-001 J69 6 VDDIO3 5 4 AD34 AC32 Y32 W34 U34 R32 M32 L34 AD32 AB33 W30 V31 T32 P32 M34 N30 C C47 100NF +1.5V J77 J78 VDDIO5 +2.5V +1.5V VDD33 VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDDIO4 VDDIO4 VDDIO4 VDDIO4 VDDIO4 VDDIO4 VDDIO4 1 2 3 VDDIO3 +2.5V TSW-103-07-T -D 2x3 0.100" HDR L3T_D1 L5C_A0 L7C_D3 L10C_A0 L14T_A0 L16C_A1 L20T_D1 L22T_D2 +3.3V B AN31 AK31 +1.5V J72 C69 V22 V21 V20 V15 V14 V13 AP32 AN32 AM34 AM33 AM31 AL32 AK30 47UF C70 100NF C71 100NF C72 100NF C74 100NF Red Banana Jack 111-0102-001 J74 6 VDDIO4 5 4 +1.5V BANANA +3.3V VDDio VDDio +1.5V +2.5V +3.3V 1 2 3 VDDIO4 +2.5V TSW-103-07-T -D 2x3 0.100" HDR A 1 2 3 Red Banana Jack 111-0102-001 +3.3V BANANA VDDio VDDio +2.5V +1.5V 6 5 VDDIO5 4 +1.5V TSW-103-07-T -D 2x3 0.100" HDR Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 4 BANANA +3.3V VDDio VDDio +1.5V +2.5V TSW-108-07-T-D 2x8 0.100" Header +3.3V 5 +3.3V C54 C55 C56 C57 C58 C59 C135 VDDIO3 VDDIO3 VDDIO3 VDDIO3 VDDIO3 VDDIO3 VDDIO3 VDDIO3 U22 U21 U20 U15 U14 U13 100NF 100NF 100NF 100NF 100NF 100NF 47UF VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 C65 100NF C66 100NF BOTTOM CENTER [BC/5] VDD33 VDD33 1 2 3 4 5 6 7 8 1 VDDIO6 Red Banana Jack 111-0102-001 J75 1 2 3 C73 100NF 1 +3.3V 47UF 1 2 3 4 5 6 7 8 C78 C79 C80 C81 C137 C67 C68 C91 C92 C93 100NF 100NF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MFR: LATTICE PKG: 680PBGA 100NF 100NF 100NF +3.3V AM32 AN1 AN2 AN33 AN34 AP1 AP2 AP18 AP33 AP34 AM22 VREF_7_01 VREF_7_02 VREF_7_03 VREF_7_04 VREF_7_05 VREF_7_06 VREF_7_07 VREF_7_08 C88 C89 C90 C139 B L3 M1 P3 T4 W2 Y5 AB4 AC5 OR4E C86 C87 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1x8 0.100" Header TSW-108-07-T-S VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 VDDIO7 100NF 100NF 100NF 47UF 100NF 100NF 100NF 100NF 100NF 47UF J71 L1 M3 R3 U1 W1 Y3 AC3 AD1 100NF 100NF +1.5V AP26 AK23 VREF_5_06 AL23 VREF_5_05 AN20 VREF_5_04 AL19 VREF_5_03 AM16VREF_5_02 VREF_5_01 AM12 AM15VDDIO5 AM20VDDIO5 AM23VDDIO5 AP11 VDDIO5 AP17 VDDIO5 AP19 VDDIO5 AP24 VDDIO5 VDDIO5 W13 W14 VDD15 W15 VDD15 W20 VDD15 W21 VDD15 W22 VDD15 VDD15 VDDIO7 BLOCK L17C_D3 L14C_A3 L12C_S0 L8C_S0 L6T_S0 L2T_A1 6 5 4 POWER AB3 AA22 VSS AA21 VSS AA20 VSS AA15 VSS AA14 VSS AA13 VSS Y22 VSS Y21 VSS Y20 VSS Y15 VSS VSS +2.5V +3.3V BANANA VDDio VDDio +2.5V +1.5V TSW-103-07-T -D 2x3 0.100" HDR VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 CENTER LEFT [CL/7] 1 2 3 Red Banana Jack 111-0102-001 AA18 AA19 AB16 AB17 AB18 AB19 J65 D26 C27 A30 D29 E32 J30 F33 J31 1x8 0.100" Header TSW-108-07-T-S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TOP CENTER [TC/1] AP15 AP14 VREF_6_11 AK13 VREF_6_10 AP9 VREF_6_09 AK11 VREF_6_08 AN6 VREF_6_07 AL7 VREF_6_06 AH5 VREF_6_05 AH4 VREF_6_04 AG1 VREF_6_03 AF2 VREF_6_02 VREF_6_01 AB32 AL4 VSS AL31 VSS AM3 VSS AM13VSS AB22 VSS AB21 VSS AB20 VSS AB15 VSS AB14 VSS AB13 VSS VSS J70 C51 C60 C61 C62 C63 C64 C136 VDDIO7 1 +3.3V C50 100NF +2.5V TSW-103-07-T -D 2x3 0.100" HDR J67 J68 47UF VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 R20 R15 R14 R13 P22 P21 P20 P15 P14 P13 N32 D23 D22 C21 D18 E18 A13 VREF_1_01 VREF_1_02 VREF_1_03 VREF_1_04 VREF_1_05 VREF_1_06 C23 C20 C15 C12 A24 A19 A17 A11 R19 R18 R17 R16 P19 P18 N22 N21 N20 N15 N14 N13 N3 D31 D4 C32 C22 F5 D5 +1.5V TOP RT [TR/2] VDD33 VDD33 VDDIO2 100NF 100NF 100NF 100NF 47UF 2x8 0.100" Header TSW-108-07-T -D C VREF_0_01 VREF_0_02 VREF_0_03 VREF_0_04 VREF_0_05 VREF_0_06 VREF_0_07 VREF_0_08 VREF_0_09 VREF_0_10 +3.3V 1 2 3 C43 C44 D13 D12 C9 C8 B7 E9 G4 F2 K5 J1 E30 D32 C34 C33 C31 B32 A32 100NF 100NF 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 VREF_2_08 VREF_2_07 VREF_2_06 VREF_2_05 VREF_2_04 VREF_2_03 VREF_2_02 VREF_2_01 AE31 AH33 VREF_4_08 AK34 VREF_4_07 AL34 VREF_4_06 AM30VREF_4_05 AM29VREF_4_04 AN28 VREF_4_03 AK25 VREF_4_02 VREF_4_01 47UF 100NF 100NF 100NF 100NF 9 10 11 12 13 14 15 16 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 L20C_S1 L18C_D0 L16T_D0 L13T_S2 L9C_D1 L6C_S1 L4C_A0 L2T_D0 J66 9 10 11 12 13 14 15 16 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 VDDIO0 BOT RT [BR/4] A3 B3 C1 C2 C4 D3 E5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO0 +1.5V VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 C34 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 C33 100NF VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C32 100NF N16 N17 N18 N19 P16 P17 CENTER RIGHT [CR/3] 6 5 4 C134 C39 C40 C41 C42 +3.3V BANANA VDDio VDDio +2.5V +1.5V TSW-103-07-T -D 2x3 0.100" HDR 100NF U1A Y14 Y13 W19 W18 W17 W16 V34 V19 V18 V17 V16 1 2 3 +2.5V Red Banana Jack 111-0102-001 1 J64 +3.3V C31 VDD33 VDD33 47UF C13 C3 B34 B33 B2 B1 A34 A33 A18 A2 A1 +1.5V J62 VDDIO0 Red Banana Jack 111-0102-001 J63 6 VDDIO2 5 BANANA +3.3V VDDio 4 VDDio +1.5V +2.5V +1.5V +2.5V TOP LEFT [TL/0] VDDio VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS +3.3V C29 C30 1 100NF 100NF 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 1 of 1 5 4 3 2 1 POWER SEQUENCER GUARANTEES 1.5V IS ALWAYS PRESENT BEFORE 2.5V, OR 3.3V R90 +5V 4.7K 1 D PWR_EN D 2 VCONTROL 5 to 3.3V (3A) Regulator AMS1503CT C100 75R 100NF R112 4 22UF C99 1 3 100NF C109 SENSE VPOWEROUTPUT ADJ/GND PWR_EN Q4 2P3906 U3 124R R113 C98 C97 100NF 10UF PLACE ALL CAPS CLOSE TO INPUTS AND OUTPUTS OF REGS! 5 R162 1 3 680R Q3 22N2222 3 R92 2 4.7K +1.5V T1 T2 U4 RELAY+ +5V NO NC COMM +3.3V GND 1 2 3A Fast-Blo Socketed Fuse F1226CT-ND 1 5Vdc Coil, 10A Capacity Relay G5LE-14-DC5 Red Banana Jack 111-0102-001 G HLMP-1790 5 3 4 D22 J79 F1 3.3V GREEN LED INDICATES 3.3V PRESENCE R97 680R VCONTROL 5 to 3.3V (3A) Regulator AMS1503CT J101 C104 100NF C103 22UF T3 RELAY+ J83 J100 2A Fast Blo Socketed Fuse F1224CT-ND VCONTROL 5 to 3.3V (3A) Regulator AMS1503CT R117 24.9R 2 C107 22UF R116 124R 1 3 C111 100NF ADJ/GND 4 R103 GREEN LED INDICATES 5V PRESENT G 1520-3 Turret C106 10UF T 11 PLACE ALL CAPS CLOSE TO INPUTS U7 AND OUTPUTS OF REGS! SENSE 5 VPOWEROUTPUT C105 100NF +5V T 10 4A Slo-Blo Socketed Fuse 22HP037A F1309CT-ND Male Power Jack 2.5mm 2.5V 1 2 1x2 0.100" Header TSW-102-07-T -S GREEN LED INDICATES 2.5V PRESENCE C108 100NF Turret 1520-3 D24 HLMP-1790 2 2 1 2 270R TANT B TANT B TANT B ALCAP_F ALCAP_F ALCAP_F 1 B 1 Red Banana Jack 111-0102-001 C200 C201 C202 C203 C204 C205 F3 J84 THE SPECIFIED WALL ADAPTER CAN 3 PROVIDE UP TO 4A @ 5V. GND J82 +2.5V F2 COMM R102 Red Banana Jack 111-0102-001 +5V NO NC 5Vdc Coil, 10A Capacity Relay G5LE-14-DC5 1 1 5 3 4 1 2 1x2 0.100" Header TSW-102-07-T -S T4 +1.5V U6 +5V C J81 1 2 D23 G 1 2 3 1 2 3 1 2 1x2 0.100" Header TSW-102-07-T -S RELAY+ 1 2 3 J80 +2.5V HLMP-1790 WHEN USING 5V BANANA JACK ENSURE J101 IS IN THE 2-3 POSITION 124R R114 4 2 R115 124R ADJ/GND PWR_EN +3.3V 1 2 1 3 C110 100NF ALL LDO REGULATORS CAN SOURCE 3A AT THEIR SPECIFIED VOLTAGE C102 10UF C C101 100NF PLACE ALL CAPS CLOSE TO INPUTS U5 AND OUTPUTS OF REGS! SENSE 5 VPOWEROUTPUT B T5 1K U8 RELAY+ J85 5 3 4 +5V NO NC COMM +1.5V GND 1 2 5Vdc Coil, 10A Capacity Relay G5LE-14-DC5 1 T6 F4 1.5V 5A Slo-Blo Socketed Fuse F1310CT-ND T8 T7 Red Banana Jack 111-0102-001 J87 1 Black Banana Jack 111-0103-001 A A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 1 of 8 5 4 GP7_[32:0] B ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 L4 K2 N1 N4 P2 U2 V2 W5 Y4 AA5 AB1 AC2 AD2 AD3 AE1 AE2 GP7_7 GP7_23 GP7_31 DATA4 P5 AA4 U5 N5 GP7_0 GP7_1 GP7_3 GP7_2 GP7_4 GP7_5 GP7_11 GP7_13 GP7_6 GP7_8 GP7_9 GP7_10 GP7_12 GP7_30 GP7_15 GP7_14 GP7_28 GP7_29 GP7_27 GP7_26 GP7_25 GP7_24 GP7_22 GP7_21 GP7_19 GP7_20 GP7_18 GP7_17 K1 L2 M4 M2 N2 P1 R5 T5 P4 R1 R2 R4 T1 V5 U4 U3 V3 V4 W3 Y1 Y2 AA2 AA3 AB2 AB5 AC1 AC4 AD5 PLCK1C PLCK1T W4 AA1 PLCK0C PLCK0T T2 T3 GP7_16 GP7_32 AD4 AE3 100PF 1 URPLL1_T URPLL1_C URPPLL_T URPPLL_C B31 C30 GP2_37 J34 H34 GP2_35 J33 GP2_36 GP2_38 J32 G34 GP2_17 M30 GP2_41 H33 GP2_34 H32 GP2_33 GP2_40 L30 H31 GP2_32 G33 GP2_18 F34 GP2_19 G32 GP2_16 GP2_39 K30 G31 GP2_26 PR13B PR13A PR13C PR12C PR12D PR11A PR11C PR11D PR10A PR10C PR10D PR9A PR9D PR8C PR8D PT19A PT20A PT20C PT20D PT21A PT22A PT23B PT23A PT24B PT24A PT25C PT25D PT35A PT35B PT31D PT31C PT29A PT28A PT27D PT27C PT27A PLL_VF D30 GP1_[20:0] SLAVE SERIAL MODE SLAVE PARALLEL MODE (including DATA4) MPI_RTRY_N MPI_ACK_N MPI_TEA_N MPI_CLK A21/MPI_BURST_N ADDR20/MPI_BDIP_N ADDR19/MPI_TSZ1 ADDR18/MPI_TSZ0 ADDR17 ADDR16 PLACE CLOSE TO PLL_VF [D30] WHICH PIN IS VSSA_7? -FOR THE FILTER GND 6K E31 G30 10NF R88 PLL_CK3T PLL_CK3C GP1_0 GP1_1 GP1_2 GP1_3 GP1_4 GP1_5 GP1_6 GP1_7 GP1_8 GP1_9 GP1_11 GP1_12 GP1_17 GP1_16 GP1_18 GP1_14 GP1_15 GP1_13 GP1_19 GP1_20 GP1_10 B13 B14 A14 D15 B15 D16 A16 D17 C18 B18 C19 B19 D24 A25 E22 D21 E21 E20 A21 B21 D19 C14 PLL_CK2T PLL_CK2C PTCK1T PTCK1C DEBUG_BUS15 DEBUG_BUS14 DEBUG_BUS13 DEBUG_BUS12 DEBUG_BUS11 DEBUG_BUS10 DEBUG_BUS9 DEBUG_BUS8 DEBUG_BUS7 DEBUG_ BUS6 DEBUG_BUS5 DEBUG_BUS4 DEBUG_BUS3 DEBUG_BUS2 DEBUG_ BUS1 DEBUG_BUS0 C25 E24 B25 C24 E23 B24 B23 B22 A23 D20 A22 B20 A20 E19 A15 E17 DEBUG_BUS15 DEBUG_BUS14 DEBUG_BUS13 DEBUG_BUS12 DEBUG_BUS11 DEBUG_BUS10 DEBUG_BUS9 DEBUG_BUS8 DEBUG_BUS7 DEBUG_BUS6 DEBUG_BUS5 DEBUG_BUS4 DEBUG_BUS3 DEBUG_BUS2 DEBUG_BUS1 DEBUG_BUS0 PTCK0T PTCK0C C16 B16 C17 B17 PTCK1T PTCK1C MODE CTRL PTCK0T PTCK0C M3 M2 M1 M0 M3 M2 M1 M0 E14 C11 B12 A12 RD_DATA/TDO TMS TCK TDI E4 A9 D7 C7 CFG_IRQ_N RD_CFG_N PRGRM_N DONE CCLK RESET_N RD_DATA/TDO TMS TCK TDI E7 D2 G5 B4 E6 E3 DOUT INIT_N LDC_N HDC LDC_N HDC F1 J5 H1 J2 DOUT INIT_N DATA3 DATA2 DATA1 DATA 0 E12 A7 E11 B9 DATA3 DATA2 DATA1 DATA0 DATA7 DATA6 DATA5 TESTCFG CS0_N CS1 DATA7 DATA6 DATA 5 D1 F4 D6 C6 H3 J4 L5 TESTCFG CS0_N CS1 B11 D9 A8 B8 G1 K3 PLL_CK0C PLL_CK0T ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 2 C13 DEBUG_BUS[15:0] TOP RT [TR/2] ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 TOP CENTER [TC/1] PRCK1T PRCK1C INPUT / OUTPUT BLOCK RDY/BUSY_N/RCLK WR_N/MPI_RW RD_N/MPI_STRB_N DATA4 PL15D PL15C PL17D PL17C PL20D PL20C PL20A PL21A PL22D PL22C PL22A PL22B PL23A PL23B PL24B PL24A PL25B PL25A PL27D PL27C PL27A PL28A PL29A PL31D PL33D PL33C PL35A PL37A PR33B PR32B PR34A PR30A PR28A PR31A PR27A PR29B PR26A PR22A PR23A PR20A PR21A PR19B PR17A PR18B PR15A PR16D PR14A OR4E MFR: LATTICE PKG: 680PBGA PLCK1C PLCK1T/SCKB PR35C/L1T_D1 PR35D/L1C_D1 PR34C/L2T_D1 PR34D/L2C_D1 PR33D/L3C_D1 PR32C/L4T_D0 PR32D/L4C_D0 PR31C/L5T_A0 PR30C/L6T_D1 PR30D/L6C_D1 PR29C/L7T_D3 PR28C/L8T_D1 PR28D/L8C_D1 PR26C/L10T_A0 PR25C/L11T_A0 PR25D/L11C_A0 PR24A/L12T_A0 PR24B/L12C_A0 PR23D/L14C_A0 PR22C/L15T_D1 PR22D/L15C_D1 PR21C/L16T_A1 PR20C/L17T_A1 PR20D/L17C_A1 PR19C/L18T_A1 PR19D/L18C_A1 PR18C/L19T_A1 PR18D/L19C_A1 PR17D/L20C_D1 PR15C/L21T_A0 PR15D/L21C_A0 PR14D/L22C_D2 BOT RT [BR/4] PLCK0C PLCK0T/SCKA DATA[31:0] 5 4 GP5_[7:0] 3 GP4_[9:0] 2 L21C_D3 L21T_D3 L20T_S1 L19C_D2 L19T_D2 L18T_D0 AN29 AM28PB43D AM26PB43A AK27 PB37A AH32 PB42C AG34PR39A AF33 PR36A AF32 PR36B AF30 PR37A AE30 PR40A PR38A AF34 AD30 PR36D/L21C_D3 AG33PR36C/L21T_D3 AF31 PR37C/L20T_D1 AH34 PR38D/L19C_D2 AG32PR38C/L19T_D2 PR39C/L18T_D0 GP4_9 GP4_8 GP4_7 GP4_6 GP4_5 GP4_4 GP4_3 GP4_2 GP4_1 GP4_0 L4C_S0 L4T_S0 L10C_S0 L10T_S0 GP6_25 GP6_15 GP6_29 GP6_32 GP6_33 GP6_34 GP6_22 GP6_35 GP6_20 GP6_19 GP6_30 GP6_21 GP6_18 GP6_13 GP6_17 GP6_31 GP6_27 GP6_16 GP6_36 GP6_28 ORCA BOTTOM CENTER [BC/5] L1T_D2 L1C_D2 L2C_A1 L3T_A1 L3C_A1 L5T_A1 L5C_A1 L6C_S0 L7T_A0 L7C_A0 L8T_S0 L9T_S0 L9C_S0 L11T_S0 L11C_S0 L12T_S0 L13T_T2 L13C_T2 L14T_A3 L15T_A0 L15C_A0 L16T_D2 L16C_D2 L17T_D3 L18T_A0 L18C_A0 PL38A PL40D PL41D PL41C PL43D PL43C PL44B PL45D PL45A PL46D PL46A PL47B PL47A PB2B PB3A AN26 AN25 PB36A AN15 PB35A AL20 PB21A AL16 PB27A AK21 PB22A AK20 PB30A AK19 PB29A PB28A AN16 AK17 PB21C/L1T_D2 AP16 PB21D/L1C_D2 AN17 PB22D/L2C_A1 AL17 PB23A/L3T_A1 AL18 PB23B/L3C_A1 AN18 PB24A/L5T_A1 AK18 PB24B/L5C_A1 AM19PB24D/L6C_D0 AN19 PB25C/L7T_A0 AP20 PB25D/L7C_A0 AP21 PB26C/L8T_A0 AN21 PB27C/L9T_A0 AP22 PB27D/L9C_A0 AN22 PB29C/L11T_A0 AL22 PB29D/L11C_A0 AK22 PB30C/L12T_A0 AN23 PB31C/L13T_D2 AP23 PB31D/L13C_D2 AN24 PB32C/L14T_A3 AM24PB33C/L15T_A0 AL24 PB33D/L15C_A0 AP25 PB34C/L16T_D2 AK24 PB34D/L16C_D2 AL25 PB35C/L17T_D3 AM25PB36C/L18T_A0 PB36D/L18C_A0 AL21 AM21PBCK1C PBCK1T AM18 AM17PBCK0C PBCK0T BOTTOM LEFT [BL/6] DP2 DP3 GP5_7 GP5_6 GP5_5 GP5_4 GP5_3 GP5_2 GP5_1 GP5_0 AE4 AE5 AG2 AF5 AH1 AH3 AH2 AJ2 AJ3 AJ4 AJ1 AJ5 AK3 AM5 AP4 AL6 AM6 PB3C AK8 PB3D AP5 PB5C AP6 PB5D AL8 PB7C AN7 PB7D AL9 PB9A AN8 PB10A AN9 PB11A AK12 PB12A AL11 PB13A AN11 PB13B AM11PB14A AN12 PB14B AK14 PB15C AL13 PB15D AN13 PB17C AN14 PB17D AL14 PB19A PB20A DATA31AL15 DATA 30AK16 DATA31 DATA29AM14DATA30 DATA28AK15 DATA29 DATA27AP13 DATA28 DATA26AP12 DATA27 DATA 25AL12 DATA26 DATA24AP10 DATA25 DATA23AN10 DATA24 DATA22AM10DATA23 DATA21AP8 DATA22 DATA 0 DATA 20AL10 DATA21 DATA1 DATA19AM9 DATA20 DATA2 DATA18AP7 DATA19 DATA3 DATA17AK10 DATA18 DATA4 DATA16AM8 DATA17 DATA 5 DATA 15AM7 DATA16 DATA6 DATA14AK9 DATA15 DATA7 DATA13AG5 DATA14 DATA12AG4 DATA13 DATA11AG3 DATA12 DATA 10AF4 DATA11 DATA9 AF3 DATA10 DATA8 AF1 DATA9 DATA8 AK7 LLPPLL_T AN4 PLL_CK6C PLL_CK6T LLPPLL_C AK1 LLHPPLL_C AK2 PLL_CK7C LLHPPLL_T PLL_CK7T AL1 LVDS_R 100R R89 AK4 PTEMP PTEMP A AL5 AN5 GP6_0 GP6_1 GP6_3 GP6_2 GP6_4 GP6_6 GP6_5 GP6_8 GP6_9 GP6_10 GP6_7 GP6_11 GP6_12 GP6_24 GP6_23 PLL_CK4T PLL_CK4C PLL_CK5T PLL_CK5C DP0 DP1 GP6_[36:0] GP6_26 GP6_14 PR7C PR6A PR6C PR6D PR5C PR5D PR4C PT46D PT46C PT45C PT44D PT44C PT43D PT43C PT42C PT41D PT41C PT40D PT39D PT39C PT38D PT37D PT37A PT36D PT36C PT36A PT36B PRCK0C PRCK0T TOP LEFT [TL/0] CENTER RIGHT [CR/3] ADDR[21:0] C E16 D14 D11 E15 JTAG CENTER LEFT [CL/7] ADDR[21:0] GP0_17 GP0_18 GP0_21 GP0_16 PL3D PL5D PL7D PL7C PL11D PL11C PL11A PL13A PT17D PT12D PT12C PT12A PT11C PT11A PT7C PT5D PT4B PT4A PT3D PT3B PT3A PT2B PT2A CFG_IRQ_N/MPI_IRQ_N RD_CFG_N PRGRM_N DONE CCLK RESET_N D F3 E1 H4 G3 J3 H2 K4 M5 C14 A10 B10 C10 D10 E13 D8 A6 E10 A5 B6 A4 B5 C5 E8 PLL_CK1C PLL_CK1T U1B GP0_6 GP0_7 GP0_4 GP0_5 GP0_2 GP0_3 GP0_1 GP0_0 GP0_19 GP0_23 GP0_22 GP0_24 GP0_25 GP0_20 GP0_15 GP0_13 GP0_26 GP0_11 GP0_12 GP0_9 GP0_10 GP0_8 GP0_14 4.7K G2 H5 E2 R87 ULPPLL_T ULPPLL_C GP0_[26:0] 3 +3.3V ULHPPLL_T ULHPPLL_C PB37C/L1T_A0 PB37D/L1C_A0 PB38D/L2C_D0 PB39C/L3T_D1 PB39D/L3C_D1 PB40C/L4T_A0 PB41C/L5T_A0 PB41D/L5C_A0 PB44C/L6T_D1 PB45A/L7T_A2 PB45B/L7C_A2 PB45C/L8T_A0 PB45D/L8C_A0 PB46C/L9T_D1 PR45C/L12T_D2 PR45D/L12C_D2 PR44D/L13C_D2 PR43C/L14T_D0 PR43D/L14C_D0 PR42C/L15T_D2 PR42D/L15C_D2 PR41D/L16C_D0 PR40C/L17T_D2 PR40D/L17C_D2 E34 GP2_21 D34 GP2_23 F32 GP2_20 F31 GP2_27 E33 GP2_22 D33 GP2_24 H30 GP2_28 E28 GP2_14 B30 GP2_29 A31 GP2_25 D28 GP2_13 B29 GP2_31 E27 GP2_6 C29 GP2_15 E26 GP2_5 A29 GP2_30 D27 GP2_7 GP2_12 C28 GP2_11 B28 E25 GP2_0 A28 GP2_10 C26 GP2_4 B27 GP2_9 D25 GP2_1 A27 GP2_8 A26 GP2_2 B26 GP2_3 D GP2_[41:0] U31 T34 L13C_D2 L13T_D2 Y34 W33 L9T_A0 L9C_A0 AE34 AD33 AD31 AC34 AA34 AA31 Y33 Y31 W32 U30 T33 T30 R33 R30 P30 N34 L33 L31 K32 GP3_18 GP3_17 GP3_16 GP3_15 GP3_14 GP3_13 GP3_12 GP3_11 GP3_10 GP3_9 GP3_8 GP3_7 GP3_6 GP3_5 GP3_4 GP3_3 GP3_2 GP3_1 GP3_0 AE32 AC30 AE33 AC31 AB30 AB31 AA30 AC33 AA32 Y30 AB34 AA33 W31 V30 V33 V32 U33 U32 T31 R31 R34 P34 P31 P33 N33 N31 M31 M33 L32 K34 K33 K31 L1T_D1 L1C_D1 L2T_D1 L2C_D1 L3C_D1 L4T_D0 L4C_D0 L5T_A0 L6T_D1 L6C_D1 L7T_D3 L8T_D1 L8C_D1 L10T_A0 L11T_A0 L11C_A0 L12T_A0 L12C_A0 L14C_A0 L15T_D1 L15C_D1 L16T_A1 L17T_A1 L17C_A1 L18T_A1 L18C_A1 L19T_A1 L19C_A1 L20C_D1 L21T_A0 L21C_A0 L22C_D2 C B LRPLL2_T L11T_D1 LRPLL2_C L11C_D1 LRPPLL_T L10T_D2 L10C_D2 LRPPLL_C AJ30 AK32 AL30 AP31 AP27 AN27 AL26 AM27 AK26 AP28 AL27 AL28 AK28 AL29 AP29 AP30 AN30 AK29 AL33 AH30 AJ31 AJ32 AH31 AK33 AG30 AJ33 AJ34 AG31 GP3_[18:0] L1T_A0 L1C_A0 L2C_D0 L3T_S1 L3C_S1 L4T_A0 L5T_S0 L5C_S0 L6T_S1 L7T_A2 L7C_A2 L8T_A0 L8C_A0 L9T_D1 L12T_D2 L12C_D2 L13C_S2 L14T_D0 L14C_D0 L15T_D2 L15C_D2 L16C_D0 L17T_D2 L17C_D2 A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 3 of 8 4 3 GENERAL PURPOSE FREQUENCY SOURCES 2 1 POST CONFIG/MISC I/O HDR CS CONTROLS/GPIO J37 Y1 100NF C1 14 7 VCC 8 R3 OUT GND 22R R6 R8 1 NC OPEN-0603 OPEN-0603 DIP14 Oscillator Socket 110-93-314-41-001 D J24 SMA 50r Connector 901-143-6 +3.3V 1UH 1.6R 1 2 3 1x3 0.100" Jumper Header TSW-103-07-T -S 2 VCC 3 R13 OUT GND 1 NC 100R 100R 100R 100R 100R OPEN-0603 OPEN-0603 100NF C3 8 R20 OUT 22R 7 1 GND NC DIP14 Oscillator Socket 110-93-314-41-001 J34 1 2 3 SMA 50r Connector 901-143-6 680R R42 680R R43 680R R44 680R R45 680R R46 680R R49 680R R R D1 2 D2 VCC 8 7 6 5 1 2 3 1 2 3 3 R37 OUT OPEN-0603 OPEN-0603 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 +3.3V DONE 1N4148 R71 1UH CCLK PRGRM_N DATA[31:0] 10K 100NF 47UF 13 14 15 16 17 18 19 20 21 22 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0_A DATA0_A VCC NC GND BEn B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 4.7K D9 R51 R48 1N4148 100NF C6 JTAG PORT J54 JUMPER MUST BE ON IN ORDER TO USE 1 BUFFER 2 1x2 0.100" Header TSW-102-07-T -S 1 23 J56 11 10 9 8 7 6 5 4 3 2 10 Bit Quick Switch IDTQS3861SO DONE INIT_N DONE INIT_N L12C_A0 0R C129 +3.3V R158 R152 R159 0R L17T_D3 C130 B +3.3V R160 R153 R161 0R L17C_D3 C131 USE CAUTION IF JUMPING IS DESIRED +3.3V 1 2 U2 24 12 7 Pin Serial Connector 103906-6 DATA0_A C7 C8 R151 R157 INIT_N 2 3 4 5 6 7 8 9 11 13 15 16 17 1 10 12 14 18 19 20 21 22 23 24 25 L7 CCLK VDD PROG_N GND D7 GND D6 GND D5 GND D4 GND D3 GND D2 GND D1 GND D0 GND DONE GND INIT_N GND L10 GND Female DB25 w/ non-standard pinout 747846-2 TDI TMS TCK RD_DATA/TDO RD_CFG_N INIT_N 1UH 1UH J55 L6 R78 R79 R80 R82 1UH 100R 100R 100R 100R R85 100R C9 C10 C11 C12 L9 3 Q1 22N2222 +3.3V R156 4.7K 4.7K 4.7K 4.7K D21 J57 VDD CCLK D0 DONE PROG NC GND 10K 1 R73 R74 R75 R76 R77 CCLK DATA0_A DONE PRGRM_N R69 ASSUME POWER WILL BE SUPPLIED THROUGH PARALLEL CABLE LOPEN DIODE DROPS VOLTAGE FROM 5 TO 4.3V. RESULT IS AN OUTPUT VOLTAGE EQUAL TO 4.3V-1V = 3.3V 4.7K A 100R D17 R D20 L12T_A0 0R C128 ALL BIASING NETWORKS ARE LEFT OPEN AT TIME OF BUILD 47PF 47PF 47PF 47PF D16 +3.3V 1 2 3 4 5 6 7 R47 RED LED INDICATES 1ST STAGE OF CONFIGURATION IN PROGRESS PARALLEL +5V PORT L5 1UH 100R 100R 100R 100R 1N4148 GREEN LED INDICATES COMPLETION OF CONFIGURATION LOAD D15 SERIAL PORT L8 R81 R83 R84 R86 4.7K D8 R50 D14 J47 OPEN-0603 OPEN-0603 OPEN-0603 OPEN-0603 R +3.3V OPEN1 OPEN2 OPEN3 OPEN4 680R J43 R150 R155 R 680R R68 R 8 1 8 7 2 7 6 3 6 5 4 5 2x4 0.100" Header TSW-104-07-T -D DONE AND INIT_N STATUS LEDS 2x8 0.100" Header TSW-108-07-T-D G R66 R 1 2 3 4 RESET_N Momentary Switch B3F-1150 R61 680R G Momentary Switch B3F-1150 J53 680R R64 G D13 SW5 PRGRM_N R60 680R D12 SW4 680R 680R R62 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D19 HLMP-1700 R58 G D10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D18 HLMP-1790 680R D7 J40 R154 R72 680R R56 Vtt 100NF C5 R54 G R63 1/4W RESISTOR SOCKET (0.025") J52 Red Banana Jack 111-0102-001 D5 100R 680R Y R59 SHARED LVDS/SMA CONNECTORS J35 4.7K B R52 Y R57 2x4 0.100" Header TSW-104-07-T -D PROGRAM AND RESET SWITCHES J46 1 2 3 4 5 6 7 8 1x8 0.100" Header TSW-108-07-T -S R70 D3 D6 J51 1 2 3 4 5 6 7 8 R65 +3.3V Y THIS BOARD J49 R D4 Y CS0_N C +3.3V R38 R40 100R R67 22R 1 GND NC 66MHz Oscillator VCC1-B0B-66M000 R10 R55 Vr2 SMA 50r Connector SMA 50r Connector SMA 50r Connector SMA 50r Connector 901-143-6 901-143-6 901-143-6 901-143-6 R41 R 4 8 7 6 5 CS1 R53 J45 Red Banana Jack 111-0102-001 Y4 100NF C4 NOTE: THESE LEDs ARE DESIGNED TO OPERATE ON 3.3V. IF A LOWER VOLTAGE IS APPLIED LIGHT MAY BE DIM OR NIL. R39 680R 1UH 1.6R 1 2 3 4 100R D 1 2 1x2 0.100" Header TSW-102-07-T-S 1 L4 R34 1 2 1x3 0.100" Jumper Header TSW-103-07-T -S C GENERAL PURPOSE HEADER CONNECTED TO 16 LEDS OPEN-0603 OPEN-0603 R7 +3.3V J27 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1x8 0.100" Header TSW-108-07-T -S 2x4 0.100" Header TSW-104-07-T -D J38 +3.3V 1 2 3 4 +3.3V R21 R22 1 2 DEFAULT CHIP SELECT: 1 Y3 VCC 1 2 RESISTOR SOCKETS J50 J42 14 J23 Vr1 15MHz Oscillator VCC1-B0B-15M000 1UH 1.6R M3 M2 M1 M0 DONE 1x2 0.100" Header TSW-102-07-T-S +3.3V L3 R19 R27 R29 R31 R33 R36 J39 Red Banana Jack 111-0102-001 +3.3V 22R R14 R15 16 1 16 15 2 15 14 3 14 13 4 13 12 5 12 11 6 11 10 7 10 9 8 9 2x8 0.100" Header TSW-108-07-T-D GENERAL PURPOSE BANANAS Y2 4 100NF C2 L2 R12 1 2 3 +3.3V 1 2 3 4 5 6 7 8 100R ARE INTENDED TO PROTECT IC AGAINST EXTERNAL DRIVING OF PINS DURING CONFIG. OPERATION IS NOT GUARANTEED IF THESE PINS ARE DRIVEN DURING CONFIG/RESET. J28 1 2 3 100R 100R 100R 100R 100R 100R 100R 100R R2 RESISTOR OPTIONS TO SUPPORT ACTIVE LOW OR ACTIVE HIGH ENABLE +3.3V 1UH 1.6R R23 R24 R25 R26 R28 R30 R32 R35 4.7K SOCKET SUPPORT FOR DIP14 OSCILLATORS L1 R1 PTEMP DOUT INIT_N TESTCFG HDC LDC_N RD_CFG_N RESET_N 4.7K +3.3V R11 5 L11 1 2 3 4 5 6 7 8 VDD TDI TMS TCK TDO RD_CFG INIT_N GND 8 Pin JTAG Connector 103906-7 A 1UH Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 4 of 8 4 3 GP0_[26:0] D GP1_[20:0] J1 GP0_0 GP0_1 GP0_2 GP0_3 GP0_4 GP0_5 GP0_6 GP0_7 GP0_8 GP0_9 GP0_10 GP0_11 GP0_12 GP0_13 GP0_14 GP0_15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 J2 GP1_0 GP1_1 GP1_2 GP1_3 GP1_4 GP1_5 GP1_6 GP1_7 GP1_8 GP1_9 GP1_10 GP1_11 GP1_12 GP1_13 GP1_14 GP1_15 CCLK GP0_26 GP0_25 GP0_24 GP0_23 GP0_22 GP0_20 GP0_19 2x16 0.100" Header TSW-116-07-T -D 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 PLCK0C PLCK0T PLCK1C PLCK1T 1x8 0.100" Header TSW-108-07-T -S CENTER LEFT J8 J6 32 1 32 31 2 31 30 3 30 29 4 29 28 5 28 27 6 27 26 7 26 25 8 25 24 9 24 23 10 23 22 11 22 21 12 21 20 13 20 19 14 19 18 15 18 17 16 17 2x16 0.100" Header TSW-116-07-T -D GP7_0 1 GP7_1 2 GP7_2 3 GP7_3 4 GP7_4 5 GP7_5 6 GP7_6 7 GP7_7 8 GP7_8 9 GP7_9 10 GP7_1011 GP7_1112 GP7_1213 GP7_1314 GP7_1415 GP7_1516 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P T CK0T GP7_30 GP7_29 GP7_28 GP7_27 GP7_26 GP7_25 GP7_24 GP7_22 GP7_21 GP7_20 GP7_19 GP7_18 GP7_17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PTCK0C P T CK1T PTCK1C GP1_20 GP1_19 GP1_18 GP1_17 GP1_16 GP2_32 GP2_33 GP2_34 GP2_35 GP2_36 GP2_37 GP2_38 GP2_39 GP2_40 GP2_41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J5B J4 GP2_0 GP2_1 GP2_2 GP2_3 GP2_4 GP2_5 GP2_6 GP2_7 GP2_8 GP2_9 GP2_10 GP2_11 GP2_12 GP2_13 GP2_14 GP2_15 2x8 0.100" Header TSW-108-07-T-D TOP CENTER 1 GP2_[41:0] J3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 2x16 0.100" Header TSW-116-07-T-D TOP LEFT GP7_[32:0] 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 3x16 0.100" Header TSW-116-07-T-T GP2_31 GP2_30 GP2_29 GP2_28 GP2_27 GP2_26 GP2_25 GP2_24 GP2_23 GP2_22 GP2_21 GP2_20 GP2_19 GP2_18 GP2_17 GP2_16 2x16 0.100" Header TSW-116-07-T -D TOP RIGHT INPUT / OUTPUT HEADERS CENTER RIGHT 5 GP3_[18:0] GP3_0 GP3_1 GP3_2 GP3_3 GP3_4 GP3_5 GP3_6 GP3_7 GP3_8 GP3_9 GP3_10 GP3_11 GP3_12 GP3_13 GP3_14 GP3_15 (by bank) J7 32 1 32 31 2 31 30 3 30 29 4 29 28 5 28 27 6 27 26 7 26 25 8 25 24 9 24 23 10 23 22 11 22 21 12 21 20 13 20 19 14 19 18 15 18 17 16 17 2x16 0.100" Header TSW-116-07-T -D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 L1T_D1 L2T_D1 L3T_D1 L4T_D0 L5T_A0 L6T_D1 L7T_D3 L8T_D1 L9T_A0 L10T_A0 L11T_A0 L12T_A0 L13T_D2 L14T_A0 L15T_D1 L16T_A1 GP3_18 GP3_17 GP3_16 J11 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1x8 0.100" Header TSW-108-07-T -S GP6_[36:0] GP6_32 GP6_33 GP6_34 GP6_35 GP6_36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GP6_15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 2x16 0.100" Header TSW-116-07-T-D J13 GP5_0 GP5_1 GP5_2 GP5_3 GP5_4 GP5_5 GP5_6 GP5_7 GP6_31 GP6_30 GP6_29 GP6_28 GP6_27 GP6_25 GP6_24 GP6_23 GP6_22 GP6_21 GP6_20 GP6_19 GP6_18 GP6_17 GP6_16 BOTTOM RIGHT GP4_[9:0] 1 2 3 4 5 6 7 8 GP4_0 GP4_1 GP4_2 GP4_3 GP4_4 GP4_5 GP4_6 GP4_7 1 2 3 4 5 6 7 8 1x8 0.100" Header TSW-108-07-T -S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 L1C_D2 L2C_A1 L3C_A1 L4C_S0 L5C_A1 L6C_S0 L7C_A0 L8C_S0 L9C_S0 L10C_S0 L11C_S0 L12C_S0 L13C_T 2 L14C_A3 L15C_A0 L16C_D2 J20 DEBUG_BUS0 DEBUG_BUS1 DEBUG_BUS2 DEBUG_BUS3 DEBUG_BUS4 DEBUG_BUS5 DEBUG_BUS6 DEBUG_BUS7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 J18A L17T_D3 L18T_A0 DEBUG_BUS15 DEBUG_BUS14 DEBUG_BUS13 DEBUG_BUS12 DEBUG_BUS11 DEBUG_BUS10 DEBUG_BUS9 DEBUG_BUS8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 L17C_A1 L18C_A1 L19C_A1 L20C_D1 L21C_A0 L22C_D2 C J9B 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 3x8 0.100" Header TSW-108-07-T-T GP4_9 GP4_8 L17C_D3 L18C_A0 L17T_D2 L18T_D0 L19T_D2 L20T_S1 L21T_D3 J18B J14B 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 3x8 0.100" Header TSW-108-07-T-T 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 3x16 0.100" Header TSW-116-07-T-T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 L1C_A0 L2C_D0 L3C_S1 L4C_A0 L5C_S0 L6C_S1 L7C_A2 L8C_A0 L9C_D1 L10C_D2 L11C_D1 L12C_D2 L13C_S2 L14C_D0 L15C_D2 L16C_D0 ANY NETS SHOWING A TRUE AND COMPLEMENT WERE ROUTED AS LVDS PAIRS B TSW-116-07-T-T 3x16 0.100" Header 3x8 0.100" Header TSW-108-07-T-T TSW-108-07-T-D 2x8 0.100" Header 8 7 6 5 4 3 2 1 J15A L1T_A0 L2T_D0 L3T_S1 L4T_A0 L5T_S0 L6T_S1 L7T_A2 L8T_A0 L9T_D1 L10T_D2 L11T_D1 L12T_D2 L13T_S2 L14T_D0 L15T_D2 L16T_D0 3x16 0.100" Header TSW-116-07-T-T DEBUG_BUS[15:0] J10 16 1 16 15 2 15 14 3 14 13 4 13 12 5 12 11 6 11 10 7 10 9 8 9 2x8 0.100" Header TSW-108-07-T -D 1 2 3 4 5 6 7 8 J14A L1T_D2 L2T_A1 L3T_A1 L4T_S0 L5T_A1 L6T_S0 L7T_A0 L8T_S0 L9T_S0 L10T_S0 L11T_S0 L12T_S0 L13T_T2 L14T_A3 L15T_A0 L16T_D2 B GROUPED BUS LINES 8 7 6 5 4 3 2 1 3x8 0.100" Header TSW-108-07-T-T GP5_[7:0] J12 GP6_0 GP6_1 GP6_2 GP6_3 GP6_4 GP6_5 GP6_6 GP6_7 GP6_8 GP6_9 GP6_10 GP6_11 GP6_12 GP6_13 BOTTOM CENTER L1C_D1 L2C_D1 L3C_D1 L4C_D0 L5C_A0 L6C_D1 L7C_D3 L8C_D1 L9C_A0 L10C_A0 L11C_A0 L12C_A0 L13C_D2 L14C_A0 L15C_D1 L16C_A1 J9A L17T_A1 L18T_A1 L19T_A1 L20T_D1 L21T_A0 L22T_D2 C BOTTOM LEFT J5A 17 16 17 18 15 18 19 14 19 20 13 20 21 12 21 22 11 22 23 10 23 24 9 24 25 8 25 26 7 26 27 6 27 28 5 28 29 4 29 30 3 30 31 2 31 32 1 32 TSW-116-07-T-T 3x16 0.100" Header 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D J19A 9 8 9 10 7 10 11 6 11 12 5 12 13 4 13 14 3 14 15 2 15 16 1 16 TSW-108-07-T-T 3x8 0.100" Header 8 7 6 5 4 3 2 1 L17C_D2 L18C_D0 L19C_D2 L20C_S1 L21C_D3 J19B 17 18 19 20 21 22 23 24 J15B 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 3x16 0.100" Header TSW-116-07-T-T 3x8 0.100" Header TSW-108-07-T-T A A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 5 of 8 5 4 3 2 1 D D +3.3V +3.3V +3.3V +3.3V J103 URPPLL_T URPPLL_C R133 R132 R123 R122 R131 R130 J109 J108 URPLL1_T URPLL1_C R125 R124 ULHPPLL_T ULHPPLL_C ULPPLL_T ULPPLL_C R129 R128 R121 R120 R119 R118 R127 R126 J107 J104 J106 J110 J105 C119 C118 C115 C114 C113 C112 C117 C116 C C +3.3V +3.3V J115 +3.3V J112 LRPPLL_T LRPPLL_C LLPPLL_T LLPPLL_C J116 LRPLL2_T LRPLL2_C J117 B R149 R148 R141 R140 R147 R146 R139 R138 J113 R145 R144 R137 R136 LLHPPLL_T LLHPPLL_C B R143 R142 R135 R134 J111 +3.3V J114 J118 C127 C126 C123 C122 C125 C124 C121 C120 A A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 6 of 8 5 4 3 D 2 1 D GENERAL PURPOSE HEADER CONNECTED TO 16 DIP SWITCHES RN8D RN8C RN8B RN8A RN9D RN9C RN9B RN9A RN10D RN10C RN10B RN10A 4 3 2 1 4 3 2 1 4 3 2 1 1 RN11A RN7A 2 RN11B RN7B 1 CONFIG MODE CONTROL 3 RN11C RN7C 2 1 2 3 J120 1 1 2 2 3 3 4 RN11D RN7D 3 J121 8 47K 7 47K 6 47K 5 47K 8 47K 7 47K 6 47K 5 47K 8 47K 7 47K 6 47K 5 47K 8 47K 7 47K 6 47K 5 47K 8 47K 12 3 1 0 1 0 5 12 4 8 SW7C 7 2 SW7B 9 1 0 6 C 12 1 0 5 1 0 2 47K 1 47K 2 47K 1 47K 5 6 7 8 5 6 7 8 5 6 7 8 RN3D RN3C RN3B RN3A RN4D RN4C RN4B RN4A RN5D RN5C RN5B RN5A 3 47K 3 47K 8 RN2A 4 47K 3 47K 7 RN2B 4 47K 4 47K 6 RN2C 1 47K 1 47K 5 RN2D 2 47K 2 47K 8 RN1A 3 47K 2 47K 7 RN1B 4 47K 3 47K 6 1 47K 4 47K 5 RN1C B RN1D 6 4 8 SW6D 1 0 3 2 SW6C 7 1 0 1 11 SW6B 9 1 0 6 5 SW6A 10 1 0 4 8 SW3D 1 0 3 2 SW3C 7 1 0 1 11 SW3B 9 1 0 6 5 12 1 0 SW3A 10 8 4 3 1 0 SW2D 2 TSW-108-07-T-D 2x8 0.100" Header 1 0 SW2C 7 1 0 SW2B 9 11 SW2A 10 1 0 6 5 SW1D 1 0 4 8 11 SW1C 7 1 0 SW7A 10 M0 M1 M2 M3 SW1B 9 2 1 12 SW1A 10 1 0 1 11 1 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Red Banana Jack 111-0102-001 Red Banana Jack 111-0102-001 J29 7 47K 1 6 47K 5 47K J122 Note: It is preferrable to ensure switches are OFF following configuration if M[3:0] are to be used as GPio. SW7D 1 2 3 4 +3.3V J119 +3.3V 1 1 2 2 3 3 B A A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 7 of 8 5 4 3 1 ADDR21 ADDR20 ADDR19 ADDR18 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 R227 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K +3.3V R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 +3.3V 2 ADDR[21:0] C B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 J1114 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 CONN_A19 CONN_A20 CONN_A21 CONN_A22 CONN_A23 CONN_A24 CONN_A25 CONN_A26 CONN_A27 CONN_A28 CONN_A29 CONN_A30 CONN_A31 CONN_A32 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 Note: Jumper selects DATA0 between 7 pin serial connector (page 2) and 860 bus. +3.3V R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 ADDR[21:0] 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K D 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K GP0_[26:0] J1113 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 DATA[31:0] DATA0_B DATA0 DATA0_B DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA0_A 650908 J36 1 2 3 1 2 3 1 2 3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ADDR19 ADDR18 GP7_23 ADDR21 ADDR20 MPI_TSZ1 MPI_TSZ0 MPI_RW MPI_BURST_N MPI_BDIP_N GP7_31 GP0_18 GP0_21 MPI_STRB_N MPI_ACK_N MPI_TEA_N GP0_16 GP7_16 GP7_32 GP6_26 GP6_14 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 GP0_17 CFG_IRQ_N 650908 GP0_21 GP0_18 GP0_17 GP0_16 J1115 MPI_CLK DP0 DP1 DP2 DP3 MPI_RTRY_N MPI_IRQ_N A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D GP7_[32:0] GP7_32 GP7_31 GP7_23 GP7_16 GP6_[36:0] GP6_26 GP6_14 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 C J21 ADDR19 ADDR18 GP7_23 ADDR21 ADDR20 GP7_31 GP0_18 GP0_21 GP0_16 GP7_16 GP7_32 GP6_26 GP6_14 GP0_17 CFG_IRQ_N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 2x16 0.100" Header TSW-116-07-T -D J16 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 32 1 32 31 2 31 30 3 30 29 4 29 28 5 28 27 6 27 26 7 26 25 8 25 24 9 24 23 10 23 22 11 22 21 12 21 20 13 20 19 14 19 18 15 18 17 16 17 2x16 0.100" Header TSW-116-07-T -D DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CONN_A32 CONN_A31 CONN_A30 CONN_A29 CONN_A28 CONN_A27 CONN_A26 CONN_A25 CONN_A24 CONN_A23 CONN_A22 CONN_A21 CONN_A20 CONN_A19 ADDR17 ADDR16 B J17 650908 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 2x16 0.100" Header TSW-116-07-T -D A A Title LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD Size C Date: 5 4 3 2 Document Number Rev 2.0 Thursday, March 28, 2002 1 Sheet 8 of 8