LatticeECP2M™ PCI Express x4 Evaluation Board – Revision B User’s Guide January 2009 Revision: EB34_01.2 Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Introduction This user’s guide describes the LatticeECP2M PCI Express x4 Evaluation Board Revision B featuring the LatticeECP2M FPGA device. The evaluation board has been designed to support the LatticeECP2M35 device and the LatticeECP2M50 device. Different versions of the evaluation board are available that contain either the LatticeECP2M35 device or the LatticeECP2M50 device. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to PCI Express protocols and SERDES bridge interfaces using SMA interconnections. The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test and measurement equipment. Please note that boards populated with the LatticeECP2M-35 device have all available SERDES channels routed to the PCI Express, and in this case the SMAs are not active. The SMAs are available in larger density LatticeECP2M FPGAs fitting the same footprint, but with additional SERDES channels. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces. The board has several debugging and analyzing features for complete user evaluation of the LatticeECP2M device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeECP2M FPGA. This document describes boards marked with “Rev B” on the PCB silkscreen, next to the Lattice logo. For boards marked “Rev A”, refer to the LatticeECP2M PCI Express x4 Evaluation Board - Revision A User’s Guide. Figure 1. LatticeECP2M PCI Express x4 Evaluation Board - Revision B Board Features • SERDES interface to x4 PCI Express edge fingers • DDR2 memory device • SERDES high-speed interface SMA test points (active with LatticeECP2M-50 and larger FPGAs only) and clock connections • Power connections and power sources • ispVM® programming support 2 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor • On-board and external reference clock sources • Interchangeable clock oscillators • ORCAstra demonstration software interface via standard ispVM JTAG connection • Various high-speed layout structures • User defined input and output points • SMA connectors included (10) for high-speed clock or data interfacing • Performance monitoring via test headers, LEDs and switches The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 1 shows the functional partitioning of the board. Figure 2. LatticeECP2M PCI Express x4 Evaluation Board Revision B SMAs for a Single Quad of Generic SERDES Applications ispVM/JTAG PCI Express (x4) Edge Fingers LatticeECP2Mxx 672 fpBGA 8 LVDS Paired SMAs for Demo of LVDS I/O Performance FPGA Loader 4 SMAs for External Clock Sources Oscillators SPI Flash Device General Purpose I/Os Switches/LEDs DDR2 Memory Component 3 Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 3. LatticeECP2M PCI Express x4 Evaluation Board Revision B, Top View Additional Resources For additional information and resources related to this board, including updated documentation and software demos, please see the Lattice web site at: www.latticesemi.com/boards, and navigate to the appropriate page for this board. Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development. However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout in the user's application may significantly affect circuit performance and reliability. LatticeECP2M Device This board features a LatticeECP2M FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeECP2M devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP2M Family Data Sheet on the Lattice web site at www.latticesemi.com. Note: The connections referenced in this document refer to the LFE2M35E-FF672 device. Available I/Os and associated sysIO™ banks may differ for other densities within this device family. Applying Power to the Board The LatticeECP2M PCI Express x4 Evaluation Board is ready to power on. The board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench top supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board. To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J1 and plug the wall transformer into an AC wall outlet. 4 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor Power Supplies (see Appendix A, Figure 7) The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided for use with a bench top supply adjusted to provide a nominal 12V DC. All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies Table 1. Board Power Supply Fuses (see Appendix A, Figure 6) F1 1.2V Core Fuse F2 1.5V Fuse F3 3.3V Fuse F4 1.2V Fuse F5 2.5V Fuse F6 1.8V Fuse Table 2. Board Power Supply Indicators (see Appendix A, Figure 6) D1 2.5V Source Good Indicator D2 3.3V Source Good Indicator D3 12V Input Good Indicator D4 1.2V VCC Core Source Good Indicator D5 1.5V Source Good Indicator D6 1.8V Source Good Indicator D7 1.2V Source Good Indicator External power can be alternatively connected rather than the wall transformer power pack. Table 3. Board Supply Disconnects (see Appendix A, Figure 6) TB1 Screw Terminal for 12V DC Pin1 (Square PCB Pad) -> +12V DC Pin2 -> Ground PCI Express Power Interface Power can be sourced to the board via the PCB edge finger (CN1). This interface allows the user to provide power from a PCI Express host board. Programming/FPGA Configuration (see Appendix A, Figure 8) A programming header is provided on the evaluation board, providing access to the LatticeECP2M JTAG port. ispVM Download Interface J8 is an 10-pin JTAG connector, providing access to the LatticeECP2M JTAG port. It can be used in conjunction with the ispVM System software and Lattice USB download cable to program and control the device. 5 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor Table 4. ispVM JTAG Connector (see Appendix A, Figure 8) Pin 1 VCC Pin 2 TDO Pin 3 TDI Pin 4 PROGRAMN Pin 5 NC Pin 6 TMS Pin 7 GND Pin 8 TCK Pin 9 DONE Pin 10 INITN Download Procedures Requirements: • PC with ispVM System v.16.1.2 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). The latest ispVM System software can be downloaded from the Lattice web site at www.latticesemi.com/ispvm. Note: An option to install these drivers is included as part of the ispVM System setup. • ispDOWNLOAD Cable (HW-DLN-3C, HW-USBN-2A, or equivalent) JTAG Download The LatticeECP2M device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion. 1. Connect the ispDOWNLOAD Cable to the appropriate header. J8 is used for the 1x10 cable. Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2M FPGA device and render the board inoperable. 2. Connect the LatticeECP2M Evaluation Board to the appropriate power sources and power up board. 3. Start the ispVM System software. 6 Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide 4. Press the SCAN button located in the toolbar. The LatticeECP2M device should be automatically detected. 5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes. 6. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. 7 Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Configuration Status Indicators (see Appendix A, Figure 8) These LEDs indicate the status of configuration to the FPGA. • D8 (RED) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low. • D11 (GREEN) is illuminated, this indicates the successful completion of configuration by releasing the open collector DONE output pin. • D12 (GREEN) will flash indicating TDI activity. • D10 (RED) illuminated, this indicates that PROGRAMN is low. • D9 (RED) illuminated, this indicates that GSRN is low. PROGRAMN and GSRN (see Appendix A, Figure 8) These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2). Depressing the button drives a logic level “0” to the device. CFG [2:0] (see Appendix A, Figure 8) The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG programming is independent of the MODE pins and is always available to the user On-Board Flash Memory (see Appendix A, Figure 8) Two memory devices (U12 and U15) are on-board for non-volatile configuration memory storage. These two devices occupy the same Flash slot on the board. U15 is populated with an 8M or smaller 8-pin SOIC device. U12 is a 16-pin TSSOP 64M Flash device. J11 is used to control the selection of the Flash memory to be accessed. A jumper can select whether U12 or U15 is accessed by the configuration memory. Placing a jumper between pins 1 and 2 on J11 will select U12(64M Flash). Placing a jumper between pins 3 and 4 will select U15 is a 8M device. FPGA Clock Management (see Appendix A, Figure 12) The evaluation board includes various features for generating and managing on-board clocks. The clocks are generated from either input provided from SMAs (see table below) or from crystal oscillators (Y1, Y2 and Y3). Y1 is socketed for interchangeability and Y2 is a 100MHz surface-mounted oscillator which is fanned out around U1 for reference clocks with a fan-out buffer IC. Y3 is a 312.5MHZ clock oscillator that is connected to the SERDES reference clock input. SMA J14 and J15 can be used as an alternative input to the SERDES clock inputs for the L_REFCLK. This is discussed in the following section. Y1 can be a 4-pin DIP type oscillator like the Connor-infield XO-400 series. SERDES (see Appendix A, Figure 9) SERDES Reference Clock The 50-ohm terminated SMA J14 and J15 connectors are provided to supply reference clocks directly to the LatticeECP2M device. This drives clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same SERDES reference clocks. There 8 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor are several board connections that can be altered by adding and removing shunt resistors. Adding shunts to R79 and R80 will connect the output of Y3 oscillator. Shunts R67 and R69 will connect the SMAs to the REFCLK inputs. The board can also be provisioned to source the clock from the PCI Express edge fingers directly to the SERDES REFCLK pins. SERDES Channels (see Appendix A, Figure 9) DC coupled top-mounted SMA connectors connect to the three SERDES Tx and Rx channels of the L-Quad SERDES. These pins are directly coupled to the designated SMA connector creating a path for both input and output differential data. Table 5. SERDES Connectors (see Appendix A, Figure 9) SMA Channel Name SMA Channel Name J18 L_HDINP0 J19 L_HDOUTP0 J20 L_HDINP3 J21 L_HDINN0 J22 L_HDOUTN0 J23 L_HDINN3 J24 L_HDINP1 J25 L_HDOUTP1 J26 L_HDINN1 J27 L_HDOUTN1 J28 L_HDOUTP3 J29 L_HDINP2 J30 L_HDOUTP2 J31 L_HDOUTN3 J32 L_HDINN2 J33 L_HDOUTN2 SERDES PCI Express Channels (see Appendix A, Figure 9) This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge fingers (CN1) to fit directly into an x4 host receptacle. Power can be supplied directly from the PCI Express host via the edge finger connections. FPGA Test Pins (see Appendix A, Figure 14) General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS designated according to Table 6. Table 6. FPGA Test Pins (see Appendix A, Figure 11) Switch BGA Netname LED BGA NetName SW6D T30 Switch1 D16 U3 RED1 SW6C T4 Switch2 D17 U4 YELLOW1 SW6B P8 Switch3 D19 U5 GREEN1 SW6A R6 Switch4 D21 U6 BLUE1 SW5D T1 Switch5 D15 U2 RED2 SW5C U1 Switch6 D18 V1 YELLOW2 SW5B R7 Switch7 D20 W2 GREEN2 SW5A T5 Switch8 D22 V2 BLUE2 Note: LEDs will illuminate if connected to an unprogrammed FPGA pin. It is recommended that a pull-down be programmed on FPGA output pins. 9 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor 17-Segment LED Display (see Appendix A, Figure 14) General-purpose FPGA pins are connected to a 17-segment display according to the following table. These pins can be driven low to illuminate the display segments. Figure 4. 17-Segment LED Display Segment BGA A H2 B J3 C G1 D H3 E J7 F H5 G G5 H G6 K F3 M J8 N E1 P J9 R E3 S F5 T D3 U F6 DP C2 A H B K M N U G P T S F C R E D DP Test SMA Connections General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the evaluation of several types of FPGA I/O buffers. The use of several termination schemes permits an easy interface for each buffer type. Table 7. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13) SMA Designation Name LFE2M35E Signal 672-BGA Termination Description Termination Resistor(s) J37 LVDS_INP0 PR37A N23 100-ohm Differential R130 J39 LVDS_INN0 PR37B M21 LVDS_INP1 PR41A P24 100-ohm Differential R132 100-ohm Differential R134 100-ohm Differential R136 100-ohm Differential R131 100-ohm Differential R133 100-ohm Differential R135 LVDS_INN1 PR41B P23 J45 LVDS_INP2 PR51A T24 J47 LVDS_INN2 PR51B U24 J49* LVDS_INP3 PR57A V24 J51* LVDS_INN3 PR57B W24 J38 LVDS_OUTP0 PR50A T23 J40 LVDS_OUTN0 PR50B T22 J42 LVDS_OUTP1 PR53A V26 J44 LVDS_OUTN1 PR53B V25 J46 LVDS_OUTP2 PR55A W26 J48 LVDS_OUTN2 PR55B W25 10 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor Table 7. FPGA I/O Test SMA Connectors (see Appendix A, Figure 13) (Continued) SMA Designation Name LFE2M35E Signal 672-BGA Termination Description Termination Resistor(s) J50 LVDS_OUTP3 J52 LVDS_OUTN3 PR59A Y26 100-ohm Differential R137 PR59A AA26 Logic Analyzer Probe (see Appendix A, Figure 10, LA1) An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to utilize for test points. This connection provides 24 general I/O signals to be observed on a Logic Analyzer probe using Mictor connections such as the Agilent 5346A. Table 8. Test Pad Array BGA Reference Mictor Pin BGA Mictor Pin BGA 5 AA20 6 E24 7 V17 8 P26 9 W20 10 P25 11 AC25 12 U21 13 AC23 14 U19 15 AD26 16 V21 17 AB21 18 not used 19 AC22 20 not used 21 Y18 22 not used 23 AA19 24 not used 25 W17 26 not used 27 AC21 28 not used 29 Y17 30 not used 31 AA18 32 not used 33 AA17 34 not used 35 AB6 36 not used 37 E23 38 not used High Speed Test Point (see Appendix A, Figure 13) DP1 General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance probe to measure the performance of a coupled- differential output buffer pair. DDR2 Memory (see Appendix A, Figure 14) U18 The LatticeECP2M Evaluation Board is equipped to an 84-ball BGA DDR2 SDRAM memory device such as a Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation board includes termination of address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeECP2M device 11 LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Lattice Semiconductor Ordering Information Description Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP) LatticeECP2M35 PCI Express x4 Evaluation Board Revision B (Non-RoHS, Obsolete) LFE2M35E-P4-EV 10 LatticeECP2M50 PCI Express x4 Evaluation Board Revision B (Non-RoHS, Obsolete) LFE2M50E-P4-EV 10 LatticeECP2M50 PCI Express x4 Evaluation Board Revision B (RoHS Compliant) LFE2M50E-P4-EVN Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary April 2008 01.0 Initial release. May 2008 01.1 Various minor updates to clarify text. January 2009 01.2 Updated ordering information. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 13 A B C D 5 5 4 ECP2M-672fpBGA x4 PCI Express Platform Evaluation Board 4 3 PCIE X4 EDGE CONNECTION SERDES TEST SMAs 3 LEDs 2 16 Segment Display DIP SWITCHES 2 D a te : S iz e C Title Monday, March 17, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t Cover Page 1 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Appendix A. Schematics Figure 5. Cover Page A B C D 1 1 1 1 1 R14 0R-0805SMT TP11 TP9 TP7 TP5 TP3 1 R30 0R-0805SMT C16 10UF-16V_TANTBSMT 3_3VIN C3 10UF-16V_TANTBSMT 3_3VIN TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT 5 1 TP12 1 TP10 1 TP8 1 TP6 1 TP4 1 TP2 TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT TESTPOINT 2 4 5 C17 C9 2 4 5 OUTPUT R17 124R-0603SMT C10 1_5V C18 1_8V 22UF-16V_TANTBSMT 124R-0603SMT R33 1 3 5A Fast-Blo SMT Socketed Fuse F6 F1228CT-ND OUTPUT AMS1503CT 3 1 22UF-16V_TANTBSMT SENSE ADJUST_GND VCONTROL VPOWER U8 AMS1503CT VCC_CORE C11 C19 1_8V 1.5V 1_5V 1.8V 4 8 12_0V Q3 2N2222/SOT23 ILIM IN CNTL GND OUT SENSE EN GND VIN SC1592 TAB U20 1 2 U5 1 10K-0603SMT R10 LED-SMT1206_GREEN D6 1_8V 1. 8V R4 470R-1206SMT 12_0V 1 2 3 4 5 6 7 PTH12060W Q4 2N2222/SOT23 SENSE VOUT R233 10K-0603SMT 1_2V 3_3VIN R232 100R-0805SMT GND R25 1_8K-0603SMT R234 1.2V Analog 330UF-FKSMT C5 + 100R-0603SMT R235 3 3_3V R6 100R-0603SMT 2. 5V D1 LED-SMT1206_GREEN 2_5V G R7 150R-0603SMT 3.3V D2 LED-SMT1206_GREEN 3_3V F4 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 330UF-FKSMT C15 + 1_2V C6 10UF-16V_TANTBSMT 5A Fast-Blo SMT Socketed Fuse R28 0R-0603SMT 3_3VIN 3.3V F1228CT-ND F3 1_2V C14 10UF-16V_TANTBSMT 49_9R-0603SMT VCCA_SC 0R-0603SMT C4 10UF-16V_TANTBSMT R15 5 6 R12 100K-0603SMT 3_3VIN 1 10K-0603SMT R11 LED-SMT1206_GREEN D7 1.2V R5 470R-1206SMT 12_0V 3 G POWER RAIL GOOD INDICATORS R18 OPEN-0805SMT 1 10K-0603SMT R9 LED-SMT1206_GREEN D5 1_5V 1.5V R3 470R-1206SMT 12_0V G Q2 2N2222/SOT23 F2 F1228CT-ND 5A Fast-Blo SMT Socketed Fuse 1 10K-0603SMT R8 LED-SMT1206_GREEN D4 V C C _C O R E SENSE ADJUST_GND VCONTROL VPOWER U4 Q1 2N2222/SOT23 470R-1206SMT R2 12_0V G 4 G 3 2 TP1 100NF-0603SMT 100NF-0603SMT INHIBIT# 3 G 3 GND Pads Distributed around the board R20 ADJUST 4 3 R36 10 MUP 9 MDWN 8 TRACK GND 7 3 2 100NF-0603SMT 2 27R-0603SMT 56R-0603SMT R32 OPEN-0805SMT R19 1 2 U7 GND VIN GND VIN C1 PTH12060W 1 2 U3 LED-SMT1206_GREEN 3_3VIN 12_0V 2 D3 12_0V R1 470R-1206SMT 12VIN GOOD OPEN-0805SMT 2 12_0V C2 2 1 PTH03010W + SENSE VOUT R38 4_3K-0603SMT 5 6 D a te : S iz e C Title 0R-0603SMT R29 R16 2_5V 2.5V C8 10UF-16V_TANTBSMT Friday, February 22, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t 1 12_0V C12 10UF-16V_TANTBSMT 330UF-FKSMT C7 + 2 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 330UF-FKSMT C13 + 5A Fast-Blo SMT Socketed Fuse 0R-0603SMT VCC_CORE J1 10A Fast-Blo SMT Socketed Fuse F1251CT-ND F1 DC/DC Conversion F1228CT-ND F5 R27 100K-0603SMT R23 1M-0603SMT 5 6 R13 100K-0603SMT 100UF-FKSMT 1 Male Power Jack 2.1mm 22HP037 3 POWER INPUT 12_0V VOUT SENSE GND +12VDC Terminal Block/ED1202DS TB1 FPGA VCC_CORE 470UF-FKSMT + 12_0V INHIBIT# 3 2 G ADJUST 3_3_TRIM 10 MUP INHIBIT# 2 5 100NF-0603SMT 10 MUP 9 MDWN 9 MDWN 3 8 TRACK 4 2_5_TRIM 8 TRACK ADJUST 4 CORE_TRIM GND 7 GND 14 7 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 6. DC/DC Conversion A B C D C35 C36 C37 C46 5.6nF 0402 C121 T8 1 1 JUMPER1 C122 JUMPER1 J101 C71 C72 C73 C74 VCC_PLL G19 J17 H7 K6 R8 P7 V18 P20 J99 HEADER 3 VCC Core U1I 1_5V J98 HEADER 3 C123 C124 ecp2m-672fpbga 2 2 1_5V 1_2V C125 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 1_2V L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 C126 PP6 VCC_CORE + C419 + C417 22UF-16V_TANTBSMT C127 C420 VDDOB C418 VDDIB 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C70 ecp2m-672fpbga PLL RLM0_PLLCAP LLM0_PLLCAP J100 V19 RUM0_VCCPLL RUM1_VCCPLL LUM0_VCCPLL LUM1_VCCPLL LLM0_VCCPLL LLM2_VCCPLL RLM0_VCCPLL RLM2_VCCPLL + C38 C128 C20 1UF-16V-0805SMT C129 PP1 C133 C134 C135 C136 C137 C138 C139 C140 C141 5 4 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C132 VCC_CORE 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C120 VCC_CORE C47 5.6nF 0402 U1G 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C28 VCC_PLL 1 2 C41 C31 C42 C49 C50 C60 C64 C108 100NF-0603SMT C100 C88 C114 100NF-0603SMT C32 C51 C65 C24 C25 C26 C43 C33 C44 C34 C52 C53 C54 C55 C66 C67 C68 C61 10NF-0603SMT C115 10NF-0603SMT 100NF-0603SMT C116 100NF-0603SMT 10NF-0603SMT C117 L_VDDRX 10NF-0603SMT C94 VDDIB VDDIB AE25 AD23 AD15 AE13 B25 C23 C15 B13 A22 C20 C18 A16 AF16 AD20 AD18 AF22 AE19 B19 C27 C45 C56 C69 C92 C96 ecp2m-672fpbga SERDES Supplies L_VCCIB0 L_VCCIB1 L_VCCIB2 L_VCCIB3 U_VCCIB0 U_VCCIB1 U_VCCIB2 U_VCCIB3 U_VCCOB0 U_VCCOB1 U_VCCOB2 U_VCCOB3 L_VCCOB3 L_VCCOB1 L_VCCOB2 L_VCCOB0 L_VCCAUX33 U_VCCAUX33 U1H 3 100NF-0603SMT C118 100NF-0603SMT C110 100NF-0603SMT C102 10NF-0603SMT C119 10NF-0603SMT C111 10NF-0603SMT C103 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT C90 VDDOB 10NF-0603SMT C101 L_VDDP C109 C107 10NF-0603SMT C99 + C87 C106 U_VDDRX C40 PP14 PP13 PP12 L_VDDP 2 C58 C30 C428 C426 PP2 PP3 1UF-16V-0805SMT C76 U1J VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 C78 ecp2m-672fpbga C77 B7 B12 F11 J13 K12 D18 F16 J14 K15 G25 L21 M17 M25 N18 P18 R17 R25 T21 Y25 AC18 AA16 U15 V14 AA11 AE7 U12 V13 AE12 P9 R10 R2 T6 Y2 G2 L6 M10 M2 N9 C429 + FB11 BLM41PG600SN1 U_VDDRX C427 + FB10 BLM41PG600SN1 U_VDDTX C425 + FB9 BLM41PG600SN1 U_VDDP 1_2V 3_3V FB1 FB2 D a te : S iz e C + C130 L_VDDRX + C112 L_VDDTX C113 C131 C105 C62 3_3V 10NF-0603SMT C81 22UF-16V_TANTBSMT Thursday, February 21, 2008 PP4 PP8 PP7 PP5 10NF-0603SMT C82 1 S he e t 3 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP2M PCI EXPRESS Card P roje c t + C59 1 10NF-0603SMT C80 U17 AC24 AA7 J11 J12 J15 J16 L18 L9 M18 M9 R18 R9 T18 T9 V11 V12 V15 V16 Power Supplies BLM41PG600SN1 FB3 BLM41PG600SN1 + C104 L_VDDP 10NF-0603SMT C79 BLM41PG600SN1 Title VCCIO8 VCCIO8 VCCJ VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX Power Supplies 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C75 10NF-0603SMT C97 22UF-16V_TANTBSMT C424 + C57 1_8V + C29 2_5V 2 100NF-0603SMT C93 U_VDDP U_VDDTX L_VDDTX U_VDDRX L_VDDRX 10NF-0603SMT C95 AD25 AD24 AD13 AD14 C25 C24 C14 C13 AD16 AD17 AD21 AD22 C22 C21 C17 C16 C19 AD19 100NF-0603SMT C91 VDDOB L_VCCRX0 L_VCCRX1 L_VCCRX3 L_VCCRX2 U_VCCRX0 U_VCCRX1 U_VCCRX2 U_VCCRX3 L_VCCTX3 L_VCCTX2 L_VCCTX1 L_VCCTX0 U_VCCTX0 U_VCCTX1 U_VCCTX2 U_VCCTX3 U_VCCP L_VCCP 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT C63 L_VDDTX 100NF-0603SMT C23 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C48 U_VDDTX 100NF-0603SMT C98 U_VDDP C22 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 3_3V 1_8V C21 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C39 3 1 2 FB8 BLM41PG600SN1 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1 2 3 1 2 3 1UF-16V-0805SMT 1UF-16V-0805SMT 1_2V 22UF-16V_TANTBSMT 2_5V 100NF-0603SMT 1 1UF-16V-0805SMT 2 4 1UF-16V-0805SMT C89 1 2 5 1 2 1 2 1 2 1 2 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1UF-16V-0805SMT 1 2 1 2 1 15 2 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 7. Power Supplies A B C143 3_3V 10NF-0603SMT C 100NF-0603SMT C144 [10] GSRN 3_3V 5 FPGA_CSSPI0N SFLASH_Q_1 1 2 3 4 3_3V CK D DU8 DU7 DU6 DU5 VSS W# 1 3 3_3V HEADER 2X2 2 4 8 7 6 5 16 15 14 13 12 11 10 9 J11 M25P80-FLASH S# VCC Q HOLD# W# CLK DI GND U15 FLASH1 M25P64-FLASH HOLD# VCC DU1 DU2 DU3 DU4 S# Q U12 SPI0_Q FPGA_CCLK FPGA_SISPI FPGA_CCLK LED-SMT1206_RED D10 680R-0603SMT R53 Slave Serial FLASH0 SFLASH_Q_0 SFLASH_Q_1 FLASH_DIS FPGA_CSSPI0N SFLASH_Q_0 3_3V LED-SMT1206_RED D9 1 2 3 4 5 6 7 8 ispJTAG 680R-0603SMT R51 Slave Parallel 1(OFF) X X 1(OFF) 1(OFF) X 0(ON) SPI Flash 0(ON) 1(OFF) 1(OFF) SPIm 0(ON) 0(ON) 0(ON) 3_3V Q5 2N2222/SOT23 D11 CFG1 CFG0 R47 10K-0603SMT R48 10K-0603SMT 1 INITN R55 10K-0603SMT DONE JUMPER1 J13 JUMPER1 J12 4 2 2 PROGRAMN GSRN 0R-0603SMT R64 PROGRAMN FPGA RESETN/GSRN 1 DONE indicator will light when configuration is successfully completed LED-SMT1206_RED R D8 [5] PCIE_PERSTN 1 6 5 4 1 2 3 INITN indicator will light if an error occurs during configuration programming CFG2 ON R45 10K-0603SMT R52 680R-0603SMT 3_3V R54 1(OFF) R56 10K-0603SMT Y GSRN Y PROGRAMN 220R-0603SMT G 3 2 R61 10K-0603SMT 0(ON) LED-SMT1206_GREEN 3_3V 3 3 6 3 2Y 1Y 2 4 Momentary Switch B3F-1150 1 SW3 2 4 Momentary Switch B3F-1150 1 SW2 R62 1 5 4 2 3 1 SN74LVC125A/SO14 2A 2OE_N 1A 1OE_N U14A 3_3V HEADER 2 J2 C145 Configuration Mode R60 10K-0603SMT 100NF-0603SMT CFG0 4_7K-0603SMT GND 1 2 OUT1 OUT2 MAX6817 IN2 IN1 U11 4 6 SPIFASTN R44 5 VCC CFG1 R65 GND 2 R66 100R-0603SMT 3 11 8 4Y 3Y 3_3V 10K-0603SMT SPI0_Q R58 4_7K-0603SMT CFG2 100R-0603SMT R59 4_7K-0603SMT SW1 SW DIP-3 CTS 194-3MST 12 13 9 10 SN74LVC125A/SO14 4A 4OE_N 3A 3OE_N U14B FPGA_D0 FPGA_D7 FPGA_D7 FPGA_D0 HEADER 3 J5 HEADER 3 J60 FPGA_SISPI FPGA_CSSPI1N FPGA_CSSPI0N FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 CSN CS1N WRITEN 1 2 3 1 2 3 ecp2m-672fpbga PR62A/BUSY PR62B/DOUT/CSON PR63A/DI PR63B/D7 PR64A/D6 PR64B/D5 PR65A/D4 PR65B/D3 PR66A/D2 PR66B/D1 PR67A/D0 PR67B/CSN PR68A/CS1N PR68B/WRITEN FPGA_D[0..7] FPGA_CSSPI1N FPGA_CSSPI0N Y24 W23 V20 W21 AA24 Y23 W18 W22 Y20 W19 Y22 AB26 Y21 Y19 2 DONE FPGA_D7 FPGA_D6 FPGA_D5 FPGA_D4 FPGA_D3 FPGA_D2 FPGA_D1 FPGA_D0 CSN CS1N 3_3V FPGA_CCLK FPGA_SISPI HEADER 3 J3 CONFIG CFG2 CFG1 CFG0 PROGRAMN DONE INITN CCLK TCK TMS TDO TDI XRES 1 2 3 CSN 4 6 OUT Y2 OUT Y1 6 4 TMS_BUF TCK_BUF OUT Y2 OUT Y1 3_3V 1 2 3 U9 IN A2 IN A1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 3 3_3V J6 HEADER 17X2 NC7WZ16-MACO6A/Fairchild TinyLogic R63 220R-0603SMT D12 LED-SMT1206_GREEN This LED indicates activity on TDI. TDI_BUF TCK_BUF TMS_BUF LOCAL_TDO TDI_BUF CFG2 CFG1 CFG0 R49 10K-0603SMT J4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 3_3V AA21 AA22 AB23 AC26 AB25 AA23 AB24 AC3 AC4 V8 W8 H19 NC7WZ16-MACO6A/Fairchild TinyLogic R 5 U1B IN A2 IN A1 3_3V FPGA_D6 3 1 3 1 D a te : S iz e C 3_3V LOCAL_TMS LOCAL_TCK DONE INITN LOCAL_TDO LOCAL_TDI 4.7K 4.7K INITN GND DONE TCK TMS NC 4.7K Tuesday, February 05, 2008 4.7K EXBV8V472JV 7 1 3_3V 100NF-0603SMT 1 S he e t 4 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 ECP2M PCI EXPRESS Card P roje c t VCC ispEN_N TDI TDO HEADER 10 2 3 4 5 6 8 9 10 J8 FROM ISPVM CABLE Configuration/Testpoints WRITEN CFG0 CFG1 CFG2 sysCONFIG Connector 3_3V INITN PROGRAMN CS1N R50 10K-0603SMT 10K-0603SMT R46 FPGA_CCLK 1 PROGRAMN DONE INITN R43 4_7K-0603SMT R40 R41 R42 10K-0603SMT 10K-0603SMT 10K-0603SMT Title U13 C147 CONFIG CFG Switches 100NF-0603SMT VCC GND 2 5 VCC GND 2 D 2 C142 100NF-0603SMT 3 RN1B 4 RN1C 4_7K-0603SMT R57 7 RN1D 5 14 VCC 1 RN1A 8 LOCAL_TDO 2 7 LOCAL_TCK 3 6 LOCAL_TMS 4 5 LOCAL_TDI 16 C146 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 8. Configuration/Testpoints A B C D C421 R229 1_6R-0603SMT C422 100NF-0603SMT 3_3V + 10UF-16V_TANTBSMT 2 1 C423 NC 5 DIS# 100NF-0603SMT 6 Q_N Q 5 4 Y3 CW-P423-312.5MHZ VCC GND 3 3_3V 82R-0603SMT R227 [4,10] PCIE_PERSTN PCIE_3V3 12_0V PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST# GND REFCLK+ REFCLKGND PERp0 PERn0 GND RSVD_A19 GND PERp1 PERn1 GND GND PERp2 PERn2 GND GND PERp3 PERn3 GND RSVD_A32 CN1 2 4 +12V +12V RSVD_B3 GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE# RSVD_B12 GND PETp0 PETn0 GND PRSNT3# GND PETp1 PETn1 GND GND PETp2 PETn2 GND GND PETp3 PETn3 GND RSVD_B30 PRSNT4# GND x1 x4 PCI Express x4 Edge Finger Conn. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 0R-0603SMT 0R-0603SMT B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 PRSNT SELECT HEADER 2X2 1 3 J16 SMA_REFCLKN R69 R70 51R-0603SMT R67 R68 51R-0603SMT 1 PETp3 PETn3 PETp2 PETn2 PETp1 PETn1 x4 1 PCIE_WAKEN PETp0 PETn0 x1 2 [6] PCIE_SMCLK [6] PCIE_SMDAT [6] JUMPER1 J97 PCIE_3V3 X4 PCIe Board Fingers 1 0R-0603SMT 0R-0603SMT SMA_REFCLKP R80 R79 4 TP13 TESTPOINT U_HDINP3 U_HDINN3 U_HDINP2 U_HDINN2 U_HDINP1 U_HDINN1 U_HDINP0 U_HDINN0 U_REFCLKP U_REFCLKN L_HDINP3 L_HDINN3 L_HDINP2 L_HDINN2 L_HDINP1 L_HDINN1 L_HDINP0 L_HDINN0 L_REFCLKP L_REFCLKN 4 B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM) PERp3 PERn3 PERp2 PERn2 PERp1 PERn1 PERp0 PERn0 U_REFCLKP U_REFCLKN J15 Rosenberger 32K153-400E3 1 A_OSC_N A_OSC_P R231 130R-0603SMT 3_3V J14 Rosenberger 32K153-400E3 R226 82R-0603SMT R230 130R-0603SMT 2 2 5 A14 B14 A15 B15 A23 B23 A24 B24 D19 E19 AF14 AE14 AF15 AE15 AF23 AE23 AF24 AE24 AC19 AB19 3 L_REFCLKP U_REFCLKP ecp2m-672fpbga U_HDINP3 U_HDINN3 U_HDINP2 U_HDINN2 U_HDINP1 U_HDINN1 U_HDINP0 U_HDINN0 U_REFCLKP U_REFCLKN L_HDINP3 L_HDINN3 L_HDINP2 L_HDINN2 L_HDINP1 L_HDINN1 L_HDINP0 L_HDINN0 L_REFCLKP L_REFCLKN U1A 3 R216 R215 100R-0603SMT OPEN-0603SMT Place near U1 A17 B17 A18 B18 A20 B20 A21 B21 AF17 AE17 AF18 AE18 AF20 AE20 AF21 AE21 L_REFCLKN U_REFCLKN SERDES U_HDOUTP3 U_HDOUTN3 U_HDOUTP2 U_HDOUTN2 U_HDOUTP1 U_HDOUTN1 U_HDOUTP0 U_HDOUTN0 L_HDOUTP3 L_HDOUTN3 L_HDOUTP2 L_HDOUTN2 L_HDOUTP1 L_HDOUTN1 L_HDOUTP0 L_HDOUTN0 J23 Rosenberger 32K153-400E3 J20 Rosenberger 32K153-400E3 J32 Rosenberger 32K153-400E3 J29 Rosenberger 32K153-400E3 J26 Rosenberger 32K153-400E3 J24 Rosenberger 32K153-400E3 J21 Rosenberger 32K153-400E3 J18 Rosenberger 32K153-400E3 U_HDOUTP3 U_HDOUTN3 U_HDOUTP2 U_HDOUTN2 U_HDOUTP1 U_HDOUTN1 U_HDOUTP0 U_HDOUTN0 L_HDOUTP3 L_HDOUTN3 L_HDOUTP2 L_HDOUTN2 L_HDOUTP1 L_HDOUTN1 L_HDOUTP0 L_HDOUTN0 2 2 2 2 2 2 2 2 2 2 100NFX5R-0402SMT C156 C157 PETp1 U_HDOUTN2 50 C160 C162 C163 C161 C159 J25 Rosenberger 32K153-400E3 J27 Rosenberger 32K153-400E3 J30 Rosenberger 32K153-400E3 J33 Rosenberger 32K153-400E3 J28 Rosenberger 32K153-400E3 J31 Rosenberger 32K153-400E3 L_HDINP1 L_HDINN1 L_HDINP2 L_HDINN2 L_HDINP3 L_HDINN3 1 1 1 1 1 1 D a te : S iz e C PERp3 PERn2 L_HDOUTN0 L_HDOUTP1 L_HDOUTN1 L_HDOUTP2 L_HDOUTN2 L_HDOUTP3 L_HDOUTN3 1 1 1 1 1 1 1 Friday, February 22, 2008 1 S he e t 5 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 L_HDOUTP0 PERn3 ECP2M PCI EXPRESS Card P roje c t PERn1 PERp1 PERp2 1 SERDES J22 Rosenberger 32K153-400E3 L_HDINN0 1 Title J19 Rosenberger 32K153-400E3 3G SMAs PCIe Terminations 100NFX5R-0402SMT 100NFX5R-0402SMT 100NFX5R-0402SMT L_HDINP0 U_HDOUTN3 C158 100NFX5R-0402SMT 100NFX5R-0402SMT 1 50 U_HDOUTP3 U_HDOUTP2 50 U_HDOUTN1 50 50 100NFX5R-0402SMT PERn0 PERp0 U_HDOUTP1 100NFX5R-0402SMT U_HDOUTP0 U_HDOUTN0 50 50 50 PETp3 PETn2 PETn3 U_HDINP3 U_HDINN2 U_HDINN3 50 50 50 PETp2 U_HDINP2 50 PETn1 PETn0 U_HDINN1 U_HDINP1 50 PETp0 U_HDINP0 U_HDINN0 50 50 1 50 2 2 2 2 2 2 2 17 2 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 9. SERDES A B SP5 SP7 SP9 1_8V SP11 R84 1K-0603SMT SP8 SP10 SP12 5 R83 OPEN-0603SMT 1K_ADJ/SMT3MM R82 SP6 C166 10NF-0603SMT C 1 1 1 1 1 1 1 1 1 1 1 1 R81 1K-0603SMT SP4 [7] DDR2_DQS1 [7] DDR2_DQS1# [7] DDR2_DQS0 [7] DDR2_DQS0# [7] DDR2_DQ[0:15] DDR_VREF1 DDR2_DQ[0:15] RN12 1 2 3 4 RN13 1 2 3 4 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 RN14 1 2 3 4 RN11 1 2 3 4 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQS1 DDR2_DQS1# DDR2_DQS0 DDR2_DQS0# RN10 1 2 3 4 33 33 33 33 33 4 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 741X083 8 7 6 5 Bank5 DQS1 DQS1# DQS0 DQS0# DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 ecp2m-672fpbga All these 741X083/33-ohm devices should be placed near the FPGA. ODT0 CS0# CAS# RAS# A4 A7 BA0 A11 A5 BA1 A1 A6 A3 A2 A0 A9 A12 DQ8 DQ9 DQ15 DQ14 DQ12 DQ13 DQ10 DQ11 DQS1 DQS1# DM1 A8 Bank4 Bottom PB40A/PCLKT4_0 PB40B/PCLKC4_0 PB41B/VREF1_4 PB42A PB42B PB48A PB49A PB49B PB50B PB51A PB52A PB52B PB54A PB54B PB57A PB58A PB59B PB60A PB61A PB61B PB63A PB65A PB65B PB68B PB69A PB69B PB70B PB71A PB71B PB72B PB73A PB73B DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 AC13 Y14 AC14 AB14 AA14 AC15 AB15 AC16 AB16 AA15 Y15 AC17 W15 AB17 AB20 AC20 W16 AA17 AA18 Y17 AC21 W17 AA19 Y18 AC22 AB21 AD26 AC23 AC25 W20 V17 AA20 [8] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] C176 CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 C177 C178 FPGA_VTT R1=50 Ohm R1 C179 R1 C180 RP1 A1 B1 C1 D1 E1 F1 G1 H1 J1 A1 B1 C1 D1 E1 F1 G1 H1 J1 K K# CS0# BA0 BA1 WE# RAS# CAS# ODT0 A12 DM0 DM1 CKE0# A8 A9 A10 A11 A4 A5 A6 A7 A0 A1 A2 A3 FPGA_VTT C181 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 3 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C175 A3 B3 C3 D3 E3 F3 G3 H3 J3 FPGA_VTT This RT140287/50-ohm pack should be placed near the FPGA. OSC_IN_1 TestArray15 TestArray14 TestArray13 TestArray12 TestArray11 TestArray10 TestArray9 TestArray8 TestArray7 TestArray6 TestArray5 TestArray4 TestArray3 TestArray2 TestArray1 PCIE_SMCLK [5] PCIE_SMDAT [5] PCIE_WAKEN [5] J2 J2 SP3 H2 H2 DM0 WE# DQS0 DQS0# DQ0 DQ1 DQ3 DQ7 DQ6 DQ4 DQ2 DQ5 CKE0# A10 G2 G2 D F2 F2 741X083 741X083 741X083 741X083 741X083 741X083 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RN3 1 2 3 4 22 22 22 22 22 22 DDR2_A12 DDR2_DM0 DDR2_DM1 DDR2_CKE0# RN6 8 7 6 5 RN9 8 7 6 5 RN8 8 7 6 5 1_8V 2 C168 2 5 4 DDR2_A[0:12] + VDDQ VREF SD U16 1_8V DDR2_K [7] DDR2_K# [7] DDR2_CS0# [7] DDR2_BA0 [7] DDR2_BA1 [7] DDR2_WE# [7] DDR2_RAS# [7] DDR2_CAS# [7] DDR2_ODT0 [7] DDR2_DM0 [7] DDR2_DM1 [7] DDR2_CKE0 [7] LP2996-SO8 C170 100NF-0603SMT 100NF-0603SMT C167 DDR_VREF1 R87 0R-0603SMT 2_5V DDR2_K DDR2_K# DDR2_CS0# DDR2_BA0 DDR2_BA1 DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_ODT0 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 RN5 8 7 6 5 RN7 8 7 6 5 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 741X083 DDR2_A0 8 DDR2_A1 7 DDR2_A2 6 DDR2_A3 5 RN4 8 7 6 5 22 All these 741X083/22-ohm devices should be placed near the FPGA. R217 51R-0603SMT DDR2_DQS1 SP2 C2 R218 51R-0603SMT DDR2_DQS1# SP1 E2 E2 R219 51R-0603SMT DDR2_DQS0 PB2A PB2B PB3A PB3B PB4A PB4B PB5A PB5B PB6A PB6B PB7A PB7B PB8A PB8B PB9A PB9B PB10A PB10B PB11A PB11B PB12A PB12B PB13A PB13B PB14A PB14B PB15A PB15B PB16A PB16B PB17A PB17B PB18A PB18B PB19A PB19B PB20A PB20B PB21A PB21B PB22A PB22B PB23A PB23B PB24A PB24B PB25A PB25B PB26A PB26B PB27A PB27B PB28A PB28B PB33A PB33B PB34A/VREF2_5 PB34B/VREF1_5 PB35A/PCLKT5_0 PB35B/PCLKC5_0 C169 U1C D2 D2 AB6 Y8 AD1 AD2 AC5 AA8 AC6 W9 AB7 Y9 AD3 AD4 AA9 W10 AC7 Y10 AE2 AD5 AE4 AE3 W11 AB8 AE5 AD6 AA10 AC8 W12 AC9 W13 AB10 AF3 AF4 AF5 AF6 Y12 AB11 AD7 AF7 AD8 AA12 AE8 AF8 AD9 AC10 AC11 AB12 AD10 Y13 AF9 AE9 AF10 AE10 AD11 AF11 AA13 AB13 W14 AC12 AF12 AD12 B2 B2 R220 51R-0603SMT DDR2_DQS0# K K# A2 A2 C2 2 47UF-16V_TANTBSMT [10] TestArray16 R85 4_7K-0603SMT 3 1UF-16V-0805SMT 4 6 7 VTT VSENSE AVIN PVIN GND 1 8 3 C172 [7] + 100UF-FKSMT C171 C173 1 D a te : S iz e C Title PP9 FPGA_VTT Friday, February 15, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t 6 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 DDR2 FPGA Controller C174 + R86 0R-0603SMT ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines 100NF-0603SMT 1UF-16V-0805SMT 5 1 18 2 DDR2_A[0:12] 10UF-16V_TANTBSMT A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 10. DDR2 FPGA Controller A B 5 R90 1K-0603SMT R92 FB4 C202 BLM41PG600SN1 C197 10NF-0603SMT 1_8V + C211 VDDL R93 OPEN-0603SMT C203 R94 1K-0603SMT C212 + C200 1_8V + C198 1_8V 1UF-16V-0805SMT C201 C199 4 PP11 1_8V R88 4_7K-0603SMT 2_5V C182 VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VREF VDDL VSSDL 100NF-0603SMT DDR2-SDRAM-84FBGA A1 E1 J9 M9 R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J2 J1 J7 VDDQ VREF SD U18B 5 4 1UF-16V-0805SMT U17 C183 2 6 7 C184 3 8 + DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK CK# CKE WE# RAS# CAS# ODT CS# BA0 BA1 NC_A2 NC_E2 NC_R8 RFU_L1 RFU_R3 RFU_R7 DDR2-SDRAM-84FBGA U18A C194 + 1_8V 100NF-0603SMT C185 LP2996-SO8 VTT VSENSE AVIN PVIN 47UF-16V_TANTBSMT C193 2_5V 100NF-0603SMT B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 F7 E8 B7 A8 F3 B3 J8 K8 K2 K3 K7 L7 K9 L8 L2 L3 A2 E2 R8 L1 R3 R7 C195 10UF-16V_TANTBSMT DDR2_K# 3 [6] [6] R236 DDR2_DQS0 [6] DDR2_DQS0# [6] DDR2_DQS1 [6] DDR2_DQS1# [6] DDR2_DM0 [6] DDR2_DM1 [6] DDR2_K [6] DDR2_K# [6] DDR2_CKE0 [6] DDR2_WE# [6] DDR2_RAS# [6] DDR2_CAS# [6] DDR2_ODT0 [6] DDR2_CS0# [6] DDR2_BA0 [6] DDR2_BA1 [6] DDR2_A[0:12] DDR2_DQ[0:15] 100R-0402SMT PP10 DDR_VTT Place Close to U18 DDR2_K DDR2_DQ15 DDR2_DQ14 DDR2_DQ13 DDR2_DQ12 DDR2_DQ11 DDR2_DQ10 DDR2_DQ9 DDR2_DQ8 DDR2_DQ7 DDR2_DQ6 DDR2_DQ5 DDR2_DQ4 DDR2_DQ3 DDR2_DQ2 DDR2_DQ1 DDR2_DQ0 DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_DQS0 DDR2_DQS0# DDR2_DQS1 DDR2_DQS1# DDR2_DM0 DDR2_DM1 DDR2_K DDR2_K# DDR2_CKE0# DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_ODT0 DDR2_CS0# DDR2_BA0 DDR2_BA1 C196 + R89 0R-0603SMT 1UF-16V-0805SMT 3 VTT C187 C188 C189 C190 C191 C192 C205 CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 DDR_VTT CTS-RT1402B7 A3 B3 C3 D3 E3 F3 G3 H3 J3 R1=50 Ohm C206 R1 R1 C207 R1=50 Ohm C208 R1 R1 C209 RP3 A1 B1 C1 D1 E1 F1 G1 H1 J1 RP2 A1 B1 C1 D1 E1 F1 G1 H1 J1 C210 A1 B1 C1 D1 E1 F1 G1 H1 J1 A1 B1 C1 D1 E1 F1 G1 H1 J1 DDR2_WE# DDR2_RAS# DDR2_CAS# DDR2_BA1 DDR2_BA0 DDR2_CS0# DDR2_ODT0 DDR2_CKE0# DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 X2 2 Termination at end of line VTT RESISTOR X1 DDR2 Device Pin 1 D a te : S iz e C Title Friday, February 15, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t DDR2 Device/Termination 7 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 U1 Pin X1 needs to be matched length for all traces 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C204 DDR_VTT A3 B3 C3 D3 E3 F3 G3 H3 J3 A3 B3 C3 D3 E3 F3 G3 H3 J3 DDR_VTT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 100NF-0603SMT 10NF-0603SMT 10NF-0603SMT 10NF-0603SMT C186 DDR_VTT 2 J2 4 G2 H2 1K_ADJ/SMT3MM 10NF-0603SMT J2 J2 F2 F2 R91 0R-0603SMT C213 C 1_8V 100NF-0603SMT 22UF-16V_TANTBSMT 22UF-16V_TANTBSMT 100NF-0603SMT H2 H2 E2 E2 D 1 2 G2 G2 D2 D2 GND 1 F2 F2 J2 C2 C2 100UF-FKSMT E2 E2 H2 B2 B2 B2 B2 1 2 D2 D2 G2 A2 A2 C2 A2 A2 C2 5 C214 19 1UF-16V-0805SMT 10NF-0603SMT DDR2_DQ[0:15] C215 DDR2_A[0:12] 100NF-0603SMT A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 11. DDR2 Device/Termination DDR2_A[0:12] 22UF-16V_TANTBSMT 1UF-16V-0805SMT 20 A B C C228 R98 + 10UF-16V_TANTBSMT C230 5 J35 Johnson 142-0711-201 1_6R-0603SMT C229 100NF-0603SMT 3_3V 100NF-0603SMT 2 1 14 R99 130R-0603SMT 51R-0603SMT R109 Q_N Q [6] OSC_IN_1 [10] OSC_IN_2 J36 Johnson 142-0711-201 C231 51R-0603SMT R110 4 R103 R102 0R-0603SMT 0R-0603SMT 1 2 3 4 3 4 GND N/C CY2304-1 REF FBK CLKA1 VDD CLKA2 CLKB2 GND CLKB1 U19 Y2 OUT Vcc 8 7 6 5 CTS-CB3LV-3C-100.00MHZ REFCLK_EXT_IN_N REFCLK_EXT_IN_P 4 100NF-0603SMT OSC_IN_1 OSC_IN_2 3_3V 1 82R-0603SMT OSC_N R104 82R-0603SMT OSC_P R107 R97 130R-0603SMT 3_3V 1 3_3V 8 Y1 110-93-314-41-001 VDD GND 7 D 2 5 2 1 OSC_IN_3 OSC_IN_4 RS_PCLK_CLKP 3_3V [9] [9] C233 3 10NF-0603SMT OSC_IN_3 [10] OSC_IN_4 [10] 100NF-0603SMT C232 RS_PCLK_CLKN LS_PCLK_CLKN [10] LS_PCLK_CLKP [10] 3 Place near to U1 R118 100R-0603SMT RS_PCLK_CLKP RS_PCLK_CLKN R119 100R-0603SMT LS_PCLK_CLKP LS_PCLK_CLKN 2 2 D a te : S iz e C Title Friday, February 15, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t Clocks 8 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 12. Clocks A B C 5 J51 Johnson 142-0711-201 J49 Johnson 142-0711-201 J47 Johnson 142-0711-201 J45 Johnson 142-0711-201 J43 Johnson 142-0711-201 J41 Johnson 142-0711-201 2 2 2 2 2 2 2 2 LVDS_INP_1 LVDS_INN_1 LVDS_INP_2 LVDS_INN_2 LVDS_INP_3 1 1 1 1 1 1 LVDS_INN_3 DQS PAIR LVDS_INN_0 R130 100R-0603SMT R132 100R-0603SMT R134 100R-0603SMT R136 100R-0603SMT 4 J52 Johnson 142-0711-201 J50 Johnson 142-0711-201 J48 Johnson 142-0711-201 J46 Johnson 142-0711-201 J44 Johnson 142-0711-201 J42 Johnson 142-0711-201 J40 Johnson 142-0711-201 2 2 2 2 LVDS_OUTN_2 LVDS_OUTP_3 1 1 3 LVDS_OUTP_2 1 DP1 R138 LVDS_PROBEP LVDS_PROBEN Place this resistor close to test point 100R-0603SMT 1 LVDS_OUTN_1 1 LVDS_OUTN_3 LVDS_OUTP_1 1 1 LVDS_OUTN_0 1 R131 100R-0603SMT R133 100R-0603SMT R135 100R-0603SMT R137 100R-0603SMT 2 2 2 2 1 2 3 [8] RS_PCLK_CLKP [8] RS_PCLK_CLKN Bank3 Bank2 ecp2m-672fpbga 2 Right PR9A/VREF1_2 PR9B/VREF2_2 PR11A*/RUM0_SPLLT_IN_A PR11B*/RUM0_SPLLC_IN_A PR37A*/PCLKT3_0 PR37B*/PCLKC3_0 PR12A/RUM0_SPLLT_FB_A PR12B/RUM0_SPLLC_FB_A PR38A/VREF1_3 PR13A* PR38B/VREF2_3 PR13B* PR39A* PR14A PR39B* PR14B PR40A PR15A* PR40B PR41A*/RLM2_SPLLT_IN_A PR15B* PR16A PR41B*/RLM2_SPLLC_IN_A PR16B PR42A/RLM2_SPLLT_FB_A PR17A* PR42B/RLM2_SPLLC_FB_A PR17B* PR44A* PR18A PR44B* PR18B PR45A PR19A* PR45B PR19B* PR46A* PR20A PR46B* PR20B PR47A PR21A* PR47B PR21B* PR48A* PR22A PR48B* PR49A PR22B PR23A* PR49B PR23B* PR50A* PR24A PR50B* PR51A PR24B PR25A* PR51B PR25B* PR53A* PR26A PR53B* PR26B PR54A PR28A*/RUM1_SPLLT_IN_A PR54B PR55A* PR28B*/RUM1_SPLLC_IN_A PR29A/RUM1_SPLLT_FB_A PR55B* PR29B/RUM1_SPLLC_FB_A PR56A PR57A*/RLM0_GPLLT_FB_A PR30A* PR30B* PR57B*/RLM0_GPLLC_FB_A PR31A PR58A/RLM0_GPLLT_IN_A PR31B PR58B/RLM0_GPLLC_IN_A PR59A*/RLM0_GDLLT_IN_A PR32A* PR32B* PR59B*/RLM0_GDLLC_IN_A PR60A/RLM0_GDLLT_FB_A PR33A PR33B PR60B/RLM0_GDLLC_FB_A PR34A* PR34B* PR35A/PCLKT2_0 PR35B/PCLKC2_0 RS_PCLK_CLKP RS_PCLK_CLKN J39 Johnson 142-0711-201 LOOP_P0 LOOP_N0 LOOP_P15 LOOP_N15 LOOP_P1 LOOP_N1 LOOP_P14 LOOP_N14 LOOP_P2 LOOP_N2 LOOP_P13 LOOP_N13 LOOP_P3 LOOP_N3 LOOP_P12 LOOP_N12 LOOP_P4 LOOP_N4 LOOP_P11 LOOP_N11 LOOP_P5 LOOP_N5 LOOP_P10 LOOP_N10 LOOP_P6 LOOP_N6 LOOP_P9 LOOP_N9 LOOP_P7 LOOP_N7 LOOP_P8 LOOP_N8 LOOP_P8 LOOP_N8 LOOP_P7 LOOP_N7 LOOP_P9 LOOP_N9 LOOP_P6 LOOP_N6 LOOP_P10 LOOP_N10 LOOP_P5 LOOP_N5 LOOP_P11 LOOP_N11 RS_PCLK_CLKP RS_PCLK_CLKN LOOP_P0 LOOP_N0 LVDS_OUTP_0 DQS PAIR LVDS_OUTP_3 LVDS_OUTN_3 LVDS_INP_3 LVDS_INN_3 LOOP_P12 LOOP_N12 LOOP_P4 LOOP_N4 LVDS_INP_1 LVDS_INN_1 LOOP_P3 LOOP_N3 LOOP_P13 LOOP_N13 LOOP_P2 LOOP_N2 LOOP_P14 LOOP_N14 LOOP_P1 LOOP_N1 LOOP_P15 LOOP_N15 LOOP_P0 LOOP_N0 LVDS_OUTP_0 LVDS_OUTN_0 LVDS_INP_2 LVDS_INN_2 LVDS_OUTP_1 LVDS_OUTN_1 LVDS_PROBEP LVDS_PROBEN LVDS_OUTP_2 LVDS_OUTN_2 LVDS_INP_0 LVDS_INN_0 TestArray22 TestArray23 TestArray21 TestArray19 TestArray20 Place these resistors close to U1 Device N23 M21 P26 P25 N22 N20 P22 N21 P24 P23 N19 R22 R24 R23 P19 P21 R26 T26 R20 R21 R19 T19 U26 U25 T23 T22 T24 U24 V26 V25 U22 U18 W26 W25 U21 V24 W24 U20 V23 Y26 AA26 U19 V21 LOOP_P1 LOOP_N1 1 LOOP_P2 LOOP_N2 J38 Johnson 142-0711-201 LOOP_P3 LOOP_N3 LVDS_INP_0 LOOP_P4 LOOP_N4 1 LOOP_P5 LOOP_N5 U1E LOOP_P6 D a te : S iz e C Title LOOP_N6 J37 Johnson 142-0711-201 E23 E24 F26 G26 F21 H20 F24 F23 F22 J18 G23 G24 K19 G22 H26 H25 H24 H23 J19 G21 J26 J25 J20 H22 K18 H21 J21 K20 J24 J23 K21 L19 K23 K24 K26 K25 M19 K22 L26 M26 M20 L23 L24 L22 N26 M23 M24 M22 N25 N24 LOOP_P7 [10] [10] [10] [10] [10] 1 LOOP_P14 LOOP_P15 Thursday, February 07, 2008 1 S he e t ECP2M PCI EXPRESS Card P roje c t 9 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 Differential I/O Loops LOOP_N7 [10] TestArray17 [10] TestArray18 LOOP_P8 LOOP_N8 Place these resistors close to SMA pair LOOP_P9 LOOP_N9 2 LOOP_P10 LOOP_N10 Place these resistors close to U1 Device 3 LOOP_P11 LOOP_N11 4 LOOP_P12 LOOP_N12 D 5 LOOP_P13 LOOP_N13 R140 100R-0603SMT R141 100R-0603SMT R142 100R-0603SMT R143 100R-0603SMT R144 100R-0603SMT R145 100R-0603SMT R146 100R-0603SMT R147 100R-0603SMT R148 100R-0603SMT R149 100R-0603SMT R150 100R-0603SMT R151 100R-0603SMT R152 100R-0603SMT R153 100R-0603SMT R154 100R-0603SMT R155 100R-0603SMT R156 100R-0603SMT LOOP_N14 21 LOOP_N15 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 13. Differential I/O Loops A B C 5 BGA H2 J3 G1 H3 J7 H5 G5 G6 F3 J8 E1 J9 E3 F5 D3 F6 C2 [6] TestArray1 [6] TestArray2 [6] TestArray3 [6] TestArray4 [6] TestArray5 [6] TestArray6 [6] TestArray7 [6] TestArray8 [6] TestArray9 [6] TestArray10 [6] TestArray11 [6] TestArray12 [6] TestArray13 [6] TestArray14 [6] TestArray15 [6] TestArray16 [9] TestArray17 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2_767004 5V SCL GND SDA CLK1 CLK 7 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 29 32 31 33 34 35 36 37 38 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 9 11 10 RN16H 8 RN16E 5 RN16F 6 RN16G 7 15 17 3 4 15 EXB2HV121JV 14 150R 13 12 11 10 9 RN17B 2 RN17C 3 RN17D 4 RN17E 5 RN17F 6 RN17G 7 RN17H 8 6 8 9 13 16 1 2 TestArray18 TestArray19 TestArray20 TestArray21 TestArray22 TestArray23 4 TestArray24 TestArray37 TestArray38 TestArray39 TestArray40 [4] GSRN [5] PCIE_PERSTN 16 RN17A 1 5 [9] [9] [9] [9] [9] [9] 13 12 RN16D 4 12 [8] OSC_IN_2 14 RN16C 3 11 7 R157 150R-0603SMT RN16A 1 16 EXB2HV121JV RN16B 2 150R 15 14 10 LTP-587HR/16-SEGMENT TestArray18 TestArray19 TestArray20 TestArray21 TestArray22 TestArray23 18 DP U T S R P N M K H G F E D C B LOGIC ANALYZER PROBE TestArray1 TestArray2 TestArray3 TestArray4 TestArray5 TestArray6 TestArray7 TestArray8 TestArray9 TestArray10 TestArray11 TestArray12 TestArray13 TestArray14 TestArray15 TestArray16 TestArray17 LA1 2_5V D14 C2 C1 F6 H9 D3 D2 F5 H8 E3 E2 J9 E4 E1 D1 J8 F4 F3 F1 G6 K9 G5 G4 H5 H6 J7 H4 H3 G3 G1 H1 J3 J4 H2 J2 K7 J6 K5 L5 K4 L4 K3 L3 J1 K2 K1 L1 K8 M5 M4 M3 L8 M6 M1 N1 N3 N2 N5 N4 M7 M8 Bank7 G7 G8 F8 J10 D4 C3 F7 G9 C4 B2 C5 B3 E7 H10 F9 G10 E6 D5 H11 D7 F10 C6 A3 A4 A5 A6 H12 D8 G12 C8 C7 D6 H13 D9 A7 B8 C9 G13 E10 F12 A8 B9 E8 C10 A9 H14 D10 F13 E11 G14 D11 B10 A10 H15 H18 H16 D12 A11 A12 F14 C11 G15 C12 3 ecp2m-672fpbga PT2A PT2B PT3A PT3B PT4A PT4B PT5A PT5B PT6A PT6B PT7A PT7B PT8A PT8B PT9A PT9B PT10A PT10B PT11A PT11B PT12A PT12B PT13A PT13B PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT21A PT21B PT22A PT22B PT23A PT23B PT24B PT29A PT29B PT30A PT30B PT31A PT31B PT32A PT32B PT33A PT33B PT34A PT34B PT35A PT35B PT36A/VREF1_0 PT36B/VREF2_0 PT37A/PCLKT0_0 PT37B/PCLKC0_0 U1F ecp2m-672fpbga PL2A* PL2B* PL3A PL3B PL4A* PL4B* PL5A PL5B PL6A* PL6B* PL7A PL7B PL8A* PL8B* PL9A/VREF2_7 PL9B/VREF1_7 PL11A*/LUM0_SPLLT_IN_A PL11B*/LUM0_SPLLC_IN_A PL12A/LUM0_SPLLT_FB_A PL12B/LUM0_SPLLC_FB_A PL13A* PL13B* PL14A PL14B PL16A PL16B PL17A* PL17B* PL19A* PL19B* PL20A PL20B PL21A* PL21B* PL22A PL22B PL23A* PL23B* PL24A PL24B PL25A* PL25B* PL26A PL26B PL28A*/LUM1_SPLLT_IN_A PL28B*/LUM1_SPLLC_IN_A PL29A/LUM1_SPLLT_FB_A PL29B/LUM1_SPLLC_FB_A PL30A* PL30B* PL31A PL31B PL32A* PL32B* PL33A PL33B PL34A* PL34B* PL35A/PCLKT7_0 PL35B/PCLKC7_0 U1D Bank0 A 3 Top PT38A/PCLKT1_0 PT38B/PCLKC1_0 PT39A/VREF1_1 PT39B/VREF2_1 PT40A PT40B PT41A PT41B PT42A PT42B PT43A PT43B PT44A PT44B PT45A PT45B PT46A PT46B Bank6 E13 H17 E12 F15 D13 D14 E14 G17 E15 G18 D15 E16 F18 F19 D16 F17 D17 E17 Left PL37A*/PCLKT6_0 PL37B*/PCLKC6_0 PL38A/VREF2_6 PL38B/VREF1_6 PL39A* PL39B* PL40A PL40B PL41A*/LLM2_SPLLT_IN_A PL41B*/LLM2_SPLLC_IN_A PL42A/LLM2_SPLLT_FB_A PL42B/LLM2_SPLLC_FB_A PL44A* PL44B* PL45A PL45B PL46A* PL46B* PL47A PL47B PL48A* PL48B* PL49A PL49B PL50A* PL50B* PL51A PL51B PL55A* PL55B* PL57A*/LLM0_GPLLT_IN_A PL57B*/LLM0_GPLLC_IN_A PL58A/LLM0_GPLLT_FB_A PL58B/LLM0_GPLLC_FB_A PL59A*/LLM0_GDLLT_IN_A PL59B*/LLM0_GDLLC_IN_A PL60A/LLM0_GDLLT_FB_A PL60B/LLM0_GDLLC_FB_A PL62A* PL62B* PL63A PL63B PL64A* PL64B* PL65A PL65B PL66A* PL66B* PL67A PL67B PL68A* PL68B* PL69A PL69B Bank1 4 P3 P2 P5 N6 P4 R3 P6 N7 P1 R1 N8 R5 T3 T4 P8 R6 T1 U1 R7 T5 U3 U4 U5 U6 U2 V1 W2 V2 V4 V3 W4 W3 W1 Y1 AA1 AB1 U7 V6 W5 Y4 U8 W6 Y3 AA3 V7 Y5 AB2 AA4 Y6 U9 AA5 AA6 Y7 V9 TestArray45 TestArray46 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 SWITCH8 RED1 YELLOW1 GREEN1 BLUE1 RED2 YELLOW2 GREEN2 BLUE2 TestArray41 TestArray42 TestArray43 TestArray44 7 7 2_5V 2 RN18C 470R-1206SMT R160 1 16 7 10 1 EXB2HV103JV 10K RN18G 470R-1206SMT R164 5 12 1 EXB2HV103JV 10K RN18E 470R-1206SMT R162 3 14 1 EXB2HV103JV 10K 1 SW6A SWITCH4 3 SW6B SWITCH3 12 4 SW6C SWITCH2 10 RN18A EXB2HV103JV 10K 1 R158 470R-1206SMT 1 SW5A SWITCH8 3 SW5B SWITCH7 12 4 SW5C SWITCH6 10 BLUE1 GREEN1 YELLOW1 6 SW6D SWITCH1 9 2 RED1 6 SW5D SWITCH5 9 OSC_IN_3 [8] OSC_IN_4 [8] LS_PCLK_CLKP [8] LS_PCLK_CLKN [8] 1 0 D SEGMENT A B C D E F G H K M N P R S T U DP 5 1 0 8 1 0 8 5 1 0 5 1 0 1 0 11 1 0 11 2 1 0 2 LED-SMT1206_RED D16 LED-SMT1206_GREEN D19 LED-SMT1206_BLUE D21 4 RED1 BLUE1 RED2 YELLOW2 470R 5 12 RN19E EXB2HV471JV 470R 6 11 RN19F EXB2HV471JV BLUE2 470R 8 9 RN19H EXB2HV471JV D a te : LED-SMT1206_RED D15 LED-SMT1206_YELLOW D18 LED-SMT1206_GREEN D20 LED-SMT1206_BLUE D22 Monday, March 17, 2008 1 S he e t 10 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 R173 680R-0603SMT R172 680R-0603SMT R171 680R-0603SMT R170 680R-0603SMT R169 680R-0603SMT R168 680R-0603SMT R167 680R-0603SMT R166 680R-0603SMT Q13 2N2222/SOT23 12_0V Q11 2N2222/SOT23 12_0V Q9 2N2222/SOT23 12_0V Q7 2N2222/SOT23 12_0V 1 ECP2M PCI EXPRESS Card P roje c t R165 470R-1206SMT RN18H FPGA TEST GREEN2 7 10 RN19G EXB2HV471JV S iz e C RN18F 470R-1206SMT R163 13 1 8 91 EXB2HV103JV 10K 4 13 RN19D EXB2HV471JV 470R RN18D 470R-1206SMT 6 11 1 EXB2HV103JV 10K YELLOW1 470R 15 1 R161 EXB2HV103JV 10K GREEN1 470R RN18B 470R-1206SMT R159 EXB2HV103JV 10K 2 470R 3 14 RN19C EXB2HV471JV BLUE2 GREEN2 YELLOW2 RED2 470R 2 15 RN19B EXB2HV471JV 1 16 RN19A EXB2HV471JV Q12 2N2222/SOT23 12_0V Q10 2N2222/SOT23 12_0V Title LED-SMT1206_YELLOW D17 Q8 2N2222/SOT23 12_0V Q6 2N2222/SOT23 12_0V R 3 2 Y 3 2 G 3 2 B 3 2 R 3 2 Y 3 2 G 3 2 B 3 22 2 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 14. FPGA Test 23 A B C D 5 5 VDDTX VDDRX VDDP VDDOB VDDIB VCC CORE C236 C237 C238 C239 C240 C241 C242 C246 C247 C258 C251 C261 C252 C278 C277 C276 C279 3_3V 1000PF-0402SMT C268 C287 MH2 M HOLE2 MH1 M HOLE2 M HOLE2 MH3 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C286 C284 C285 L_VDDTX U_VDDTX 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT L_VDDRX 22PF-0402SMT C267 L_VDDP U_VDDRX 1000PF-0402SMT C266 U_VDDP 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C250 VDDOB 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C245 VDDIB 4 VDDAUX33 22PF-0402SMT C269 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C235 VCC_CORE 4 ecp2m-672fpbga VSS U1K VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 A13 A19 A2 A25 AA2 AA25 AB18 AB22 AB5 AB9 AE1 AE11 AE16 AE22 AE26 AE6 AF13 AF19 AF2 AF25 B1 B11 B16 B22 B26 B6 E18 E22 E5 E9 F2 F25 G11 G16 J22 J5 K11 K13 K14 K16 L10 L11 L16 L17 L2 L20 L25 L7 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T2 T20 T25 T7 U11 U13 U14 U16 V22 V5 Y11 Y16 ALL CAPS PLACED UNDER BGA 3 VCCIO5 VCCIO7 VCCIO6 VCCIO4 VCCIO3 VCCIO2 VCCIO1 VCCAUX 1_8V 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V 2_5V C254 C243 C255 C244 C256 C257 C259 C249 C260 C263 C264 C265 C271 C272 C273 C274 C275 C281 C282 C283 C289 C290 C291 C292 C294 C295 C296 C297 C299 C300 C301 C302 2 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C298 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C293 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C288 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C280 D a te : S iz e C Title Monday, March 17, 2008 1 S he e t 11 of 11 R ev 2.0 1605 Valley Center Parkway Bethlehem, PA 18017 1 ECP2M PCI EXPRESS Card P roje c t VSS/Decoupling 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C270 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C262 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C248 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT 1000PF-0402SMT C253 2 A B C D Lattice Semiconductor LatticeECP2M PCI Express x4 Evaluation Board – Revision B User’s Guide Figure 15. VSS/Decoupling