DS7237C 05

®
RT7237C
2A, 18V, 800kHz Synchronous Step-Down Converter
General Description
Features
The RT7237C is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 2A
output current from a 4.5V to 18V input supply. The
RT7237C's current mode architecture and external
compensation allow the transient response to be
optimized over a wide input range and loads. Cycle-bycycle current limit provides protection against shorted
outputs, and soft-start eliminates input current surge during
start-up. The RT7237C also provides under voltage
protection and thermal shutdown protection. The low
current (<3μA) shutdown mode provides output
disconnection, enabling easy power management in
battery-powered systems. The RT7237C is available in
an SOP-8 (Exposed Pad) package.
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Marking Information
RT7237CH
GSPYMDNN
±1.5% High Accuracy Reference Voltage
4.5V to 18V Input Voltage Range
2A Output Current
Integrated N-MOSFET Switches
Current Mode Control
Fixed Frequency Operation : 800kHz
Output Adjustable from 0.8V to 12V
Stable with Low ESR Ceramic Output Capacitors
Up to 95% Efficiency
Programmable Soft-Start
Cycle-by-Cycle Over Current Limit
Input Under Voltage Lockout
Output Under Voltage Protection
Thermal Shutdown Protection
RoHS Compliant and Halogen Free
RT7253CHGSP : Product Number
Applications
YMDNN : Date Code
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Wireless AP/Router
Set-Top-Box
Industrial and Commercial Low Power Systems
LCD Monitors and TVs
Green Electronics/Appliances
Point of Load Regulation of High-Performance DSPs
Simplified Application Circuit
BOOT
VIN
VIN
CIN
RT7237C
CBOOT
L
SW
Chip Enable
VOUT
R1
EN
SS
COUT
FB
CSS
CC
GND
RC
R2
COMP
CP
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February 2015
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RT7237C
Ordering Information
Pin Configurations
RT7237C
(TOP VIEW)
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
G : Green (Halogen Free and Pb Free)
H : UVP Hiccup
8
BOOT
VIN
2
SW
GND
3
GND
EN
6
COMP
5
FB
9
4
SS
7
SOP-8 (Exposed Pad)
Note :
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
BOOT
Bootstrap for High Side Gate Driver. Connect a 0.1F or greater ceramic
capacitor from BOOT to SW pins.
2
VIN
Power Input. The Input Voltage range is from 4.5V to 18V. Must bypass with a
suitable large ceramic capacitor.
3
SW
Switch Node. Connect this pin to an external L-C filter.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
5
FB
Feedback Input. It is used to regulate the output of the converter to a set value
via an external resistive voltage divider.
6
COMP
Compensation Node. COMP is used to compensate the regulation control
loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
7
EN
Enable Input. A logic high enables the converter; a logic low forces the IC into
shutdown mode reducing the supply current to less than 3A.
8
SS
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
from SS to GND to set the soft-start period. A 0.1F capacitor sets the
soft-start period to 13.5ms.
4,
9 (Exposed Pad)
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RT7237C
Function Block Diagram
VIN
Internal
Regulator
Oscillator
Slope Comp
Shutdown V V
A
CC
Comparator
1.2V
Foldback
Control
+
-
5k
1.8V
-
RSENSE
0.4V
+
UV
Comparator
Lockout
Comparator
-
EN
Current Sense
Amplifier
+
+
VCC
VA
BOOT
S
+
R
Current
Comparator
Q
150m
Q
130m
SW
GND
6µA
0.8V
SS
FB
+
+EA
-
COMP
Operation
Internal Regulator
UV Comparator
Provide internal power for logic control and switch gate
drivers.
As FB voltage is lower than the UV voltage, it will activate
a UV protect scheme.
Shutdown Comparator
Error Amplifier
Activate internal regulator once EN input level is higher
than the target level. Force IC to enter shutdown mode
when the EN input level is lower than 0.4V.
The output voltage COMP of the error amplifier is adjusted
by comparing FB signal with the internal reference voltage
and SS signal.
Lockout Comparator
Current Sense Amplifier
Activate the current comparator, release lock-out logic,
and enable the switches as EN input level is higher than
lockout threshold voltage. Otherwise, the switches still
lock out.
RSENSE detects the peak current of the high side switch.
This signal is amplified by the current sense amplifier and
added with a slope compensation signal. Then, It controls
the switches by comparing this signal with the COMP
voltage.
Oscillator
The oscillator provides internal clock and controls the
converter's switching frequency.
Foldback Control
Dynamically adjust the internal clock. It provides a slower
frequency as a lower FB voltage.
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February 2015
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RT7237C
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------Switch Voltage, SW -----------------------------------------------------------------------------------------------VBOOT − VSW ---------------------------------------------------------------------------------------------------------Other Pins Voltage ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
−0.3V to 20V
−0.3V to (VIN + 0.3V)
−0.3V to 6V
−0.3V to 20V
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------
1.333W
Recommended Operating Conditions
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75°C/W
15°C/W
260°C
150°C
−65°C to 150°C
2kV
(Note 4)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 4.5V to 18V
Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Shutdown Supply Current
VEN = 0V
--
0.5
3
A
Supply Current
VEN = 3V, VFB = 0.9V
--
0.8
1.2
mA
0.788
0.8
0.812
V
--
940
--
A/V
Reference Voltage
VREF
4.5V VIN 18V
Error Amplifier
Transconductance
GEA
IC = ±10A
High Side Switch
On-Resistance
RDS(ON)1
--
150
--
m
Low Side Switch
On-Resistance
RDS(ON)2
--
130
--
m
High Side Switch Leakage
Current
VEN = 0V, VSW = 0V
--
0
10
A
Upper Switch Current Limit
Min. Duty Cycle, VBOOT VSW = 4.8V
--
4
--
A
COMP to Current Sense
Transconductance
GCS
--
3.7
--
A/V
Oscillation Frequency
fOSC1
--
800
--
kHz
Short Circuit Oscillation
Frequency
fOSC2
VFB = 0V
--
270
--
kHz
Maximum Duty Cycle
DMAX
VFB = 0.7V
--
84
--
%
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DS7237C-05
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RT7237C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ns
Minimum On-Time
tON
--
100
--
EN Input Threshold Logic-High
Voltage
Logic-Low
Input Under Voltage Lockout
Threshold
Input Under Voltage Lockout
Hysteresis
Soft-Start Current
VIH
2
--
18
VIL
--
--
0.4
3.8
4.2
4.5
V
--
320
--
mV
VUVLO
VIN Rising
VUVLO
V
ISS
VSS = 0V
--
6
--
A
Soft-Start Period
tSS
CSS = 0.1F
--
13.5
--
ms
Thermal Shutdown
TSD
--
150
--
C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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RT7237C
Typical Application Circuit
VIN
4.5V to 18V
CIN
10µF x 2
2 VIN
BOOT
RT7237C
SW 3
Chip Enable
4, 9 (Exposed Pad)
GND
CBOOT
L
0.1µF 4.7µH
R1
75k
7 EN
8 SS
CSS
0.1µF
1
FB 5
COMP
6
CC
3.3nF
RC
17k
VOUT
3.3V
COUT
22µF x 2
R2
24k
CP
Open
Table 1. Suggested Components Selection
VOUT (V) R1 (k)
R2 (k)
RC (k)
CC (nF)
L (H)
COUT (F)
8
27
3
40
3.3
6.8
22 x 2
5
62
11.8
25
3.3
6.8
22 x 2
3.3
75
24
17
3.3
4.7
22 x 2
2.5
25.5
12
13
3.3
4.7
22 x 2
1.5
10.5
12
7
3.3
3.6
22 x 2
1.2
12
24
6
3.3
2
22 x 2
1
3
12
5
3.3
2
22 x 2
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RT7237C
Typical Operating Characteristics
Reference Voltage vs. Input Voltage
Efficiency vs. Load Current
100
0.820
90
0.815
VIN = 12V
VIN = 17V
70
Reference Voltage (V)
Efficiency (%)
80
60
50
40
30
20
0.810
0.805
0.800
0.795
0.790
0.785
10
VIN = 4.5V to 17V
VOUT = 3.3V
0.780
0
0.001
0.01
0.1
1
4
10
6.6
9.2
14.4
Reference Voltage vs. Temperature
Output Voltage vs. Output Current
3.38
0.815
3.36
0.810
3.34
Output Voltage (V)
0.820
0.805
0.800
0.795
0.790
0.785
3.32
3.30
VIN = 17V
VIN = 12V
3.28
3.26
3.24
VOUT = 3.3V
VIN = 12V, VOUT = 3.3V
0.780
3.22
-50
-25
0
25
50
75
100
125
0
0.5
Temperature (°C)
1
1.5
2
Output Current (A)
Switching Frequency vs. Input Voltage
Switching Frequency vs. Temperature
820
800
810
790
Switching Frequency (KHz)1
Switching Frequency (kHz)1
17
Input Voltage (V)
Output Current (A)
Reference Voltage (V)
11.8
800
790
780
770
760
750
780
VIN = 12V
VIN = 17V
770
760
750
740
730
VOUT = 3.3V, IOUT = 0.6A
VIN = 4.5V to 17V, VOUT = 3.3V, IOUT = 0.6A
740
720
4
6
8
10
12
14
16
Input Voltage (V)
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18
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT7237C
Output Current Limit vs. Temperature
Output Current Limit vs. Input Voltage
5.0
5
Output Current Limit (A)
Output Current Limit (A)
4.5
4.0
3.5
3.0
2.5
2.0
4
3
2
1.5
VIN = 12V, VOUT = 3.3V
1.0
VIN = 4.5V to 17V, VOUT = 3.3V
1
-50
-25
0
25
50
75
100
125
4
8
10
12
14
16
Input Voltage (V)
Load Transient Response
Load Transient Response
VOUT
(200mV/Div)
VOUT
(200mV/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A
Time (100μs/Div)
Output Ripple Voltage
Output Ripple Voltage
VOUT
(5mV/Div)
VSW
(10V/Div)
VSW
(10V/Div)
IL
(1A/Div)
IL
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A
Time (500ns/Div)
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VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A
Time (100μs/Div)
VOUT
(5mV/Div)
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6
Temperature (°C)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (500ns/Div)
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RT7237C
Power On from VIN
Power Off from VIN
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
Time (25ms/Div)
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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DS7237C-05
VIN = 12V, VOUT = 3.3V, IOUT = 2A
February 2015
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
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RT7237C
Application Information
Output Voltage Setting
Soft-Start
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 1.
The RT7237C provides soft-start function. The soft-start
function is used to prevent large inrush current while
converter is being powered-up. The soft-start timing can
be programmed by the external capacitor between SS and
GND. An internal current source ISS (6μA) charges an
VOUT
R1
FB
RT7237C
R2
GND
Figure 1. Output Voltage Setting
The output voltage is set by an external resistive voltage
divider according to the following equation :
VOUT = VREF  1 R1 
 R2 
external capacitor to build a soft-start ramp voltage. The
VFB voltage will track the internal ramp voltage during softstart interval. The typical soft-start time is calculated as
follows :
0.8  CSS
Soft-Start time tSS =
, if CSS capacitor
ISS
is 0.1F, then soft-start time =
0.8  0.1
≒ 13.5ms
6
Chip Enable Operation
Where VREF is the reference voltage (0.8V typ.).
External Bootstrap Diode
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V and BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT7237C. Note that the external boot voltage must be
lower than 5.5V
5V
BOOT
RT7237C
0.1µF
The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shut down the device. During shutdown
mode, the RT7237C quiescent current drops to lower than
3μA. Driving the EN pin high (>2V, <18V) will turn on the
device again. For external timing control, the EN pin can
also be externally pulled high by adding a REN resistor
and CEN capacitor from the VIN pin (see Figure 3).
EN
VIN
EN
RT7237C
CEN
GND
Figure 3. Enable Timing Control
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2V
is available, as shown in Figure 4. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
EN pin. MOSFET Q1 will be under logic control to pull
down the EN pin.
SW
VIN
Figure 2. External Bootstrap Diode
REN
EN
REN
100k
EN
Q1
RT7237C
GND
Figure 4. Digital Enable Control Circuit
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RT7237C
Under Voltage Protection
Hiccup Mode
For the RT7237C, it provides Hiccup Mode Under Voltage
Protection (UVP). When the VFB voltage drops below 0.4V,
the UVP function will be triggered to shut down switching
operation. If the UVP condition remains for a period, the
RT7237C will retry automatically. When the UVP condition
is removed, the converter will resume operation. The UVP
is disabled during soft-start period.
Hiccup Mode
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
the highest efficiency operation. However, it requires a
large inductor to achieve this goal.
For the ripple current selection, the value of ΔIL = 0.24(IMAX)
will be a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
 VOUT  
VOUT 
L =
  1  VIN(MAX) 
f
I


L(MAX)

 

The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
VOUT
(2V/Div)
ILX
(2A/Div)
Table 2. Suggested Inductors for Typical
Application Circuit
IOUT = Short
Time (50ms/Div)
Figure 5. Hiccup Mode Under Voltage Protection
Over Temperature Protection
The RT7237C features an Over Temperature Protection
(OTP) circuitry to prevent from overheating due to
excessive power dissipation. The OTP will shut down
switching operation when junction temperature exceeds
150°C. Once the junction temperature cools down by
approximately 20°C, the converter will resume operation.
To maintain continuous operation, the maximum junction
temperature should be lower than 125°C.
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
V
V
IL =  OUT   1 OUT 
VIN 
 f L  
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DS7237C-05
February 2015
Series
Dimensions
(mm)
VLF10045
SLF12565
10 x 9.7 x 4.5
12.5 x 12.5 x 6.5
NR8040
8x8x4
Component
Supplier
TDK
TDK
TAIYO
YUDEN
CIN and COUT Selection
The input capacitance, C IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current is given :
V
IRMS = IOUT(MAX) OUT
VIN
VIN
1
VOUT
This formula has a maximum at VIN = 2VOUT, where
I RMS = I OUT/2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required. Several
capacitors may also be paralleled to meet size or height
requirements in the design. For the input capacitor, two
10μF low ESR ceramic capacitors are suggested. For the
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RT7237C
The output ripple, ΔVOUT, is determined by :
1

VOUT  IL ESR 
8fCOUT 

The output ripple will be the highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where T J(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance
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θJA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to increase
thermal performance by the PCB layout copper design.
The thermal resistance θJA can be decreased by adding
copper area under the exposed pad of SOP-8 (Exposed
Pad) package.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e)
reduces the θJA to 49°C/W.
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 of derating
curves allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation
allowed.
2.2
Four-Layer PCB
2.0
Power Dissipation (W)
suggested capacitor, please refer to Table 3 for more
details. The selection of COUT is determined by the
required ESR to minimize voltage ripple. Moreover, the
amount of bulk capacitance is also a key for COUT selection
to ensure that the control loop is stable. Loop stability
can be checked by viewing the load transient response
as described in a later section.
1.8
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum Power Dissipation
is a registered trademark of Richtek Technology Corporation.
DS7237C-05
February 2015
RT7237C
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7237C.
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W

Keep the traces of the main current paths as short and
wide as possible.

Put the input capacitor as close as possible to the device
pins (VIN and GND).

SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick-up.

Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7237C.

An example of PCB layout guide is shown in Figure 8
for reference.
(b) Copper Area = 10mm2, θJA = 64°C/W
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 , θJA = 51°C/W
(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 6. Thermal Resistance vs. Copper Area Layout
Design
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7237C-05
February 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT7237C
VIN
GND
SW GND
VIN
CBOOT
Input capacitor must
be placed as close
to the IC as possible.
BOOT
L
VOUT
REN
CSS
CIN
VIN
2
SW
3
GND
4
GND
CC
8
SS
7
EN
6
COMP
5
FB
9
The feedback components
must be connected as close
to the device as possible.
CP
RC
R1
R2
COUT
VOUT
GND
SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 8. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
Location
Component Supplier
Part No.
Capacitance (F)
Case Size
CIN
MURATA
GRM31CR61E106K
10
1206
CIN
TDK
C3225X5R1E106K
10
1206
CIN
TAIYO YUDEN
TMK316BJ106ML
10
1206
COUT
MURATA
GRM31CR60J476M
47
1206
COUT
TDK
C3225X5R0J476M
47
1210
COUT
MURATA
GRM32ER71C226M
22
1210
COUT
TDK
C3225X5R1C22M
22
1210
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS7237C-05
February 2015
RT7237C
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS7237C-05
February 2015
www.richtek.com
15