The following document contains information on Cypress products.
CM25-10139-5ET1
Errata
F2MC-8L
8-BIT MICROCONTROLLER
MB89930A Series
HARDWARE MANUAL
Page
6
Item
1.3
2004.11.16
Description
The following description of "{Mask option" in "Precautions when Selecting a Model" to be added as
indicated by shading below.
{ Mask option
The optional functions and specification method for options vary according to model. Use the mask option
after checking Appendix C "MASK OPTIONS".
Note the following:
The options for MB89PV930A and MB89P935B have been fixed. (See Appendix C "MASK OPTIONS".)
At turning on the power, when the device is used without inputting the external reset, select “power-on reset
supported” and “reset output supported” by the mask options.
50
3.5
The following item to be added to "power-on reset".
{ Power-on reset
A reset is generated by power-on. The reset operation is performed after the oscillation stabilization wait
time has passed.
When the power-on reset is generated, select “power-on reset” by the mask option. Then, turn on the power
to satisfy the standard of the power-on reset (see “ELECTRICAL CHARACTERISTICS” in the data
sheet).
Notes :
At power-on, generate the power-on reset or input an external reset.
·At power on, be sure to input the external reset when the power-on reset is not generated.
·At power on, be sure to generate the power-on reset when the external reset is not inputted.
61
3.6.2
Figure 3.6-4 to be corrected as indicated by the shading below.
·Error
SCM
WT1 WT0
System clock control register (SYCC)
CS1
CS0
-
WT1 WT0
System clock control register (SYCC)
CS1
CS0
·Correct
63
3.6.3
Figure 3.6-5 to be corrected as indicated by the shading below.
·Error
Address
0007H
bit7
-
bit6
-
bit5
-
bit4
WT1
R/W
bit3
WT0
R/W
bit2
-
bit1
CS1
R/W
bit0
CS0
R/W
Initial value
---MM-00B
Address
0007H
bit7
-
bit6
-
bit5
-
bit4
WT1
R/W
bit3
WT0
R/W
bit2
-
bit1
CS1
R/W
bit0
CS0
R/W
Initial value
---MM100B
·Correct
1/3
Page
66
Item
3.6.4
Description
The following description of "Operations in Active Mode" to be deleted as indicated by shading below
Operations in Active Mode
In active (RUN) mode, the oscillator is generating a clock. The CPU, time base timer, and other peripheral
circuits operate using the clock.
In active mode, all clock speeds except the time base timer clock speed can be changed (using gears). In
active mode, specifying standby mode results in a transition to sleep mode or stop mode.
Operations always start in RUN mode after a reset (any type). (Operating modes are canceled by a reset.)
Note:
Do not rewrite the values in the oscillation stabilization wait timer selection bits (SYCC: WT1 and
WT0) while the clock is waiting for stabilization of oscillation. Using the system clock monitor bits,
change the values in these bits after checking that SYCC: SCM is 1.
372
APPENDIX
A
Table A-1 to be corrected as indicated by the shading below.
·Error
Address
Register
abbreviation
0007H
SYCC
Register name
System clock control register
Read/write
Initial value
R/W
1--MM-00
Read/write
Initial value
R/W
---MM100
·Correct
393
APPENDIX
B
Address
Register
abbreviation
0007H
SYCC
Register name
System clock control register
Table B.5-4 to be added as indicated by the shading below.
No.
1
2
3
4
5
6
7
8
9
MNEMONIC
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
4
4
4
4
1
1
1
1
1
#
1
1
1
1
1
1
1
1
1
Operation
((SP))<-- (A),(SP) <-- (SP)-2
(A) <-- ((SP)),(SP) <-- (SP)+2
((SP)) <-- (IX),(SP) <-- (SP)-2
(IX) <-- ((SP)),(SP) <-- (SP)+2
No operation
(C) <-- 0
(C) <-- 1
(I) <-- 0
(I) <-- 1
2/3
TL
-
TH AH
- - dH
- - - - - - - -
N Z V C OP CODE
- - - - 40
- - - - 50
- - - - 41
- - - - 51
- - - - 00
- - - R 81
- - - S 91
- - - - 80
- - - - 90
Page
395
Item
APPENDIX
C
Description
Table C-1 to be added as indicated by the shading below.
Model
No.
Specification method
MB89935A MB89935B
Specified when ordering
mask
MB89P935B
MB89PV930A
Not specifiable
Main clock
Initial value of oscillation
stabilization time(*1)
218/FCH
218/FCH
Selectable
1 Selection (when FCH = 10 MHz)
(about
26.2
ms)
(about
26.2 ms)
·01: 214/FCH (about 1.63 ms)
17
·10: 2 /FCH (about 13.1 ms)
·11: 218/FCH (about 26.2 ms)
Power-on reset
Power-on reset
Power-on reset
2 ·Power-on reset supported
Selectable (*2)
supported
supported
·Power-on reset not supported
Reset pin output
3 ·Reset output supported
Selectable(*2)
Output supported Output supported
·Reset output not supported
FCH: Source Oscillation
*1: Initial value at reset of oscillation stabilization time selection bit of the system clock control register
(SYCC:WT1 and WT0)
*2: At turning on the power, when the device is used without inputting the external reset, select “power-on reset
supported” and “reset output supported” by the mask options.
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