The following document contains information on Cypress products. CM25-10135-5ET1 Errata 2 F MC-8L 8-BIT MICROCONTROLLER MB89530/530H/530A Series HARDWARE MANUAL 2004.4.21 Page 32 Item 2.1 Description The description at the upper side of Figure 2.1-1 to be corrected as indicated by shading below. •error Step-down circuit stabilization time + Power supply (VCC) oscillation stabilization wait time CPU operation of product containing stepdown circuit .... (219/Fch) •correct Step-down circuit stabilization time + Power supply (VCC) oscillation stabilization wait time CPU operation of product containing stepdown circuit .... 64 3.6 (219/Fch) (218/Fch) + The description at the center-right of Figure 3.6-1 to be corrected as indicated by shading below. •error •correct 3 3 16-bit timer counter 16-bit timer counter EC EC pin 3 8-bit serial I/O pin 3 *2 8-bit serial I/O *2 SCK1 SCK1 pin 3 Baud rate generator 6-bit PPG UART/SIO pin *1 3 *2 Baud rate generator SCK pin 2 I 2C 6-bit PPG UART/SIO I 2C SCL *2 SCK pin 2 *2 *2 *2 pin 69 3.6-3 SCL pin The description at the center-right of Figure 3.6-5 to be corrected as indicated by shading below. •error •correct WT1 WT0 0 0 0 1 1 0 1 1 Oscillation stabilization wait time select bit Main clock oscillation stabilization wait time by timebase timer output (for FCH = 12.5 MHz) Setting prohibited About 212 / FCH (about 1.31 ms) About 216 / FCH (about 10.5 ms) About 218 / FCH (about 20.97 ms) 1/5 WT1 WT0 0 0 0 1 1 0 1 1 Oscillation stabilization wait time select bit Main clock oscillation stabilization wait time by timebase timer output (for FCH = 12.5 MHz) Setting prohibited About 214 / FCH (about 1.31 ms) About 217 / FCH (about 10.5 ms) About 218 / FCH (about 20.97 ms) Page 123 Item 4.5 Description The following sentence to be corrected as indicated by shading below. •error Reference …… Note that I2C can be used with the MB89PV530, MB89P538, MB89537C/538C, MB89537HC/ 538HC, and MB89537AC/538AC only. •correct Reference …… Note that I2C can be used with the MB89PV530, MB89P538, MB89F538/F538L, MB89537C/538C, MB89537HC/538HC, and MB89537AC/538AC only. 125 4.5.1 The following sentence of “❍ Port 4 direction register (DDR4)”in” ■ Functions of the Port 4 registers” to be corrected as indicated by shading below. •error The DDR4 register sets the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. (Note that the DDR4 register does not allow bit 2 and bit 3 to be used.) •correct The DDR4 register sets the direction (I/O) of each pin by bit. Specifying 1 to the bit of a pin sets it up for output, and specifying 0 sets it up for input. For the bit 3 and bit 2 of the DDR4, when the P43 and P42 are used as the resource input pin, set the bit corresponding PDR4 register to “1” because there is no DDR. 235 9.4.2 The description at the upper-right of Figure 9.4-3 to be corrected as indicated by shading below. •error 249 9.9 •correct Measured pulse selection bits Effective only when the pulse width measurement function is selected (Fc=1) "H" level (rising edge - falling edge) Measured pulse selection bits Effective only when the pulse width measurement function is selected (Fc=1) "H" level (rising edge - falling edge) "L" (rising edge - falling edge) "L" (rising edge - falling edge) Rising edge - rising edge (one cycle) Rising edge - rising edge (one cycle) Falling edge - falling edge (one cycle) Falling edge - falling edge (one cycle) Detection of "H" level (rising edge falling edge) and the rising edge - rising edge Both edge detection The following item to be added to “❍ Notes on setting the timer using a program” in ”■ Notes on Using the Pulse Width Count Timer”. • When detecting both edges are set (PCR2: W2, W1, W0 = 001B), first detection edge will be the rising edge after the operation is enabled (PCR1: EN = 1). The counter value set by detecting both edges is initialized by the rising edge but not initialized by the falling edge. 270 11.1 The following sentence of “■ 12-Bit PPG Timer Function” to be corrected as indicated by shading below. •error • Frequencies ranging from 2 to 212-1 count clock cycles can be generated. •correct • Frequencies ranging from 2 to 212-1 count clock cycles can be generated. 2/5 Page 359 Item 15.8 Description The following sentences of “❍ Coding example” in ”■ Program Example of the A/D Conversion Function” to be corrected as indicated by shading below. •error (1st line) DDR5 : (17th line) EQU 0012H ;Address of the Port 5 direction register SETB AN0 ;Specify the P00/AN0 pin as an analog input : (34th line) MOVW A,ADDL ;Read the A/D conversion data (lower 8 bits) : •correct (1st line) PDR5 : (17th line) EQU 0012H ;Address of the Port 5 direction register SETB AN0 ;Specify the P50/AN0 pin as an analog input MOV A,ADDL ;Read the A/D conversion data (lower 8 bits) : (34th line) : 371 16.4.2 The title of Table 16.4-2 to be corrected as indicated by shading below. •error Functions of Each Bit in Serial Mode Control Register 2 (SMC2) •correct Functions of Each Bit in Serial Mode Control Register 2 (SMC22) The following Note to be added to ”16.4.2 Serial Mode Control Register 2 (SMC22)”. Note: The bit manipulation instructions (SETB, CLRB) cannot be used with the SMC22 register. As the BRGE bit which value is undefined during a read operation is write-only, the BRGE bit value may be changed by using the bit manipulation instructions. 504 22.3 The description at the bottom side of Figure 22.3-1 to be corrected as indicated by shading below. •error INTE Bit causing an interrupt to the CPU to be generated 0 Enables an interrupt when data writing/erasing is completed. 1 Disables an interrupt when data writing/erasing is completed. •correct 516 22.6.2 INTE Bit causing an interrupt to the CPU to be generated 0 Disables an interrupt when data writing/erasing is completed. 1 Enables an interrupt when data writing/erasing is completed. The following sentence of “■ Specifying addresses” to be deleted as indicated by shading below. Only even addresses can be specified in bytes for the write addresses specified in a write data cycle. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one byte for each execution. 3/5 Page 520 Item 22.6.4 Description Figure 22.6-2 to be corrected as indicated by shading below. Start of deletion FMCS: WE (bit 5) Flash memory deletion enabled Deletion command sequence (1) AAAA <-- AA (2) 5554 <-- 55 (3) AAAA <-- 80 (4) AAAA <-- AA (5) 5554 <-- 55 (6) Code input to deletion sector (30H) Y Is there another deletion sector? N Internal address read 1 Y Next sector Internal address read 2 N Toggle bit (DQ6) Data 1 (DQ6) = data 2 (DQ6) Sector Erase Completed ? Y N 0 Timing limit (DQ5) 1 Internal address read 1 Internal address read 2 N Toggle bit (DQ6) Data 1 (DQ6) = data 2 (DQ6) Y Deletion error Last sector N Y FMCS: WE (bit 5) Flash memory deletion disabled Confirmation by the hardware sequence flag Completion of deletion 523 22.7 _______ The following sentence of “■ Input of a hardware reset (RST)” to be deleted as indicated by shading below. To input a hardware reset when reading is in progress, i.e., when the automatic algorithm has not been started, secure a minimum low-level width of 500 ns. To input a hardware reset while a write or erase is in progress, i.e., while the automatic algorithm is being started, secure a minimum low-level width of 500 ns. In this case, 20 µs are required until the data becomes readable after the operation being performed terminates and the flash memory is fully initialized. Performing a hardware reset during a write operation makes the data being written undetermined. Also note that performing a hardware reset during an erase operation may make the sector from which data is being erased unusable. 4/5 Page 558 Item B.5 Description Table B.5-4 to be corrected as indicated by shading below. No. 1 2 3 4 5 6 7 8 9 MNEMONIC PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 4 4 4 4 1 1 1 1 1 OP CODE 40 50 41 51 00 R 81 S 91 80 90 # Operation TL TH AH N Z V C 1 1 1 1 1 1 1 1 1 ((SP))←(A),(SP)←(SP)-2 (A)←((SP)),(SP)←(SP)+2 ((SP))←(IX),(SP)←(SP)-2 (IX)←((SP)),(SP)←(SP)+2 No operation (C)←0 (C)←1 (I)←0 (I)←1 - - dH - - 5/5 - -