The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM26-00301-2E F2MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL 2 F MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL FUJITSU LIMITED PREFACE ■ Purpose and Audience The F2MC-8FX is original 8-bit one-chip microcontrollers that support application specific IC (ASIC). It can be widely applied from household to industrial equipment starting with portable equipment. This manual is intended for engineers who actually develop products using the F2MC-8FX microcontrollers, especially for programmers who prepare programs using the assembly language for the F2MC-8FX series assembler. It describes various instructions for the F2MC8FX. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ Organization of This Manual This manual consists of the following six chapters: CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU This chapter outlines the F2MC-8FX CPU and explains its configuration by example. CHAPTER 2 MEMORY SPACE This chapter explains the F2MC-8FX CPU memory space. CHAPTER 3 REGISTERS This chapter explains the F2MC-8FX dedicated registers and general-purpose registers. CHAPTER 4 INTERRUPT PROCESSING This chapter explains the functions and operation of F2MC-8FX interrupt processing. CHAPTER 5 CPU SOFTWARE ARCHITECTURE This chapter explains the instructions for the F2MC-8FX CPU. CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS This chapter explains each execution instruction, used in the assembler, in reference format. APPENDIX The appendix contains instruction and bus operation lists and an instruction map. i • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright© 2004-2008 FUJITSU LIMITED All rights reserved. ii CONTENTS CHAPTER 1 1.1 1.2 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU ........... 1 Outline of F2MC-8FX CPU .................................................................................................................. 2 Configuration Example of Device Using F2MC-8FX CPU .................................................................. 3 CHAPTER 2 MEMORY SPACE ........................................................................................ 5 2.1 CPU Memory Space ........................................................................................................................... 6 2.2 Memory Space and Addressing .......................................................................................................... 7 2.2.1 Data Area ...................................................................................................................................... 9 2.2.2 Program Area .............................................................................................................................. 11 2.2.3 Arrangement of 16-bit Data in Memory Space ............................................................................ 13 CHAPTER 3 3.1 3.2 3.3 3.3.1 3.3.2 3.4 3.5 3.6 3.7 Registers ........................................................................................................................ Program Counter (PC) and Stack Pointer (SP) ................................................................................ Accumulator (A) and Temporary Accumulator (T) ............................................................................ How To Use The Temporary Accumulator (T) ............................................................................. Byte Data Transfer and Operation of Accumulator (A) and Temporary Accumulator (T) ............ Program Status (PS) ......................................................................................................................... Index Register (IX) and Extra Pointer (EP) ....................................................................................... Register Banks ................................................................................................................................. Direct Banks ..................................................................................................................................... CHAPTER 4 4.1 4.2 4.3 4.4 4.5 6.2 6.3 6.4 6.5 6.6 30 32 34 36 37 CPU SOFTWARE ARCHITECTURE ......................................................... 39 Types of Addressing Modes ............................................................................................................. 40 Special Instructions ........................................................................................................................... 43 CHAPTER 6 6.1 16 17 18 20 21 23 26 27 28 INTERRUPT PROCESSING ...................................................................... 29 Outline of Interrupt Operation ........................................................................................................... Interrupt Enable/Disable and Interrupt Priority Functions ................................................................. Creating an Interrupt Processing Program ....................................................................................... Multiple Interrupt ............................................................................................................................... Reset Operation ................................................................................................................................ CHAPTER 5 5.1 5.2 REGISTERS ............................................................................................... 15 F2MC-8FX DETAILED RULES FOR EXECUTION INSTRUCTIONS .......................... 47 ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator) 48 ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) ............................ 50 ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator) 52 AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) ...................... 54 AND (AND Byte Data of Accumulator and Memory to Accumulator) ............................................... 56 ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) ................. 58 iii 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 6.52 6.53 BBC (Branch if Bit is Clear) .............................................................................................................. 60 BBS (Branch if Bit is Set) .................................................................................................................. 62 BC (Branch relative if C=1)/BLO (Branch if LOwer) ......................................................................... 64 BGE (Branch Great or Equal: relative if larger than or equal to Zero) .............................................. 66 BLT (Branch Less Than zero: relative if < Zero) ............................................................................... 68 BN (Branch relative if N = 1) ............................................................................................................. 70 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal) ................................................................ 72 BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same) ...................................................... 74 BP (Branch relative if N = 0: PLUS) .................................................................................................. 76 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal) ......................................................................... 78 CALL (CALL subroutine) ................................................................................................................... 80 CALLV (CALL Vectored subroutine) ................................................................................................. 82 CLRB (Clear direct Memory Bit) ....................................................................................................... 84 CLRC (Clear Carry flag) ................................................................................................................... 86 CLRI (CLeaR Interrupt flag) .............................................................................................................. 88 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator) ....................................... 90 CMP (CoMPare Byte Data of Accumulator and Memory) ................................................................ 92 CMP (CoMPare Byte Data of Immediate Data and Memory) ........................................................... 94 CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) .................................. 96 DAA (Decimal Adjust for Addition) .................................................................................................... 98 DAS (Decimal Adjust for Subtraction) ............................................................................................. 100 DEC (DECrement Byte Data of General-purpose Register) ........................................................... 102 DECW (DECrement Word Data of Accumulator) ........................................................................... 104 DECW (DECrement Word Data of Extra Pointer) ........................................................................... 106 DECW (DECrement Word Data of Index Pointer) .......................................................................... 108 DECW (DECrement Word Data of Stack Pointer) .......................................................................... 110 DIVU (DIVide Unsigned) ................................................................................................................. 112 INC (INCrement Byte Data of General-purpose Register) .............................................................. 114 INCW (INCrement Word Data of Accumulator) .............................................................................. 116 INCW (INCrement Word Data of Extra Pointer) ............................................................................. 118 INCW (INCrement Word Data of Index Register) ........................................................................... 120 INCW (INCrement Word Data of Stack Pointer) ............................................................................. 122 JMP (JuMP to address pointed by Accumulator) ............................................................................ 124 JMP (JuMP to effective Address) ................................................................................................... 126 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) ........ 128 MOV (MOVE Byte Data from Memory to Accumulator) .................................................................. 130 MOV (MOVE Immediate Byte Data to Memory) ............................................................................. 132 MOV (MOVE Byte Data from Accumulator to memory) .................................................................. 134 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator) 136 MOVW (MOVE Word Data from Memory to Accumulator) ............................................................. 138 MOVW (MOVE Word Data from Extra Pointer to Accumulator) ..................................................... 140 MOVW (MOVE Word Data from Index Register to Accumulator) ................................................... 142 MOVW (MOVE Word Data from Program Status Register to Accumulator) .................................. 144 MOVW (MOVE Word Data from Program Counter to Accumulator) .............................................. 146 MOVW (MOVE Word Data from Stack Pointer to Accumulator) .................................................... 148 MOVW (MOVE Word Data from Accumulator to Memory) ............................................................. 150 MOVW (MOVE Word Data from Accumulator to Extra Pointer) ..................................................... 152 iv 6.54 6.55 6.56 6.57 6.58 6.59 6.60 6.61 6.62 6.63 6.64 6.65 6.66 6.67 6.68 6.69 6.70 6.71 6.72 6.73 6.74 6.75 6.76 6.77 6.78 6.79 6.80 6.81 6.82 6.83 6.84 6.85 6.86 MOVW (MOVE Immediate Word Data to Extra Pointer) ................................................................ 154 MOVW (MOVE Word Data from Accumulator to Index Register) ................................................... 156 MOVW (MOVE Immediate Word Data to Index Register) .............................................................. 158 MOVW (MOVE Word data from Accumulator to Program Status Register) ................................... 160 MOVW (MOVE Immediate Word Data to Stack Pointer) ................................................................ 162 MOVW (MOVE Word data from Accumulator to Stack Pointer) ..................................................... 164 MULU (MULtiply Unsigned) ............................................................................................................ 166 NOP (NoOPeration) ........................................................................................................................ 168 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) ........................ 170 OR (OR Byte Data of Accumulator and Memory to Accumulator) .................................................. 172 ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) .................... 174 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) .............................................. 176 POPW (POP Word Data of Intherent Register from Stack Memory) .............................................. 178 RET (RETurn from subroutine) ....................................................................................................... 180 RETI (RETurn from Interrupt) ......................................................................................................... 182 ROLC (Rotate Byte Data of Accumulator with Carry to Left) .......................................................... 184 RORC (Rotate Byte Data of Accumulator with Carry to Right) ....................................................... 186 SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator) 188 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) .................. 190 SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator) 192 SETB (Set Direct Memory Bit) ........................................................................................................ 194 SETC (SET Carry flag) ................................................................................................................... 196 SETI (SET Interrupt flag) ................................................................................................................ 198 SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L") .................................................. 200 XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L") ............................ 202 XCHW (eXCHange Word Data Accumulator and Extrapointer) ..................................................... 204 XCHW (eXCHange Word Data Accumulator and Index Register) ................................................. 206 XCHW (eXCHange Word Data Accumulator and Program Counter) ............................................. 208 XCHW (eXCHange Word Data Accumulator and Stack Pointer) ................................................... 210 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator) .................................. 212 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) ...... 214 XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator) ............................... 216 XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator) 218 APPENDIX ......................................................................................................................... 221 APPENDIX A Instruction List ...................................................................................................................... A.1 F2MC-8FX CPU Instruction Overview ............................................................................................ A.2 Operation List ................................................................................................................................. A.3 Flag Change Table ......................................................................................................................... APPENDIX B Bus Operation List ............................................................................................................... APPENDIX C Instruction Map .................................................................................................................... 222 223 226 233 240 251 INDEX................................................................................................................................... 253 v vi Main changes in this edition Page Changes (For details, refer to main body.) 11 2.2.2 Program Area Table 2.2-2 CALLV Jump Address Table ( " FFC8H " → " FFC9H " ) 53 Execution example : ADDCW A ( NZVC = "1010" → NZVC = "0000" ) 147 Execution example : MOVW A, PC ( A = "F0 63" → A = "F0 62" ) ( PC = "F0 63" → PC = "F0 62" ) 176 6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) ( " Transfer the word value from the memory indicated by SP to dr. Then, subtract 2 fromthe value of SP. " → " Subtract 2 from the value of SP. Then, transfer the word value from the memory indicated by SP to dr. " ) 6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) ■ PUSHW (PUSH Word Data of Inherent Register to Stack Memory) ( "((SP)) <-- (dr) (Word transfer) " → " (SP) ← (SP) - 2 (Word subtraction) " ) ( " (SP) <-- (SP) - 2 (Word subtraction) " → " ((SP)) ← (dr) (Word transfer) " ) 226 A.2 Operation List ( "((iX)+off) <-- d8 " → " ((IX)+off) ← d8 " ) 232 Table A.2-4 Operation List (for Other Instructions) ( "(SP) ← (SP)-2, ((SP)) ← (A) (A) ← ((SP)), (SP ) ← (SP)+2 (SP) ← (SP)-2, ((SP)) ← (IX) (IX) ← ((SP)), (SP) ← (SP)+2 No operation (C) ← 0 (C) ← 1 (I) ← 0 (I) ← 1 " ) is added. The vertical lines marked in the left side of the page show the changes. vii viii CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU This chapter outlines the F2MC-8FX CPU and explains its configuration by example. 1.1 Outline of F2MC-8FX CPU 1.2 Configuration Example of Device Using F2MC-8FX CPU 1 CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 1.1 Outline of F2MC-8FX CPU The F2MC-8FX CPU is a high-performance 8-bit CPU designed for the embedded control of various industrial and OA equipment. ■ Outline of F2MC-8FX CPU The F2MC-8FX CPU is a high-performance 8-bit CPU designed for the control of various industrial and OA equipment. It is especially intended for applications requiring low voltages and low power consumption. This 8-bit CPU can perform 16-bit data operations and transfer and is suitable for applications requiring 16-bit control data. The F2MC-8FX CPU is upper compatibility CPU of the F2MC8L CPU, and the instruction cycle number is shortened, the division instruction is strengthened, and a direct area is enhanced. ■ F2MC-8FX CPU Features The F2MC-8FX CPU features are as follows: • Minimum instruction execution time: 100 ns • Memory: 64 Kbytes • Instruction configuration suitable for controller Data type: bit, byte, word Addressing modes: 9 types High code efficiency 16-bit data operation: Operations between accumulator (A) and temporary accumulator (T) Bit instruction: set, reset, check Multiplication/division instruction: 8 × 8 = 16 bits, 16/16 = 16 bits • 2 Interrupt priorities : 4 levels CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 1.2 Configuration Example of Device Using F2MC-8FX CPU The CPU, ROM, RAM and various resources for each F2MC-8FX device are designed in modules. The change in memory size and replacement of resources facilitate manufacturing of products for various applications. ■ Configuration Example of Device Using F2MC-8FX CPU Figure 1.2-1 shows a configuration example of a device using the F2MC-8FX CPU. Figure 1.2-1 Configuration Example of Device Using F2MC-8FX CPU IX EP PC SP RP CCR AL U Serial port A/D converter PWM RAM F2MC-8FX CPU Pins inherent to the product T F2MC-8FX BUS Common pins External bus control section Timer/counter A Pins inherent to the product ROM Clock generator Interrupt controller F2MC-8FX Device 3 CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 4 CHAPTER 2 MEMORY SPACE This chapter explains the F2MC-8FX CPU memory space. 2.1 CPU Memory Space 2.2 Memory Space and Addressing 5 CHAPTER 2 MEMORY SPACE 2.1 CPU Memory Space All of the data, program, and I/O areas managed by the F2MC-8FX CPU are assigned to the 64 Kbyte memory space of the F2MC-8FX CPU. The CPU can access each resource by indicating its address on the 16-bit address bus. ■ CPU Memory Space Figure 2.1-1 shows the address configuration of the F2MC-8FX memory space. The I/O area is located close to the least significant address, and the data area is arranged right above it. The data area can be divided into the register bank, stack and direct areas for each application. In contrast to the I/O area, the program area is located close to the most significant address. The reset, interrupt reset vector and vector call instruction tables are arranged in the highest part. Figure 2.1-1 F2MC-8FX Memory Space FFFFH Program area Data area 0000H 6 I/O CHAPTER 2 MEMORY SPACE 2.2 Memory Space and Addressing In addressing by the F2MC-8FX CPU, the applicable addressing mode related to memory access may change according to the address. Therefore, the use of the proper addressing mode increases the code efficiency of instructions. ■ Memory Space and Addressing The F2MC-8FX CPU has the following addressing modes related to memory access. ([ ] indicates one byte): • Direct addressing: Specify the lower 8 bits of the address using the operand. The accesses of operand address 00H to 7FH are always 0000H to 007FH. The accesses of operand address 80H to FFH are mapped to 0080H to 047FH by setting of direct bank pointer (DP). [Structure] [← OP code →] [← lower 8 bits →] ([← if operand available →] • Extended addressing:Specify all 16 bits using the operand. [Structure] [← OP code →] [← upper 8 bits →] [← lower 8 bits →] • Bit direct addressing:Specify the lower 8 bits of the address using the operand. The accesses of operand address 00H to 7FH are always 0000H to 007FH. The accesses of operand address 80H to FFH are mapped to 0080H to 047FH by setting of direct bank pointer (DP). The bit positions are included in the OP code. [Structure] [← OP code: bit →] [← lower 8 bits →] • Indexed addressing: Add the 8 bits of the operand to the index register (IX) together with the sign and use the result as the address. [Structure] [← OP code →] [← 8 offset bits →] ([← if operand available →]) • Pointer addressing: Use the contents of the extra pointer (EP) directly as the address. [Structure] [← OP code →] • General-purpose register addressing: Specify the general-purpose registers. The register numbers are included in the OP code. [Structure] [← OP code: register →] • Immediate addressing:Use one byte following the OP code as data. [Structure] [← OP code →] [← Immediate data →] • Vector addressing: Read the data from a table corresponding to the table number. The table numbers are included in the OP code. [Structure] [← OP code: table →] • Relative addressing: Calculate the address relatively to the contents of the current PC. This addressing mode is used during the execution of the relative jump and bit check instructions. [Structure] [← OP code: table →] [← 8 bit relative value →] Figure 2.2-1 shows the memory space accessible by each addressing mode. 7 CHAPTER 2 MEMORY SPACE Figure 2.2-1 Memory Space and Addressing FFFFH Interrupt vector FFD0H CALLV table FFC0H +127 bytes Program area External area 047FH 0100H 0000H Data area 0200H Register bank I/O area : Direct addressing : Extended addressing : Bit direct addressing : Index addressing : Pointer addressing : General-purpose register addressing : Immediate addressing : Vector addressing : Relative addressing 8 -128 bytes CHAPTER 2 MEMORY SPACE 2.2.1 Data Area The F2MC-8FX CPU data area can be divided into the following three for each purpose: • General-purpose register bank area • Stack area • Direct area ■ General-Purpose Register Bank Area The general-purpose register bank area in the F2MC-8FX CPU is assigned to 0100H to 01FFH. The generalpurpose register numbers are converted to the actual addresses according to the conversion rule shown in Figure 2.2-2 by using the register bank pointer (RP) and the lower 3 bits of the OP code. Figure 2.2-2 Conversion Rule for Actual Addresses of General-purpose Register Bank Area RP Lower bits of OP code "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 Transaction address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ■ Stack Area The stack area in the F2MC-8FX CPU is used as the saving area for return addresses and dedicated registers when the subroutine call instruction is executed and when an interrupt occurs. Before pushing data into the stack area, decrease the contents of the 16-bit stack pointer (SP) by 2 and then write the data to be saved to the address indicated by the SP. To pop data off the stack area, return data from the address indicated by the SP and then increase the contents of the SP by 2. This shows that the most recently pushed data in the stack is stored at the address indicated by the SP. Figure 2.2-3 and Figure 2.2-4 give examples of saving data in the stack area and returning data from it. 9 CHAPTER 2 MEMORY SPACE Figure 2.2-3 Example of Saving Data in Stack Area Before execution MEMORY After execution MEMORY PUSHW A SP 1235H A ABCDH 67H 1235H 1234H SP 1233H A ABCDH 1233H 67H 1235H CDH 1234H ABH 1233H 1232H 1232H Figure 2.2-4 Example of Returning Data from Stack Area Before execution SP 5678H IX XXXXH MEMORY POPW IX 567BH After execution SP 567AH IX FEDCH MEMORY 567BH 567AH 567AH DCH 5679H FEH 5678H DCH 5679H FEH 5678H ■ Direct Area The direct area in the F2MC-8FX CPU is located at the lower side of the memory space or the 1152 bytes from 0000H to 047FH and is mainly accessed by direct addressing and bit direct addressing. The area that can be used at a time by direct addressing and bit direct addressing is 256 bytes. 128 bytes of 0000H to 007FH can be used at any time as a direct area. 0080H to 047FH is a direct bank of 128 bytes × 8 and can use one direct bank as a direct area by setting the direct bank pointer (DP). Conversion from the operand address of direct addressing and bit direct addressing to the real address is done by the conversion rule shown in Table 2.2-1 by using DP. Access to it is obtained by the 2-byte instruction. The I/O control registers and part of RAM that are frequently accessed are arranged in this direct area. Table 2.2-1 Conversion Rule for Actual Address of Direct Addressing and Bit Direct Addressing Operand address Direct bank pointer (DP) 00H to 7FH 80H to FFH 10 Actual address 0000H to 007FH 000 0080H to 00FFH 001 0100H to 017FH 010 0180H to 01FFH 011 0200H to 027FH 100 0280H to 02FFH 101 0300H to 037FH 110 0380H to 03FFH 111 0400H to 047FH CHAPTER 2 MEMORY SPACE 2.2.2 Program Area The program area in the F2MC-8FX CPU includes the following two: • Vector call instruction table • Reset and interrupt vector table ■ Vector Call Instruction Table FFC0H to FFCFH of the memory space is used as the vector call instruction table. The vector call instruction for the F2MC-8FX CPU provides access to this area according to the vector numbers included in the OP code and makes a subroutine call using the data written there as the jump address. Table 2.2-2 indicates the correspondence of the vector numbers with the jump address table. Table 2.2-2 CALLV Jump Address Table CALLV #k Jump address table Upper address Lower address #0 FFC0H FFC1H #1 FFC2H FFC3H #2 FFC4H FFC5H #3 FFC6H FFC7H #4 FFC8H FFC9H #5 FFCAH FFCBH #6 FFCCH FFCDH #7 FFCEH FFCFH ■ Reset and Interrupt Vector Table FFCCH to FFFFH of the memory space is used as the table indicating the starting address of an interrupt or reset Table 2.2-3 indicates the correspondence between the interrupt numbers or resets and the reference table. 11 CHAPTER 2 MEMORY SPACE Table 2.2-3 Reset and Interrupt Vector Table Interrupt No. Table address Upper data Interrupt No. Lower data Table address Upper data Lower data FFFEH FFFFH #11 FFE4H FFE5H FFFCH FFFDH #12 FFE2H FFE3H #0 FFFAH FFFBH #13 FFE0H FFE1H #1 FFF8H FFF9H #14 FFDEH FFDFH #2 FFF6H FFF7H #15 FFDCH FFDDH #3 FFF4H FFF5H #16 FFDAH FFDBH #4 FFF2H FFF3H #17 FFD8H FFD9H #5 FFF0H FFF1H #18 FFD6H FFD7H #6 FFFEH FFFFH #19 FFD4H FFD5H #7 FFECH FFFDH #20 FFD2H FFD3H #8 FFEAH FFFBH #21 FFD0H FFD1H #9 FFE8H FFF9H #22 FFCEH FFCFH #10 FFE6H FFE7H #23 FFCCH FFCDH Reset FFFCH: Reserved FFFDH: Mode Note: The actual number varies according to the product. Use the interrupt number #22 and #23 exclusively for vector call instruction, CALLV #6 and CALLV #7 12 CHAPTER 2 MEMORY SPACE 2.2.3 Arrangement of 16-bit Data in Memory Space The F2MC-8FX CPU can perform 16-bit data transfer and arithmetic operation though it is an 8-bit CPU. Arrangement of 16-bit data in the memory space is shown below. ■ Arrangement of 16-bit Data in Memory Space As shown in Figure 2.2-5, the F2MC-8FX CPU treats 16-bit data in the memory as upper data if it is written at the first location having a lower address and as lower data if it is written at the next location after that. Figure 2.2-5 Arrangement of 16-bit Data in Memory Before execution MEMORY After execution MOVW ABCDH, A MEMORY ABCFH A ABCFH ABCEH 1234H A ABCDH 1234H 34H ABCEH 12H ABCDH ABCCH ABCCH As when 16 bits are specified by the operand during the execution of an instruction, bytes are assumed to be upper and lower in the order of their proximity to the OP code. This applies when the operand indicates the memory address and 16-bit immediate data as shown in Figure 2.2-6. Figure 2.2-6 Arrangement of 16-bit Data during Instruction Execution [Example] .: MOV A, 5678H MOVWA, #1234H .: ; ; Extended address 16-bit immediate data Assembled .: XXXXH XXXXH XXXXH XXXXH XX XX 60 56 78 E4 12 34 XX ; ; Extended address 16-bit immediate data .: The same may also apply to data saved in the stack by interrupts. 13 CHAPTER 2 MEMORY SPACE 14 CHAPTER 3 REGISTERS This chapter explains the F2MC-8FX dedicated registers and general-purpose registers. 3.1 F2MC-8FX Registers 3.2 Program Counter (PC) and Stack Pointer (SP) 3.3 Accumulator (A) and Temporary Accumulator (T) 3.4 Program Status (PS) 3.5 Index Register (IX) and Extra Pointer (EP) 3.6 Register Banks 3.7 Direct Banks 15 CHAPTER 3 REGISTERS 3.1 F2MC-8FX Registers In the F2MC-8FX series, there are two types of registers: dedicated registers in the CPU, and general-purpose registers in memory. ■ F2MC-8FX Dedicated Registers The dedicated register exists in the CPU as a dedicated hardware resource whose application is restricted to the CPU architecture. The dedicated register is composed of seven types of 16-bit registers. Some of these registers can be operated with only the lower 8 bits. Figure 3.1-1 shows the configuration of seven dedicated registers. Figure 3.1-1 Configuration of Dedicated Registers Initial value 16 bits FFFDH PC Program counter: indicates the location of the stored instructions 0000H A Accumulator: temporarily stores the result of operations and transfer 0000H T Temporary accumulator: performs operations with the accumulator 0000H IX Index register: indicates address indexes 0000H EP Extra pointer: indicates memory addresses 0000H SP Stack pointer: indicates the current location of the top of the stack RP DP CCR Program status: stores register bank pointers, direct bank pointer and condition codes CCR: IL1, 0 = 11 Other flags = 0 RP : 00000 DP : 000 PS ■ F2MC-8FX General-Purpose Registers The general-purpose register is as follows: • 16 Register bank: 8-bit length: stores data CHAPTER 3 REGISTERS 3.2 Program Counter (PC) and Stack Pointer (SP) The program counter (PC) and stack pointer (SP) are application-specific registers existing in the CPU. The program counter (PC) indicates the address of the location at which the instruction currently being executed is stored. The stack pointer (SP) holds the addresses of the data location to be referenced by the interrupt and stack push/pop instructions. The value of the current stack pointer (SP) indicates the address at which the last data pushed onto the stack is stored. ■ Program Counter (PC) Figure 3.2-1 shows the operation of the program counter (PC). Figure 3.2-1 Program Counter Operation Before execution PC After execution MEMORY 1234H PC 00H 1234H MEMORY 1235H Instruction "NOP" executed 1235H XXH 1234H 00H ■ Stack Pointer (SP) Figure 3.2-2 shows the operation of the stack pointer (SP). Figure 3.2-2 Stack Pointer Operation Before execution A 1234H SP 5678H MEMORY 5679H XXH 5678H XXH 5677H 5676H MEMORY After execution PUSHW A A 1234H SP 5676H 5679H XXH 5678H XXH 5677H 32H 5676H 12H 17 CHAPTER 3 REGISTERS 3.3 Accumulator (A) and Temporary Accumulator (T) The accumulator (A) and temporary accumulator (T) are application-specific registers existing in the CPU. The accumulator (A) is used as the area where the results of operations are temporarily stored. The temporary accumulator (T) is used as the area where the old data is temporarily saved for data transfer to the accumulator (A) or the operand for operations. ■ Accumulator (A) For 16-bit operation all 16 bits are used as shown in Figure 3.3-1. For 8-bit operation only the lower 8 bits are used as shown in Figure 3.3-2. Figure 3.3-1 Accumulator (A) Operation (16-bit Operation) Before execution A 1234H T 5678H After execution A 68ADH T 5678H ADDCW A CF 1 CF 0 Figure 3.3-2 Accumulator (A) Operation (8-bit Operation) After execution Before execution A 1234H T 5678H ADDC A CF 1 A 12ADH T 5678H CF 0 ■ Temporary Accumulator (T) When 16-bit data is transferred to the accumulator (A), all the old 16-bit data in the accumulator is transferred to the temporary accumulator (T) as shown in Figure 3.3-3. When 8-bit data is transferred to the accumulator, old 8-bit data stored in the lower 8 bits of the accumulator is transferred to the lower 8 bits of the temporary accumulator as shown in Figure 3.3-4. Although all 16-bits are used as the operand for 16-bit operations as shown in Figure 3.3-5, only the lower 8 bits are used for 8-bit operations as shown in Figure 3.3-6. 18 CHAPTER 3 REGISTERS Figure 3.3-3 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (16-bit Transfer) Before execution After execution A 5678H A 1234H T XXXXH T 5678H MOVW A, #1234H Figure 3.3-4 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (8-bit Transfer) After execution Before execution A 5678H A 5612H T XXXXH T MOV A, #12H XX78H Figure 3.3-5 Operations between Accumulator (A) and Temporary Accumulator (T) (16-bit Operations) 1234H+5678H+1 After execution Before execution A 1234H T 5678H + A 68ADH T ADDCW A 5678H CF 1 CF 0 Figure 3.3-6 Operations between Accumulator (A) and Temporary Accumulator (T) (8-bit Operations) 34H+78H+1 After execution Before execution A 1234H T 5678H CF 1 + A 12ADH T 5678H ADDC A CF 0 19 CHAPTER 3 REGISTERS 3.3.1 How To Use The Temporary Accumulator (T) The F2MC-8FX CPU has a special-purpose register called a temporary accumulator. This section described the operation of this register. ■ How to Use the Temporary Accumulator (T) The F2MC-8FX CPU has various binary operation instructions, some data transfer instructions and the temporary accumulator (T) for 16-bit data operation. Although there is no instruction for direct data transfer to the temporary accumulator, the value of the original accumulator is transferred to the temporary accumulator before executing the instruction for data transfer to the accumulator. Therefore, to perform operations between the accumulator and temporary accumulator, execute operations after carrying out the instruction for data transfer to the accumulator twice. Since data is not automatically transferred by all instructions to the temporary accumulator, see the columns of TL and TH in the instruction list for details of actual data transfer instructions. An example of addition with carry of 16-bit data stored at addresses 1280H and 0042H is shown below. MOVW A, 0042H MOVW A, 1280H ADDCW A - Figure 3.3-7 shows the operation for the accumulator and temporary accumulator when the above example is executed. Figure 3.3-7 Operation of Accumulator (A) and Temporary Accumulator (T) in Word Data Processing Before execution Last result A XXXXH A 1234H A 5678H + A 68ACH T XXXXH T XXXXH T 1234H CF 0 T 1234H RAM RAM RAM 78H 1281H 78H 1280H 56H 1280H 56H 1280H 56H 1280H 56H ... ... ... 1281H ... 78H ... 1281H ... 78H ... 1281H ... 20 RAM 0043H 34H 0043H 34H 0043H 34H 0043H 34H 0042H 12H 0042H 12H 0042H 12H 0042H 12H CHAPTER 3 REGISTERS 3.3.2 Byte Data Transfer and Operation of Accumulator (A) and Temporary Accumulator (T) When data transfer to the accumulator (A) is performed byte-by-byte, the transfer data is stored in the AL. Automatic data transfer to the temporary accumulator (T) is also performed byte-by-byte and only the contents of the original AL are stored in the TL. Neither the upper 8 bits of the accumulator nor the temporary accumulator are affected by the transfer. Only the lower 8 bits are used for byte operation between the accumulator and temporary accumulator. None of the upper 8 bits of the accumulator or temporary accumulator are affected by the operation. ■ Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing An example of addition with carry of 8-bit data stored at addresses 1280H and 0042H is shown below. MOV A, 0042H MOV A, 1280H ADDC A - Figure 3.3-8 shows the operation of the accumulator and temporary accumulator when the above example is executed. Figure 3.3-8 Operation of Accumulator and Temporary Accumulator in Byte Data Processing Before execution Last result A ABXXH A ABEFH A AB56H T CDXXH T CDXXH T CDEFH *1 0042H EFH 0042H EFH A AB*246H CF 1 T CDEFH 56H 0042H 1280H EFH 56H ... 1280H RAM ... RAM ... 56H ... ... 1280H ... 56H ... 1280H RAM ... RAM + 0042H EFH *1 The TH does not change when there is automatic data transfer to the temporary accumulator. *2 The AH is not changed by the result of the addition of the AL, TL, and CF. 21 CHAPTER 3 REGISTERS ■ Direct Data Transfer from Temporary Accumulator (T) The temporary accumulator (T) is basically temporary storage for the accumulator (A). Therefore, data from the temporary accumulator cannot be transferred directly to memory. However, as an exception, using the accumulator as a pointer enabling saving of the contents of the temporary accumulator in memory. An example of this case is shown below. Figure 3.3-9 Direct Data Transfer from Temporary Accumulator (T) [Example] MOVW @A, T Before execution After execution A 1234H A 1234H T CDEFH T CDEFH RAM 22 RAM 1235H XXH 1235H EFH 1234H XXH 1234H CDH CHAPTER 3 REGISTERS 3.4 Program Status (PS) The program status (PS) is a 16-bit application-specific register existing in the CPU. In upper byte of program status (PS), the upper 5-bit is the register bank pointer (RP) and lower 3-bit is the direct bank pointer (DP). The lower byte of program status (PS) is the condition code register (CCR). The upper byte of program status (PS), i.e. RP and DP, is mapped to address 0078H. So it is possible to make read and write accesses to them by an access to address 0078H. ■ Structure of Program Status (PS) Figure 3.4-1 shows the structure of the program status. The register bank pointer (RP) indicates the address of the register bank currently in use. The relationship between the contents of the register bank pointer and actual addresses is as shown in Figure 3.4-2. DP shows the memory area (direct bank) used for direct addressing and bit direct addressing. Conversion from the operand address of direct addressing and bit direct addressing to the real address follows the conversion rule shown in Table 3.4-1 by using DP. The condition code register (CCR) has bits for indicating the result of operations and the content of transfer data and bits for controlling the operation of the CPU in the event of an interrupt. Figure 3.4-1 Structure of Program Status (PS) 15 14 13 12 11 10 PS 9 RP DP RP DP 8 7 6 5 4 3 2 1 0 H I IL0, 1 N Z V C CCR Figure 3.4-2 Conversion Rule for Actual Address of General-purpose Register Area RP Lower bits of OP code "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 Transaction address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 23 CHAPTER 3 REGISTERS Table 3.4-1 Conversion Rule for Actual Address of Direct Addressing and Bit Direct Addressing Operand address Direct bank pointer (DP) 00H to 7FH Actual address 0000H to 007FH 80H to FFH 000 0080H to 00FFH 001 0100H to 017FH 010 0180H to 01FFH 011 0200H to 027FH 100 0280H to 02FFH 101 0300H to 037FH 110 0380H to 03FFH 111 0400H to 047FH ■ Program Status (PS) Flags The program status flags are explained below. • H flag This flag is 1 if a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 is generated as the result of an operation, and it is 0 in other cases. Because it is used for decimal compensation instructions, it cannot be guaranteed if it is used for applications other than addition or subtraction. • I flag An interrupt is enabled when this flag is 1 and is disabled when it is 0. It is set to 0 at reset which results in the interrupt disabled state. • IL1, IL0 These bits indicate the level of the currently-enabled interrupt. The interrupt is processed only when an interrupt request with a value less than that indicated by these bits is issued. • IL1 IL0 Interrupt level High and low 0 0 0 Highest 0 1 1 1 0 2 1 1 3 Lowest N flag This flag is 1 when the most significant bit is 1 and is 0 when it is 0 as the result of an operation. • Z flag This flag is 1 when the most significant bit is 0 and is 0 in other cases as the result of an operation. • 24 V flag CHAPTER 3 REGISTERS This flag is 1 when a two’s complement overflow occurs and is 0 when one does not as the result of an operation. • C flag This flag is 1 when a carry or a borrow, from bit 7 in byte mode and from bit 15 in word mode, is generated as the result of an operation but 0 in other cases. The shifted-out value is provided by the shift instruction. ■ Access to Register Bank Pointer and Direct Bank Pointer The upper byte of program status (PS), i.e. register bank pointer (RP) and direct bank pointer (DP), is mapped to address 0078H. So it is possible to make read and write accesses to them by an access to address 0078H, besides using instructions that have access to PS (MOVW A, PS or MOVW PS, A). 25 CHAPTER 3 REGISTERS 3.5 Index Register (IX) and Extra Pointer (EP) The index register (IX) and extra pointer (EP) are 16-bit application-specific registers existing in the CPU. The index register (IX) adds an 8-bit offset value with its sign to generate the address stored by the operand. The extra pointer (EP) indicates the address stored by the operand. ■ Index Register (IX) Figure 3.5-1 indicates the operation of the index register. Figure 3.5-1 Operation of Index Register (IX) Before execution A XXXXH IX 5678H MEMORY 56CFH 56CEH 56CDH 34H 12H After execution A 1234H IX 5678H MEMORY 56CFH 56CEH 34H 56CDH 12H 56CCH 56CCH MOVW A, @IX+55H 5678H+0055H = 56CDH + ■ Extra Pointer (EP) Figure 3.5-2 shows the operation of the extra pointer. Figure 3.5-2 Operation of the Extra Pointer (EP) MEMORY Before execution A XXXXH EP 5678H 5679H 34H 5678H 12H 5677H 5676H 26 After execution A 1234H EP 5678H MOVW A, @EP MEMORY 5679H 34H 5678H 12H 5677H 5676H CHAPTER 3 REGISTERS 3.6 Register Banks The register bank register is an 8-bit general-purpose register existing in memory. There are eight registers per bank of which there can be 32 altogether. The current bank is indicated by the register bank pointer (RP). ■ Register Bank Register Figure 3.6-1 shows the configuration of the register bank. Figure 3.6-1 Configuration of Register Bank Address = 0100H + 8 * (RP) R0 R1 R2 R3 R4 R5 R6 R7 Maximum of 32 banks Memory area 27 CHAPTER 3 REGISTERS 3.7 Direct Banks The direct bank is in 0080H to 047FH of direct area, and composed of 128 bytes × 8 banks. The access that uses direct addressing and bit direct addressing in operand address 80H to FFH can be extended to 8 direct banks according to the value of the direct bank pointer (DP). The current bank is indicated by the direct bank pointer (DP). ■ Direct Bank Figure 3.7-1 shows the configuration of a direct bank. The access that uses direct addressing and bit direct addressing in operand address 80H to FFH can be extended to 8 direct banks according to the value of the direct bank pointer (DP). The access that uses direct addressing and bit direct addressing in operand address 00H to 7FH is not affected by the value of the direct bank pointer (DP). This access is directed to fixed direct area 0000H to 007FH. Figure 3.7-1 Configuration of Direct Bank Memory Direct bank 7 (DP=111) 047FH 0400H Direct bank 1 (DP=001) 017FH 0100H FFH 80H Direct bank 0 (DP=000) 00FFH 0080H 7FH 00H Fixed direct area 007FH 0000H Direct addressing and Operand address in bit direct addressing 28 Direct area CHAPTER 4 INTERRUPT PROCESSING This chapter explains the functions and operation of F2MC-8FX interrupt processing. 4.1 Outline of Interrupt Operation 4.2 Interrupt Enable/Disable and Interrupt Priority Functions 4.3 Creating an Interrupt Processing Program 4.4 Multiple Interrupt 4.5 Reset Operation 29 CHAPTER 4 INTERRUPT PROCESSING 4.1 Outline of Interrupt Operation F2MC-8FX series interrupts have the following features: • Four interrupt priority levels • All maskable features • Vector jump feature by which the program jumps to address mentioned in the interrupt vector. ■ Outline of Interrupt Operation In the F2MC-8FX series, interrupts are transferred and processed according to the following procedure: 1. An interrupt source occurs in resources. 2. Refer to interrupt enable bits in resources. If an interrupt is enabled, interrupt requests are issued from resources to the interrupt controller. 3. As soon as an interrupt request is received, the interrupt controller decides the priorities of the interrupt requested and then transfers the interrupt level corresponding to the interrupts applicable to the CPU. 4. The CPU compares the interrupt levels requested by the interrupt controller with the IL bit in the program status register. 5. In the comparison, the CPU checks the contents of the I flag in the same program status register only if the priority is higher than the current interrupt processing level. 6. In the check in 5., the CPU sets the contents of the IL bit to the requested level only if the I flag is enabled for interrupts, processes interrupts as soon as the instruction currently being executed is completed and then transfers control to the interrupt processing routine. 7. The CPU clears the interrupt source caused in 1. using software in the user’s interrupt processing routine to terminate the processing of interrupts. 30 CHAPTER 4 INTERRUPT PROCESSING Figure 4.1-1 shows the flow diagram of F2MC-8FX interrupt operation. Internal bus Figure 4.1-1 Outline of F2MC-8FX Interrupt Operation 2 F MC-8FX CPU I IL 6 4 Check Comparator 5 Peripheral Interrupt request enable bit 7 Interrupt request flag AND 1 Peripheral 2 Level comparator 3 Interrupt controller 31 CHAPTER 4 INTERRUPT PROCESSING 4.2 Interrupt Enable/Disable and Interrupt Priority Functions In the F2MC-8FX series, interrupt requests are transferred to the CPU using the three types of enable/disable functions listed below. • Request enable check by interrupt enable flags in resources • Checking the level using the interrupt level determination function • Interrupt start check by the I flag in the CPU Interrupts generated in resources are transferred to the CPU with the priority levels determined by the interrupt priority function. ■ Interrupt Enable/Disable Functions • Request enable check by interrupt enable flags in resources This is a function to enable/disable a request at the interrupt source. If interrupt enable flags in resources are enabled, interrupt request signals are sent from resources to the interrupt controller. This function is used for controlling the presence or absence of an interrupt, resource-by-resource. It is very useful because when software is described for each resource operation, interrupts in another resource do not need to be checked for whether they are enabled or disabled. • Checking the level using the interrupt level determination function This function determines the interrupt level. The interrupt levels corresponding to interrupts generated in resources are compared with the IL bit in the CPU. If the value is less than the IL bit, a decision is made to issue an interrupt request. This function is able to assign priorities if there are two or more interrupts. • Interrupt start check by the I flag in the CPU The I flag enables or disables the entire interrupt. If an interrupt request is issued and the I flag in the CPU is set to interrupt enable, the CPU temporarily suspends the flow of instruction execution to process interrupts. This function is able to temporarily disable the entire interrupt. ■ Interrupt Requests in Resources As shown in Figure 4.2-1, interrupts generated in resources are converted by the corresponding interrupt level registers in the interrupt controller into the values set by software and then transferred to the CPU. The interrupt level is defined as high if its numerical value is lower, and low if it is higher. 32 CHAPTER 4 INTERRUPT PROCESSING Figure 4.2-1 Relationship between Interrupt Request and Interrupt Level in Resources To CPU Interrupt level register Resource #1 1H Interrupt request F/F 2H Resource #n 0H ... ... ... ... Resource #2 3H Interrupt controller 33 CHAPTER 4 INTERRUPT PROCESSING 4.3 Creating an Interrupt Processing Program In the F2MC-8FX series, basically, interrupt requests from resources are issued by hardware and cleared by software. ■ Creating an Interrupt Processing Program The interrupt processing control flow is as follows: 1. Initialize resources before operation. 2. Wait until an interrupt occurs. 3. In the event of an interrupt, if the interrupt can be accepted, perform interrupt processing to branch to the interrupt processing routine. 4. First, set software so as to clear the interrupt source at the beginning of the interrupt processing routine. This is done so that the resource causing an interrupt can regenerate the interrupt during the interrupt processing program. 5. Next, perform interrupt processing to transfer the necessary data. 6. Use the interrupt release instruction to release the interrupt from interrupt processing. 7. Then, continue to execute the main program until an interrupt recurs. The typical interrupt processing flow is shown in Figure 4.3-1. The numbers in the figure correspond to the numbers above. Figure 4.3-1 Interrupt Processing Flow Interrupt processing program Main program Set the interrupt request from the resource in hardware and issue an interrupt request. Initialize the resource. Set he interrupt level to the IL bit. → Prevent multiple interrupts of the same level. Clear the interrupt source: To accept a multiple interrupts from the same resource. Interrupt processing program: Transfer the actual processing data. Release the interrupt from the interrupt processing. The time to transfer control to the interrupt processing routine after the occurrence of an interrupt 3 in Figure 4.3-1) is 9 instruction cycles. An interrupt can only be processed in the last cycle of each instruction. The time shown in Figure 4.3-2 is required to transfer control to the interrupt processing routine after an interrupt occurs. The longest cycle (17 + 9 = 26 instruction cycles) is required when an interrupt request is issued immediately after starting the execution of the DIVU instruction. 34 CHAPTER 4 INTERRUPT PROCESSING Figure 4.3-2 Interrupt Response Time CPU operation Interrupt wait time Normal instruction execution Sample wait (a) Interrupt request issued Interrupt handling 9 instruction cycles (b) Interrupt processing program Indicates the last instruction cycle in which an interrupt is sampled. Note: It will take (a) + (b) instruction cycles to transfer control to the interrupt processing routine after an interrupt occurs. 35 CHAPTER 4 INTERRUPT PROCESSING 4.4 Multiple Interrupt The F2MC-8FX CPU can have a maximum of four levels as maskable interrupts. These can be used to assign priorities to interrupts from resources. ■ Multiple Interrupt A specific example is given below. • When giving priority over the A/D converter to the timer interrupt START MOV ADIL, #2 Set the interrupt level of the A/D converter to 2. MOV TMIL, #1 Set the interrupt level of the timer to 1. ADIL and TMIL are IL bits in the interrupt controller. CALL STAD Start the A/D converter. CALL STTM Start the timer. . . . When the above program is started, interrupts are generated from the A/D converter and timer after an elapsed time. In this case, when the timer interrupt occurs while processing the A/D converter interrupt, it will be processed through the sequence shown in Figure 4.4-1. Figure 4.4-1 Example of Multiple Interrupt ... Main program Initialize the resource. The A/D converter interrupt occurs. IL=2 Process the timer interrupt. IL=1 Timer interrupt occurs. Suspended Resumed Process the timer interrupt. Release the timer interrupt. Process the A/D ı converter interrupt. Release the timer interrupt. ... The main program is resumed. ı A/D converter interrupt processing When starting processing of an A/D converter interrupt, the IL bit in the PS register of the CPU is automatically the same as the value of request (2 here). Therefore, when a level 1 or 0 interrupt request is issued during the processing of an A/D converter interrupt, the processing proceeds without disabling the A/D converter interrupt request. When temporarily disabling interrupts lower in priority than this interrupt during A/D converter interrupt processing, disable the I flag in the PS register of the CPU for the interrupts or set the IL bit to 0. When control is returned to the interrupted routine by the release instruction after completion of each interrupt processing routine, the PS register is set to the value saved in the stack. Consequently, the IL bit takes on the value before interruption. For actual coding, refer to the Hardware Manual for each device to check the addresses of the interrupt controller and each resource and the interrupts to be supported. 36 CHAPTER 4 INTERRUPT PROCESSING 4.5 Reset Operation In the F2MC-8FX series, when a reset occurs, the flag of program status is 0 and the IL bit is set to 11. When cleared, the reset operation is executed from the starting address written to set vectors (FFFEH, FFFFH). ■ Reset Operation A reset affects: • Accumulator, temporary accumulator: Initializes to 0000H • Stack pointer: Initializes to 0000H • Extra pointer, index register: Initializes to 0000H • Program status: Sets flag to 0, sets IL bit to 11, sets RP bit to 00000 and Initializes DP bit to 000 • Program counter: Reset vector values • RAM (including general-purpose registers): Keeps value before reset • Resources: Basically stop • Others: Refer to the manual for each product for the condition of each pin Refer to the manual for each product for details of the value and operation of each register for special reset conditions. 37 CHAPTER 4 INTERRUPT PROCESSING 38 CHAPTER 5 CPU SOFTWARE ARCHITECTURE This chapter explains the instructions for the F2MC-8FX CPU. 5.1 Types of Addressing Modes 5.2 Special Instructions 39 CHAPTER 5 CPU SOFTWARE ARCHITECTURE 5.1 Types of Addressing Modes The F2MC-8FX CPU has the following ten addressing modes: • Direct addressing (dir) • Extended addressing (ext) • Bit direct addressing (dir:b) • Indexed addressing (@IX+off) • Pointer addressing (@EP) • General-purpose register addressing (Ri) • Immediate addressing (#imm) • Vector addressing (#k) • Relative addressing (rel) • Inherent addressing ■ Direct Addressing (dir) This addressing mode, indicated as "dir" in the instruction list, is used to access the direct area from 0000H to 047FH. In this addressing, when the operand address is 00H to 7FH, it accesses 0000H to 007FH. Moreover, when the operand address is 80H to FFH, the access is good to 0080H to 047FH at the mapping by direct bank pointer DP setting. [Example] MOV 92H,A DP 001B 0112H 45H A 45H ■ Extended Addressing (ext) This addressing mode, indicated as "ext" in the instruction list, is used to access the entire 64-Kbyte area. In this addressing mode, the upper byte is specified by the first operand and the lower byte by the second operand. ■ Bit Direct Addressing (dir:b) This addressing mode, indicated as "dir:b" in the instruction list, is used for bit-by-bit access of the direct area from 0000H to 047FH. In this addressing, when the operand address is 00H to 7FH, it accesses 0000H to 007FH. Moreover, when the operand address is 80H to FFH, the access is good to 0080H to 047FH at the mapping by direct bank pointer DP setting. The position of the bit in the specified address is specified by the value for the instruction code of three subordinate position bits. [Example] DP 40 XXXB 7 6 5 4 3 2 1 0 SETB 34H: 2 0034H X X X X X 1 X X B CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ Index Addressing (@IX+off) This addressing mode, indicated as "@IX+off" in the instruction list, is used to access the entire 64-Kbyte area. In this addressing mode, the contents of the first operand are sign-extended and then added to the index register (IX). The result is used as the address. [Example] IX MOVW A, @IX+5AH 27A5H 2800H + 34H 1234H A 27FFH 12H ■ Pointer Addressing (@EP) This addressing mode, indicated as "@EP" in the instruction list, is used to access the entire 64-Kbyte area. In this addressing mode, the contents of the extra pointer (EP) are used as the address. [Example] EP MOVW A, @EP 27A5H 27A6H 34H 27A5H 12H A 1234H ■ General-Purpose Register Addressing (Ri) This addressing mode, indicated as "Ri" in the instruction list, is used to access the register bank area. In this addressing mode, one upper byte of the address is set to 01 and one lower byte is created from the contents of the register bank pointer (RP) and the 3 lower bits of the instruction to access this address. [Example] RP MOV A, R2 01010B 0152H ABH A ABH ■ Immediate Addressing (#imm) This addressing mode, indicated as "#imm" in the instruction list, is used for acquiring the immediate data. In this addressing mode, the operand is used directly as the immediate data. The byte or word is specified by the instruction code. [Example] MOV A, #56H A 56H 41 CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ Vector Addressing (#k) This addressing mode, indicated as "#k" in the instruction list, is used for branching to the subroutine address registered in the table. In this addressing mode, the information about #k is contained in the instruction code and the table addresses listed in Table 5.1-1 are created. Table 5.1-1 Jump Address Table #k Address table (upper jump address: lower jump address) 0 FFC0H:FFC1H 1 FFC2H:FFC3H 2 FFC4H:FFC5H 3 FFC6H:FFC7H 4 FFC8H:FFC9H 5 FFCAH:FFCBH 6 FFCCH:FFCDH 7 FFCEH:FFCFH [Example] CALLV #5 (Conversion) FEH FFCAH FFCBH DCH PC FEDCH ■ Relative Addressing (rel) This addressing mode, indicated as "rel" in the instruction list, is used for branching to the 128-byte area across the program counter (PC). In this addressing mode, the contents of the operand are added with their sign, to the program counter. The result is stored in the program counter. [Example] Old PC BNE +FEH 9ABCH { 9ABCH + FFFEH New PC 9ABAH In this example, the program jumps to the address where the instruction code BNE is stored, resulting in an infinite loop. ■ Inherent Addressing This addressing mode, which has no operand in the instruction list, is used for operations to be determined by the instruction code. In this addressing mode, the operation varies for every instruction. [Example] Old PC 42 NOP 9ABCH New PC 9ABDH CHAPTER 5 CPU SOFTWARE ARCHITECTURE 5.2 Special Instructions In the F2MC-8FX series, the following six special instructions are available: • JMP @A • MOVW A, PC • MULU A • DIVU A • XCHW A, PC • CALLV #k ■ JMP @A This instruction is used for branching to an address where the contents of the accumulator (A) are used. The contents of one of the N jump addresses arranged in table form is selected and transferred to the accumulator. Executing this instruction enables the N-branch processing. [Example] JMP @A After execution Before execution 1234H Old PC XXXXH A 1234H New PC 1234H ■ MOVW A, PC This instruction is used for performing the opposite operation to JMP @A. In other words, it stores, the contents of the program counter (PC) in the accumulator (A). When this instruction is executed in the main routine and a specific subroutine is to be called, make sure that the contents of the accumulator are the specified value in the subroutine, that is the branch is from the expected section, enabling a decision on crash. [Example] MOVW A, PC After execution Before execution A Old PC XXXXH 1234H A New PC 1234H 1234H When this instruction is executed, the contents of the accumulator are the same as those of the address where the code for the next instruction is stored and not the address where the code for this instruction is stored. The above example shows that the value 1234H stored in the accumulator agrees with that of the address where the instruction code next to MOVW A, PC is stored. 43 CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ MULU A This instruction is used for multiplying 8 bits of the AL by 8 bits of the TL without a sign and stores the 16bit result in the accumulator (A). The contents of the temporary accumulator (T) do not change. In the operation, the original contents of the AH and TH are not used. Since the flag does not change, attention must be paid to the result of multiplication when branching accordingly. [Example] MULU A, T After execution Before execution A 5678H A 1860H T 1234H T 1234H ■ DIVU A This instruction is used for dividing 16 bits of the temporary accumulator (T) by 16 bits of the A without a sign and stores the results as 16 bits in the A and the remainder as 16 bits in the T. When A is 0000H, Z flag is 1 as 0 division. At this time, the operation result is not guaranteed. [Example] DIVU A Before execution After execution A 1234H A 0004H T 5678H T 0DA8H ■ XCHW A, PC This instruction is used for exchanging the contents of the accumulator (A) for those of the program counter (PC). As a result, the program branches to the address indicated by the contents of the original accumulator and the contents of the current accumulator become the value of the address next to the one where the instruction code XCHW A, PC is stored. This instruction is provided especially for specifying tables using the main routine and for subroutines to use them. [Example] XCHW A, PC After execution Before execution A 5678H A 1235H PC 1234H PC 5678H When this instruction is executed, the contents of the accumulator are the same as those of the address where the code for the next instruction is stored and not the address where the code for this instruction is stored. The above example shows that the value of the accumulator 1235H agrees with that of the address where the instruction code next to XCHW A, PC is stored. Consequently, 1235H not 1234H is indicated. 44 CHAPTER 5 CPU SOFTWARE ARCHITECTURE Figure 5.2-1 Example of Using XCHW A, PC [Main routine] ... [Subroutine] MOVW A, #PUTSUB XCHW A, PC PUTSUB XCHW A, EP PUSHW A DB 'PUT OUT DATA', EOL PTS1 MOVW A, #1234H MOV A, @EP INCW EP ... MOV IO, A ... Output table data here. CMP A, #EOL BNE PTS1 POPW A XCHW A, EP JMP @A ■ CALLV #k This instruction is used for branching to a subroutine address registered in the table. In this addressing mode, the information about #k is included in the instruction code and the tale addresses listed in Table 5.21 are created. After saving the contents of the current program counter (PC) in the stack, the program branches to the address in the table. Because it is a 1-byte instruction, using it for frequently-used subroutines reduces the size of the entire program. Table 5.2-1 Jump Address Table #k Address table (upper jump address : lower jump address) 0 FFC0H:FFC1H 1 FFC2H:FFC3H 2 FFC4H:FFC5H 3 FFC6H:FFC7H 4 FFC8H:FFC9H 5 FFCAH:FFCBH 6 FFCCH:FFCDH 7 FFCEH:FFCFH 45 CHAPTER 5 CPU SOFTWARE ARCHITECTURE [Example] CALLV #3 Before execution PC 5678H SP 1234H (- 2) PC FEDCH SP 1232H DCH 1234H FEH FFC6H FEH ... FFC7H ... DCH ... 1234H ... 46 After execution 1233H XXH 1233H 79H 1232H XXH 1232H 56H CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS This chapter explains each execution instruction, used in the assembler, in reference format. All execution insurrections are described in alphabetical order. For information about the outline of each item and the meaning of symbols (abbreviations) explained for each execution instruction, see "CHAPTER 5 CPU SOFTWARE ARCHITECTURE". 47 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.1 ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Add the byte data of TL to that of AL, add a carry to the LSB and then return the results to AL. The contents of AH are not changed. ■ ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Operation (AL) ← (AL) + (TL) + (C) (Byte addition with carry) Assembler format ADDC A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycle: 1 Byte count: 1 OP code: 22 48 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDC A Memory FFFFH A 12 34 A 12 AC T 56 78 T 56 78 IX IX SP SP PC PC Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 1 0 (After execution) 49 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.2 ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) Add the byte data of EA memory (memory expressed in each type of addressing) to that of AL, add a carry to the LSB and then return the results to AL. The contents of AH are not changed. ■ ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) Operation (AL) ← (AL) + (EA) + (C) (Byte addition with carry) Assembler format ADDC A, EA Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Table 6.2-1 Number of Execution Cycles / Byte Count / OP Code EA 50 #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 24 25 26 27 28 to 2F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDC A, #25H Memory A 12 FFFFH 34 A T T IX IX SP SP PC PC Byte 12 Memory FFFFH Byte 0000H 5A 0000H EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 51 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.3 ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Add the word data of T to that of A, add a carry to the LSB and then return the results to A. ■ ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Operation (A) ← (A) + (T) + (C) (Word addition with carry) Assembler format ADDCW A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycle: 1 Byte count: 1 OP code: 23 52 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDCW A Memory FFFFH A 12 34 A 68 AD T 56 78 T 56 78 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 53 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.4 AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical AND on the byte data of AL and TL for every bit and return the result to AL. The byte data of AH is not changed. ■ AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) Operation (AL) ← (AL) ^ (TL) (Byte AND) Assembler format AND A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 62 54 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : AND A Memory FFFFH A 12 34 A 12 24 T XX 2C T XX 2C IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 55 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.5 AND (AND Byte Data of Accumulator and Memory to Accumulator) Carry out the logical AND on the byte data of AL and EA memory (memory expressed in each type of addressing) for every bit and return the result to AL. The byte data of AH is not changed. ■ AND (AND Byte Data of Accumulator and Memory to Accumulator) Operation (AL) ← (AL) ^ (EA) (Byte AND) Assembler format AND A, EA Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Table 6.5-1 Number of Execution Cycles / Byte Count / OP Code 56 EA #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 64 65 66 67 68 to 6F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : AND , @EP Memory A 02 FFFFH 53 A T T IX IX 31 0123H SP SP PC PC EP Byte 01 PS Byte 0000H 23 Byte N Z V C 0 0 1 0 (Before execution) EP 02 01 FFFFH 31 0123H Byte 0000H 11 23 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 57 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.6 ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical AND on the word data of A and T for every bit and return the results to A. ■ ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) Operation (A) ← (A) ^ (T) (Word AND) Assembler format ANDW A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 63 58 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ANDW A Memory FFFFH A 56 63 A 14 22 T 34 32 T 34 32 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 59 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.7 BBC (Branch if Bit is Clear) Branch when the value of bit b in dir memory is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BBC (Branch if Bit is Clear) Operation (bit)b = 0: (PC) ← (PC) + 3 + rel (Word addition) (bit)b = 1: (PC) ← (PC) + 3 (Word addition) Assembler format BBC dir:b, rel Condition code (CCR) N Z V C - + - - +: Changed by executing instruction -: Not changed N: Not changed Z: Set to 1 when the value of dir:b is 0 and set to 0 when it is 1. V: Not changed C: Not changed Number of execution cycles: 5 Byte count: 3 OP code: B0 to B7 60 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BBC 84H : 0, 0FBH Memory FFFFH Memory FFFFH B0 E800H A A B0 E800H T T E7FEH IX IX SP SP bit0 bit0 PC E8 00 XXXX XXX0 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) PC E7 FE XXXX XXX0 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 1 0 0 (After execution) 61 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.8 BBS (Branch if Bit is Set) Branch when the value of bit b in dir memory is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BBS (Branch if Bit is Set) Operation (bit)b = 0: (PC) ← (PC) + 3 (Word addition) (bit)b = 1: (PC) ← (PC) + 3 + rel (Word addition) Assembler format BBS dir:b, rel Condition code (CCR) N Z V C - + - - +: Changed by executing instruction -: Not changed N: Not changed Z: Set to 1 when the value of dir:b is 0 and set to 0 when it is 1. V: Not changed C: Not changed Number of execution cycles: 5 Byte count: 3 OP code: B8 to BF 62 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BBS 84H : 0, 0FBH Memory FFFFH Memory FFFFH B0 E800H A A B0 E800H T T E7FEH IX IX SP SP bit0 bit0 PC E8 00 XXXX XXX1 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) PC E7 FE XXXX XXX1 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 63 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.9 BC (Branch relative if C=1)/BLO (Branch if LOwer) Execute the next instruction if the C-flag is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BC (Branch relative if C=1)/BLO (Branch if LOwer) Operation (C) = 0: (PC) ← (PC) + 2 (Word addition) (C) = 1: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BC rel/BLO rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: F9 64 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BC 0FEH Memory FFFFH Memory A A T T IX IX FFFFH E804H SP F9 PC E8 PC Byte PS Byte Byte F9 F802H 02 EP FE SP FE 0000H N Z V C 1 1 1 0 (Before execution) E8 E802H 04 Byte EP PS Byte Byte 0000H N Z V C 1 1 1 0 (After execution) 65 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.10 BGE (Branch Great or Equal: relative if larger than or equal to Zero) Execute the next instruction if the logical exclusive-OR for the V and N flags is 1 and the branch if it is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BGE (Branch Great or Equal: relative if larger than or equal to Zero) Operation (V) ∀ (N) = 1: (PC) ← (PC) + 2 (Word addition) (V) ∀ (N) = 0: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BGE rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FE 66 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BGE 02H Memory FFFFH Memory A A T T IX IX FFFFH F458H SP FE PC F4 F456H PC 56 Byte EP PS Byte Byte 02 SP 02 0000H N Z V C 0 1 1 1 (Before execution) F4 F456H Byte 0000H 58 EP PS Byte FE Byte N Z V C 0 1 1 1 (After execution) 67 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.11 BLT (Branch Less Than zero: relative if < Zero) Execute the next instruction if the logical exclusive-OR for the V and N flags is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BLT (Branch Less Than zero: relative if < Zero) Operation (V) ∀ (N) = 0: (PC) ← (PC) + 2 (Word addition) (V) ∀ (N) = 1: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BLT rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FF 68 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BLT 02H Memory FFFFH Memory A A T T FFFFH F45AH IX IX F458H SP F4 F456H PC 56 Byte EP PS Byte Byte 02 SP 02 FF PC F458H 0000H N Z V C 0 1 1 1 (Before execution) F4 F456H Byte 0000H 5A EP PS Byte FF Byte N Z V C 0 1 1 1 (After execution) 69 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.12 BN (Branch relative if N = 1) Execute the next instruction if the N-flag is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BN (Branch relative if N = 1) Operation N = 0: (PC) ← (PC) + 2 (Word addition) N = 1: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BN rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FB 70 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BN 02H Memory FFFFH Memory A A T T IX IX FC63H SP SP 02 02 PC FFFFH FC FB 5F FC5FH Byte EP PS Byte Byte 0000H N Z V C 1 1 1 0 (Before execution) PC FC 63 EP PS Byte Byte FB FC5FH Byte 0000H N Z V C 1 1 1 0 (After execution) 71 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.13 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal) Execute the next instruction if the Z-flag is 1 and the branch if it is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal) Operation (Z) = 1: (PC) ← (PC) + 2 (Word addition) (Z) = 0: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BNZ rel/BNE rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FC 72 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BNZ 0FAH Memory FFFFH Memory A A T T IX IX FFFFH FE20H SP FC PC FE FE1EH PC 1E Byte EP PS Byte Byte FA SP FA 0000H N Z V C 0 1 0 0 (Before execution) FE FE1EH Byte 0000H 20 EP PS Byte FC Byte N Z V C 0 1 0 0 (After execution) 73 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.14 BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same) Execute the next instruction if the C-flag is 1 and the branch if it is 0 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same) Operation (C) = 1: (PC) ← (PC) + 2 (Word addition) (C) = 0: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BNC rel/BHS rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: F8 74 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BNC 01H Memory FFFFH Memory A A T T IX IX FFFFH E805H E804H E804H SP F8 PC E8 E802H PC 02 Byte EP PS Byte Byte 01 SP 01 0000H N Z V C 1 1 1 0 (Before execution) E8 E802H Byte 0000H 05 EP PS Byte F8 Byte N Z V C 1 1 1 0 (After execution) 75 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.15 BP (Branch relative if N = 0: PLUS) Execute the next instruction if the N-flag is 1 and the branch if it is 0 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BP (Branch relative if N = 0: PLUS) Operation (N) = 1: (PC) ← (PC) + 2 (Word addition) (N) = 1: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BP rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FA 76 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BP 04H Memory FFFFH Memory A A T T IX IX FFFFH FC61H SP FA PC FC FC5FH PC 5F Byte EP PS Byte Byte 04 SP 04 0000H N Z V C 1 0 1 1 (Before execution) FC FC5FH Byte 0000H 61 EP PS Byte FA Byte N Z V C 1 0 1 1 (After execution) 77 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.16 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal) Execute the next instruction if the Z-flag is 0 and the branch if it is 1 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value). ■ BZ (Branch relative if Z = 1)/BEQ (Branch if Equal) Operation (Z) = 0: (PC) ← (PC) + 2 (Word addition) (Z) = 1: (PC) ← (PC) + 2 + rel (Word addition) Assembler format BZ rel/BEQ rel Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence) Byte count: 2 OP code: FD 78 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BZ 0FAH Memory FFFFH Memory FFFFH A A FE20H T T FA FA FE1EH FD FE1EH FD IX IX SP SP FE1AH PC FE PC 1E Byte FE 1A 0000H Byte 0000H EP EP PS Byte Byte N Z V C 0 1 0 0 (Before execution) PS Byte Byte N Z V C 0 1 0 0 (After execution) 79 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.17 CALL (CALL subroutine) Branch to address of ext. Return to the instruction next to this one by using the RET instruction of the branch subroutine. ■ CALL (CALL subroutine) Operation (SP) ← (SP) - 2 (Word subtraction), ((SP)) ← (PC) (Word transfer) (PC) ← ext Assembler format CALL ext Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 6 Byte count: 3 OP code: 31 80 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CALL 0FC00H Memory FFFFH Memory A A T T IX IX FFFFH 020AH 020AH SP PC 02 F6 SP OA PC 23 Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 02 FC 26 08 0208H Byte 0000H 00 EP PS Byte F6 Byte N Z V C 0 0 0 0 (After execution) 81 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.18 CALLV (CALL Vectored subroutine) Branch to the vector address (VA) of vct. Return to the instruction next to this one by using the RET instruction of the branch subroutine. The vector address (VA) indicated by VCT is shown on the next page. ■ CALLV (CALL Vectored subroutine) Operation (SP) ← (SP) - 2 (Word subtraction), ((SP)) ← (PC) (Word transfer) (PC) ← (VA) Assembler format CALLV #vct Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 7 Byte count: 1 OP code: E8 to EF 82 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CALL #02H Memory FFFFH Memory FFFFH A A vct 00 FFC5H 02 EC FFC4H T T EC00H IX IX 0208H 0208H SP PC 02 E8 SP 08 PC 00 Byte EP PS Byte 0000H N Z V C 0 0 0 0 EC 01 06 PS Byte E8 0206H Byte 0000H 00 EP (Before execution) Byte 02 N Z V C 0 0 0 0 Byte (After execution) Table 6.18-1 Call Storage Address of Vector Call Instruction Vector address (VA) Instruction Lower address Upper address FFCEH FFCFH CALL#7 FFCCH FFCDH CALL#6 FFCAH FFCBH CALL#5 FFC8H FFC9H CALL#4 FFC6H FFC7H CALL#3 FFC4H FFC5H CALL#2 FFC2H FFC3H CALL#1 FFC0H FFC1H CALL#0 83 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.19 CLRB (Clear direct Memory Bit) Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) of the direct area to 0. ■ CLRB (Clear direct Memory Bit) Operation (dir:b) ← 0 Assembler format CLRB dir:b Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 Byte count: 2 OP code: A0 to A7 84 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRB 84H : 0 Memory Memory FFFFH A A T T IX IX SP SP 0000 000X 0084H 0000 0000 0084H PC PC 0000H Byte EP PS FFFFH 00 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 0000H Byte EP 00 Byte Byte N Z V C 0 0 0 0 (After execution) 85 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.20 CLRC (Clear Carry flag) Set the C-flag to 0. ■ CLRC (Clear Carry flag) Operation (C) ← 0 Assembler format CLRC Condition code (CCR) N Z V C - - - R +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Not changed Z: Not changed V: Not changed C: Set to 0. Number of execution cycle: 1 Byte count: 1 OP code: 81 86 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRC Memory FFFFH A A T T IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 87 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.21 CLRI (CLeaR Interrupt flag) Set the I-flag to 0. ■ CLRI (CLeaR Interrupt flag) Operation (I) ← 0 Assembler format CLRI Condition code (CCR) I N Z V C R - - - - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction I: Set to 0 N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 80 88 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRI Memory FFFFH A A T T IX IX SP SP PC PC 0000H Byte EP PS Byte H I 0 1 IL1 IL0 1 1 N Z V C 0 0 0 1 Byte (Before execution) Memory FFFFH Byte 0000H EP PS Byte H I 0 0 IL1 IL0 1 1 N Z V C 0 0 0 1 Byte (After execution) 89 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.22 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator) Compare the byte data of AL with that of TL and set the results to CCR. AL and TL are not changed. ■ CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator) Operation (TL) - (AL) Assembler format CMP A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycle: 1 Byte count: 1 OP code: 12 90 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP A Memory FFFFH A XX 75 A XX 75 T XX 48 T XX 48 IX IX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 0 1 (After execution) 91 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.23 CMP (CoMPare Byte Data of Accumulator and Memory) Compare the byte data of AL with that of the EA memory (memory expressed in each type of addressing) and set the results to CCR. AL and EA memory are not changed. ■ CMP (CoMPare Byte Data of Accumulator and Memory) Operation (AL) - (EA) Assembler format CMP A, EA Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Table 6.23-1 Number of Execution Cycles / Byte Count / OP Code EA 92 #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 14 15 16 17 18 to 1F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP A , 80H Memory A XX FFFFH A 23 T T IX IX 56 SP 0180H FFFFH 56 0180H Byte 0000H 23 SP PC PC 0000H Byte EP EP PS XX Memory 02 Byte Byte N Z V C 0 0 0 1 (Before execution) PS 02 Byte Byte N Z V C 1 0 0 1 (After execution) 93 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.24 CMP (CoMPare Byte Data of Immediate Data and Memory) Compare the byte data of EA memory (memory expressed in each type of addressing) with the immediate data and set the results to CCR. EA memory is not changed. ■ CMP (CoMPare Byte Data of Immediate Data and Memory) Operation (EA) - d8 Assembler format CMP EA, #d8 Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Table 6.24-1 Number of Execution Cycles / Byte Count / OP Code EA 94 dir @IX+off @EP Ri Number of execution cycles 4 4 3 3 Byte count 3 3 2 2 OP code 95 96 97 98 to 9F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP @EP , #33H Memory FFFFH A A T T IX IX 54 SP 0120H FFFFH 54 0120H Byte 0000H SP PC PC EP Memory Byte 01 PS Byte 0000H 20 Byte N Z V C 0 0 0 1 (Before execution) EP 01 20 PS Byte Byte N Z V C 0 0 0 0 (After execution) 95 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.25 CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) Compare the word data of A with that of T and set the results to CCR. A and T are not changed. ■ CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) Operation (T) - (A) Assembler format CMPW A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycles: 2 Byte count: 1 OP code: 13 96 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMPW A Memory FFFFH A 86 75 A 86 75 T 24 48 T 24 48 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 1 1 (After execution) 97 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.26 DAA (Decimal Adjust for Addition) When adding the correction value to AL by the state in the carry before execution of instruction and half-carry, decimal operation is corrected. ■ DAA (Decimal Adjust for Addition) Operation (AL) ← (AL) + 6 or 60H or 66H (Add a correction value shown in the next page to AL and the value of AL according to the state of the C or H-flag.) Assembler format DAA Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Change as indicated on the next page. Number of execution cycle: 1 Byte count: 1 OP code: 84 98 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DAA Memory A XX FFFFH A 4A XX T T IX IX SP SP PC PC Memory FFFFH Byte 0000H 50 0000H Byte EP EP H PS 0 I IL1 IL0 0 1 1 Byte N 0 Z V 0 0 C PS 0 H I 0 0 Byte Byte IL1 IL0 1 1 N Z V C 0 0 0 0 Byte (Before execution) (After execution) Table 6.26-1 Decimal Adjustment Table (DAA) C-flag AL (bit7 to bit4) H-flag AL (bit3 to bit0) Correction value C-flag after execution 0 0 0 0 0 0 1 1 1 0 to 9 0 to 8 0 to 9 A to F 9 to F A to F 0 to 2 0 to 2 0 to 3 0 0 1 0 0 1 0 0 1 0 to 9 A to F 0 to 3 0 to 9 A to F 0 to 3 0 to 9 A to F 0 to 3 00 06 06 60 66 66 60 66 66 0 0 0 1 1 1 1 1 1 Table 6.26-2 Execution Example Mnemonic AL C H MOV A, #75H 75 0 × ADDC A, #25H 9A 0 0 DAA 00 1 0 99 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.27 DAS (Decimal Adjust for Subtraction) Subtract the correction value from AL according to the state of the C or H-flag before executing instruction. ■ DAS (Decimal Adjust for Subtraction) Operation (AL) ← (AL) - 6 or 60H or 66H (Subtract a correction value shown in the next page to AL and the value of AL according to the state of the C or H-flag.) Assembler format DAS Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Change as indicated on the next page. Number of execution cycle: 1 Byte count: 1 OP code: 94 100 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DAS Memory A XX FFFFH A 2F XX T T IX IX SP SP PC PC Memory FFFFH Byte 0000H 29 0000H Byte EP EP H PS 1 I 0 IL1 IL0 1 Byte N 1 0 Z 0 V C 0 PS 0 H I 1 0 Byte Byte IL1 IL0 1 1 N Z V C 0 0 0 0 Byte (Before execution) (After execution) Table 6.27-1 Decimal Adjustment Table (DAS) C-flag H-flag Correction value C-flag after execution 0 1 0 1 0 1 1 0 00 66 06 60 0 1 0 1 Table 6.27-2 Execution Example Mnemonic AL C H MOV A, #70H 70 × × SUBC A, #25H 4B 0 1 DAS 45 0 1 101 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.28 DEC (DECrement Byte Data of General-purpose Register) Decrement byte data of Ri by one. ■ DEC (DECrement Byte Data of General-purpose Register) Operation (Ri) ← (Ri) - 1 (byte subtract) Assembler format DEC Ri Condition code (CCR) N Z V C + + + - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Not changed Number of execution cycles: 3 Byte count: 1 OP code: D8 to DF 102 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DEC R2 Memory FFFFH Memory A A T T IX IX R2 R2 0112H FE SP 0112H FD SP R1 R1 R0 0110H R0 0110H PC PC 0000H Byte 0000H Byte EP EP PS FFFFH 10 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 10 Byte Byte N Z V C 1 0 0 0 (After execution) 103 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.29 DECW (DECrement Word Data of Accumulator) Decrement word data of A by one. ■ DECW (DECrement Word Data of Accumulator) Operation (A) ← (A) - 1 (Word subtraction) Assembler format DECW A Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: D0 104 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW A Memory A 78 FFFFH 22 A T T IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 78 Memory FFFFH Byte 0000H 21 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 105 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.30 DECW (DECrement Word Data of Extra Pointer) Decrement word data of EP by one. ■ DECW (DECrement Word Data of Extra Pointer) Operation (EP) ← (EP) - 1 (Word subtraction) Assembler format DECW EP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: D3 106 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW EP Memory FFFFH A A T T IX IX SP SP PC PC EP 0000H Byte 12 34 PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP 12 FFFFH Byte 0000H 33 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 107 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.31 DECW (DECrement Word Data of Index Pointer) Decrement word data of IX by one. ■ DECW (DECrement Word Data of Index Pointer) Operation (IX) ← (IX) - 1 (Word subtraction) Assembler format DECW IX Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: D2 108 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW IX Memory FFFFH A A T T IX 16 IX 27 SP SP PC PC Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 16 Memory FFFFH Byte 0000H 26 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 109 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.32 DECW (DECrement Word Data of Stack Pointer) Decrement word data of SP by one. ■ DECW (DECrement Word Data of Stack Pointer) Operation (SP) ← (SP) - 1 (Word subtraction) Assembler format DECW SP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: D1 110 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW SP Memory FFFFH Memory FFFFH Byte 0000H Byte 0000H N Z V C N Z V C 0 0 0 0 0 0 0 0 (Before execution) (After execution) 111 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.33 DIVU (DIVide Unsigned) Divide the word data of T by that of AL as an unsigned binary value. Return the quotient to A and the remainder to T. When A is 0, the result is indefinite and Z flag is 1 to show 0 division. ■ DIVU (DIVide Unsigned) Operation Quotient (A) ← (T) / (A) Remainder (T) ← (T) MOD (A) Assembler format DIVU A Condition code (CCR) N Z V C - + - - +: Changed by executing instruction -: Not changed N: Not changed Z: Set to 1 if A before execution of instruction is 0000H and set to 0 in other cases. V: Not changed C: Not changed Number of execution cycles: 17 Byte count: 1 OP code: 11 112 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DIVU A Memory FFFFH A 00 OA A 00 20 T 01 41 T 00 01 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 113 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.34 INC (INCrement Byte Data of General-purpose Register) Add 1 to byte data of Ri. ■ INC (INCrement Byte Data of General-purpose Register) Operation (Ri) ← (Ri) + 1 (Word addition) Assembler format INC Ri Condition code (CCR) N Z V C + + + - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Not changed Number of execution cycles: 3 Byte count: 1 OP code: C8 to CF 114 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INC R1 Memory FFFFH A A T T IX IX SP SP R1 56 0108H Byte EP PS 08 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) FFFFH 57 0109H R1 0109H R0 PC Memory R0 PC 0108H Byte EP PS 08 Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 115 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.35 INCW (INCrement Word Data of Accumulator) Add 1 to word data of A. ■ INCW (INCrement Word Data of Accumulator) Operation (A) ← (A) +1 (Word addition) Assembler format INCW A Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: C0 116 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW A Memory A 12 FFFFH A 33 T T IX IX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 12 Memory FFFFH Byte 0000H 34 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 117 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.36 INCW (INCrement Word Data of Extra Pointer) Add 1 to word data of EP. ■ INCW (INCrement Word Data of Extra Pointer) Operation (EP) ← (EP) + 1 (Word addition) Assembler format INCW EP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: C3 118 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW EP Memory FFFFH A A T T IX IX SP SP PC PC EP 25 PS Byte Byte 42 Byte 0000H N Z V C 0 0 0 0 (Before execution) EP 25 FFFFH Byte 0000H 43 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 119 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.37 INCW (INCrement Word Data of Index Register) Add 1 to word data of IX. ■ INCW (INCrement Word Data of Index Register) Operation (IX) ← (IX) + 1 (Word addition) Assembler format INCW IX Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: C2 120 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW IX Memory FFFFH A A T T IX 25 IX 72 SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 25 Memory FFFFH Byte 0000H 73 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 121 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.38 INCW (INCrement Word Data of Stack Pointer) Add 1 to word data of SP. ■ INCW (INCrement Word Data of Stack Pointer) Operation (SP) ← (SP) + 1 (Word addition) Assembler format INCW SP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: C1 122 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW SP Memory FFFFH A A T T IX IX SP FF SP FF 00 Memory FFFFH Byte 0000H 00 PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 123 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.39 JMP (JuMP to address pointed by Accumulator) Transfer word data from A to PC. ■ JMP (JuMP to address pointed by Accumulator) Operation (PC) ← (A) (Word transfer) Assembler format JMP @A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 1 OP code: E0 124 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : JMP @A Memory A F0 FFFFH A 89 T T IX IX SP SP PC XX PC XX Byte F0 89 F0 89 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 125 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.40 JMP (JuMP to effective Address) Branch to the PC value indicated by ext. ■ JMP (JuMP to effective Address) Operation (PC) ← ext (Word transfer) Assembler format JMP ext Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 Byte count: 3 OP code: 21 126 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : JMP 0E654H Memory FFFFH Memory A A T T IX IX FFFFH E654H 54 SP 54 SP E6 21 PC D8 D800H PC 00 Byte EP PS Byte Byte E6 0000H N Z V C 0 1 1 1 (Before execution) E6 D800H Byte 0000H 54 EP PS Byte 21 Byte N Z V C 0 1 1 1 (After execution) 127 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.41 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) Transfer byte data from T to memory indirectly addressed by A. ■ MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) Operation ((A)) ← T (Word transfer) Assembler format MOV @A, T Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 2 Byte count: 1 OP code: 82 128 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV @A, T Memory FFFFH A 01 20 A 01 20 T XX 3F T XX 3F Memory FFFFH 3F 0120H Byte 0000H IX IX XX SP 0120H SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 129 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.42 MOV (MOVE Byte Data from Memory to Accumulator) Transfer byte data from EA memory (memory expressed in each type of addressing) to A. Byte data in AL is transferred to TL. AH is not changed. ■ MOV (MOVE Byte Data from Memory to Accumulator) Operation (AL) ← (EA) (Byte transfer) Assembler format MOV A, EA Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of transferred data is 1 and set to 0 in other cases. Z: Set to 1 if transferred data is 00H and set to 0 in other cases. V: Not changed C: Not changed Table 6.42-1 Number of Execution Cycles / Byte Count / OP Code EA 130 #d8 dir @IX+off ext @A @EP Ri Number of execution cycles 2 3 3 4 2 2 2 Byte count 2 2 2 3 1 1 1 OP code 04 05 06 60 92 07 08 to 0F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV A, 83H Memory FFFFH A 11 22 A 11 51 T XX XX T XX 22 FFFFH 51 0383H Byte 0000H IX IX 51 0383H SP SP PC PC Byte 0000H EP EP PS Memory 06 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 06 Byte Byte N Z V C 0 0 0 0 (After execution) 131 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.43 MOV (MOVE Immediate Byte Data to Memory) Transfer byte immediate data to EA memory (memory expressed in each type of addressing). ■ MOV (MOVE Immediate Byte Data to Memory) Operation (EA) ← d8 (Byte transfer) Assembler format MOV EA, #d8 Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.43-1 Number of Execution Cycles / Byte Count / OP Code EA 132 dir @IX+off @EP Ri Number of execution cycles 4 4 3 3 Byte count 3 3 2 2 OP code 85 86 87 88 to 8F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV @IX+02, #35H Memory Memory FFFFH A A T T IX 02 00 0202H XX IX 02 FFFFH 00 0202H 35 (IX+2) (IX+2) SP SP 0200H 0200H PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 133 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.44 MOV (MOVE Byte Data from Accumulator to memory) Transfer bytes (data from AL) immediate data to EA memory (memory expressed in each type of addressing). ■ MOV (MOVE Byte Data from Accumulator to memory) Operation (EA) ← (AL) (Byte transfer) Assembler format MOV EA, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.44-1 Number of Execution Cycles / Byte Count / OP Code EA 134 dir @IX+off ext @EP Ri Number of execution cycles 3 3 4 2 2 Byte count 2 2 3 1 1 OP code 45 46 61 47 48 to 4F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV 82H, A Memory A XX FFFFH A 06 T T IX IX SP SP FFFFH 06 0202H Byte 0000H 06 0202H XX PC PC 0000H Byte EP EP PS XX Memory 03 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 03 Byte Byte N Z V C 0 0 0 0 (After execution) 135 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.45 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator) Transfer word data from T to memory indirectly addressed by A. ■ MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator) Operation ((A)) ← (T) (Word transfer) Assembler format MOVW @A, T Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 1 OP code: 83 136 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW @A, T Memory FFFFH A 01 78 A 01 78 T FB AA T FB AA Memory FFFFH AA 0179H FB 0178H Byte 0000H IX IX XX SP 0179H 0178H XX SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 137 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.46 MOVW (MOVE Word Data from Memory to Accumulator) Transfer word data from EA and EA + 1 memories (EA is an address expressed in each type of addressing) to A. Word data in A is transferred to T. ■ MOVW (MOVE Word Data from Memory to Accumulator) Operation (A) ← (EA) (Word transfer) Assembler format MOVW A, EA Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if MSB of transferred data is 1 and set to 0 in other cases. Z: Set to 1 if transferred data is 0000H and set to 0 in other cases. V: Not changed C: Not changed Table 6.46-1 Number of Execution Cycles / Byte Count / OP Code EA #d16 dir @IX+off ext @A @EP Number of execution cycles 3 4 4 5 3 3 Byte count 3 2 2 3 1 1 E4 C5 C6 C4 93 C7 OP code 138 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, @IX+01H Memory FFFFH Memory A 01 02 A EF 23 T XX XX T 01 02 IX 01 50 IX 01 50 SP 23 23 EF EF SP FFFFH 0151H (IX+1) 0150H 0150H PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Byte EP PS Byte Byte 0000H N Z V C 1 0 0 0 (After execution) 139 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.47 MOVW (MOVE Word Data from Extra Pointer to Accumulator) Transfer word data from EP to A. ■ MOVW (MOVE Word Data from Extra Pointer to Accumulator) Operation (A) ← (EP) (Word transfer) Assembler format MOVW A, EP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: F3 140 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, EP Memory A XX FFFFH A XX T T IX IX SP SP PC PC 96 Byte EP 32 PS Byte FFFFH Byte 0000H 32 0000H Byte EP 96 Memory N Z V C 0 0 0 0 (Before execution) 96 32 PS Byte Byte N Z V C 0 0 0 0 (After execution) 141 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.48 MOVW (MOVE Word Data from Index Register to Accumulator) Transfer word data from IX to A. ■ MOVW (MOVE Word Data from Index Register to Accumulator) Operation (A) ← (IX) (Word transfer) Assembler format MOVW A, IX Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: F2 142 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, IX Memory A XX FFFFH A XX 23 87 23 FFFFH Byte 0000H T T IX 87 Memory 87 IX 23 SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 143 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.49 MOVW (MOVE Word Data from Program Status Register to Accumulator) Transfer word data from PS to A. ■ MOVW (MOVE Word Data from Program Status Register to Accumulator) Operation (A) ← (PS) (Word transfer) Assembler format MOVW A, PS Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 70 144 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, PS Memory A XX FFFFH A XX T T IX IX SP SP PC PC Byte EP PS 78 18 Byte Byte 0000H N Z V C 1 0 0 0 (Before execution) 78 Memory FFFFH Byte 0000H 18 EP PS 78 18 Byte Byte N Z V C 1 0 0 0 (After execution) 145 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.50 MOVW (MOVE Word Data from Program Counter to Accumulator) Transfer word data from PC to A. ■ MOVW (MOVE Word Data from Program Counter to Accumulator) Operation (A) ← (PC) (Word transfer) Assembler format MOVW A, PC Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 2 Byte count: 1 OP code: F0 146 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, PC Memory A XX FFFFH A XX T T IX IX SP SP PC F0 PC 62 Byte F0 62 F0 62 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 147 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.51 MOVW (MOVE Word Data from Stack Pointer to Accumulator) Transfer word data from SP to A. ■ MOVW (MOVE Word Data from Stack Pointer to Accumulator) Operation (A) ← (SP) (Word transfer) Assembler format MOVW A, SP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: F1 148 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, SP Memory A XX FFFFH A XX T T IX IX SP 69 SP 05 69 05 69 05 Memory FFFFH Byte 0000H PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 149 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.52 MOVW (MOVE Word Data from Accumulator to Memory) Transfer word data from A to EA and EA + 1 memories (memory expressed in each type of addressing). ■ MOVW (MOVE Word Data from Accumulator to Memory) Operation (EA) ← (A) (Word transfer) Assembler format MOVW EA, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.52-1 Number of Execution Cycles / Byte Count / OP Code EA dir @IX+off ext @EP Number of execution cycles 4 4 5 3 Byte count 2 2 3 1 D5 D6 D4 D7 OP code 150 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW 93H, A Memory A 10 FFFFH A 56 T T IX IX XX 0094H XX 0093H SP FFFFH 56 0094H 10 0093H Byte 0000H 56 SP PC PC 0000H Byte EP PS 10 Memory 00 Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS 00 Byte Byte N Z V C 0 0 0 0 (After execution) 151 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.53 MOVW (MOVE Word Data from Accumulator to Extra Pointer) Transfer word data from A to EP. ■ MOVW (MOVE Word Data from Accumulator to Extra Pointer) Operation (EP) ← (A) (Word transfer) Assembler format MOVW EP, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: E3 152 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW EP, A Memory A 87 FFFFH A 65 T T IX IX SP SP PC PC XX Byte EP XX PS Byte 65 87 65 FFFFH Byte 0000H 0000H Byte EP 87 Memory N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 153 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.54 MOVW (MOVE Immediate Word Data to Extra Pointer) Transfer word immediate data to EP. ■ MOVW (MOVE Immediate Word Data to Extra Pointer) Operation (EP) ← d16 (Word transfer) Assembler format MOVW EP, #d16 Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 3 OP code: E7 154 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW EP, #2345H Memory FFFFH A A T T IX IX SP SP PC PC EP 0000H Byte XX XX PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP 23 FFFFH Byte 0000H 45 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 155 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.55 MOVW (MOVE Word Data from Accumulator to Index Register) Transfer word data from A to IX. ■ MOVW (MOVE Word Data from Accumulator to Index Register) Operation (IX) ← (A) (Word transfer) Assembler format MOVW IX, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: E2 156 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW IX, A Memory A 56 FFFFH 43 A 43 56 43 FFFFH Byte 0000H T T IX 56 Memory XX IX XX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 157 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.56 MOVW (MOVE Immediate Word Data to Index Register) Transfer word immediate data to IX. ■ MOVW (MOVE Immediate Word Data to Index Register) Operation (IX) ← d16 (Word transfer) Assembler format MOVW IX, #d16 Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 3 OP code: E6 158 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW IX, #4567H Memory FFFFH A A T T IX XX IX XX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 45 Memory FFFFH Byte 0000H 67 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 159 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.57 MOVW (MOVE Word data from Accumulator to Program Status Register) Transfer word data from A to PS. ■ MOVW (MOVE Word data from Accumulator to Program Status Register) Operation (PS) ← (A) (Word transfer) Assembler format MOVW PS, A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Become the value for lower bit 3 of A Z: Become the value for lower bit 2 of A V: Become the value for lower bit 1 of A C: Become the value for lower bit 0 of A Number of execution cycle: 1 Byte count: 1 OP code: 71 160 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW PS, A Memory A 50 Memory FFFFH A 32 T T IX IX SP SP PC PC Byte 32 Byte 0000H 0000H EP EP PS 50 FFFFH XX XX Byte Byte N Z X X V X C X (Before execution) PS 50 32 Byte Byte N Z 0 0 V 1 C 0 (After execution) 161 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.58 MOVW (MOVE Immediate Word Data to Stack Pointer) Transfer word immediate data to SP. ■ MOVW (MOVE Immediate Word Data to Stack Pointer) Operation (SP) ← d16 (Word transfer) Assembler format MOVW SP, #d16 Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 3 OP code: E5 162 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW SP, #6789H Memory FFFFH A A T T IX IX SP XX SP XX 67 Memory FFFFH Byte 0000H 89 PC PC 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 163 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.59 MOVW (MOVE Word data from Accumulator to Stack Pointer) Transfer word data from A to SP. ■ MOVW (MOVE Word data from Accumulator to Stack Pointer) Operation (SP) ← (A) (Word transfer) Assembler format MOVW SP, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: E1 164 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW SP, A Memory A 43 FFFFH A 21 T T IX IX SP XX SP XX 43 21 43 21 Memory FFFFH Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 165 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.60 MULU (MULtiply Unsigned) Multiply the byte data of AL and TL as unsigned binary values. Return the results to the word data of A. ■ MULU (MULtiply Unsigned) Operation (A) ← (AL) * (TL) Assembler format MULU A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 8 Byte count: 1 OP code: 01 166 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MULU A Memory FFFFH A XX 20 A 08 00 T XX 40 T XX 40 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 167 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.61 NOP (NoOPeration) No operation ■ NOP (NoOPeration) Operation ———— Assembler format NOP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 00 168 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : NOP Memory FFFFH Memory A A T T FFFFH IX IX PC+1 PC+1 PC SP PC SP PC PC Byte 0000H EP N Z V Byte EP N C Z 0000H V C PS PS Byte Byte (Before execution) Byte Byte (After execution) 169 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.62 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical OR on byte data of AL and TL for every bit and return the results to AL. The contents of AH are not changed. ■ OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Operation (AL) ← (AL) ∨ (TL) (byte logical OR) Assembler format OR A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 72 170 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : OR A Memory FFFFH A 15 23 A 15 63 T XX 41 T XX 41 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 171 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.63 OR (OR Byte Data of Accumulator and Memory to Accumulator) Carry out the logical OR on AL and EA memory (memory expressed in each type of addressing) for every bit and return the results to AL. The contents of AH are not changed. ■ OR (OR Byte Data of Accumulator and Memory to Accumulator) Operation (AL) ← (AL)∨ (EA) (byte logical OR) Assembler format OR A, EA Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Table 6.63-1 Number of Execution Cycles / Byte Count / OP Code EA 172 #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 74 75 76 77 78 to 7F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : OR A, @EP Memory A 15 Memory FFFFH A 32 76 T T IX IX 56 0122H SP SP PC PC 0000H Byte EP 15 FFFFH 01 PS Byte EP 22 Byte N Z V C 0 0 0 0 (Before execution) 01 0122H Byte 0000H 22 PS Byte 56 Byte N Z V C 0 0 0 0 (After execution) 173 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.64 ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical OR on the word data of A and T for every bit and return the results to A. ■ ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) Operation (A) ← (A) ∨ (T) (word logical OR) Assembler format ORW A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 73 174 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ORW A Memory FFFFH A 57 23 A 77 63 T 33 41 T 33 41 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 175 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) Subtract 2 from the value of SP. Then, transfer the word value from the memory indicated by SP to dr. ■ PUSHW (PUSH Word Data of Inherent Register to Stack Memory) Operation (SP) ← (SP) - 2 (Word subtraction) ((SP)) ← (dr) (Word transfer) Assembler format PUSHW dr Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.65-1 Number of Execution Cycles / Byte Count / OP Code DR 176 A IX Number of execution cycles 4 4 Byte count 1 1 OP code 40 41 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : PUSHW IX Memory FFFFH Memory A A T T IX 12 IX 34 12 FFFFH 34 0222H SP 02 22 0222H SP X 02 20 34 X 12 0220H Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 177 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.66 POPW (POP Word Data of Intherent Register from Stack Memory) Transfer the word value from the memory indicated by SP to dr. Then, add 2 to the value of SP. ■ POPW (POP Word Data of Intherent Register from Stack Memory) Operation (dr) ← ((SP)) (Word transfer) (SP) ← (SP) + 2 (Word addition) Assembler format POPW dr Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.66-1 Number of Execution Cycles / Byte Count / OP Code DR 178 A IX Number of execution cycles 3 3 Byte count 1 1 OP code 50 51 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : POPW A Memory A XX Memory FFFFH A XX T T IX IX 31 FFFFH 26 0235H SP 02 33 SP 26 31 02 35 26 0233H 31 0233H Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 179 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.67 RET (RETurn from subroutine) Return the contents of PC saved in the stack. When this instruction is used in combination with the CALLV or CALL instruction, return to the next instruction to each of them. ■ RET (RETurn from subroutine) Operation (PC) ← ((SP)) (Word transfer) (SP) ← (SP) + 2 (Word addition) Assembler format RET Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 6 Byte count: 1 OP code: 20 180 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RET Memory FFFFH Memory A A T T IX IX SP 02 SP 06 02 0208H 08 10 PC F8 10 FC 09 FFFFH 0206H Byte PC FC 10 0000H FC 0206H Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 181 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.68 RETI (RETurn from Interrupt) Return the contents of PS and PC saved in the stack. Return PS and PC to the state before interrupt. ■ RETI (RETurn from Interrupt) Operation (PS) ← ((SP)), (PC) ← ((SP + 2)) (Word transfer) (SP) ← (SP) + 4 (Word addition) Assembler format RETI Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Become to the saved value of N. Z: Become to the saved value of Z. V: Become to the saved value of V. C: Become to the saved value of C. Number of execution cycles: 8 Byte count: 1 OP code: 30 182 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RETI Memory Memory FFFFH A A T T IX IX FFFFH 020AH 10 10 SP 02 FC 06 SP 02 84 84 PC XX 0206H 08 XX Byte PC FC 10 0000H 08 0206H Byte 0000H EP EP PS 0208H FC OA XX XB Byte Byte N Z V C 1 0 1 1 (Before execution) PS 08 84 Byte Byte N Z V C 0 1 0 0 (After execution) 183 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.69 ROLC (Rotate Byte Data of Accumulator with Carry to Left) Shift byte data of AL with a carry one bit to the left. The contents of AH are not changed. ■ ROLC (Rotate Byte Data of Accumulator with Carry to Left) Operation AL C Assembler format ROLC A Condition code (CCR) N Z V C + + - + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases. Z: Set to 1 if the result of the shift is 00H and set to 0 in other cases. V: Not changed C: Enter Bit 7 of A before shift. Number of execution cycle: 1 Byte count: 1 OP code: 02 184 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ROLC A Memory A XX FFFFH A 55 T T IX IX SP SP PC PC Byte XX Memory FFFFH Byte 0000H AB 0000H EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 185 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.70 RORC (Rotate Byte Data of Accumulator with Carry to Right) Shift byte data of AL with a carry bit to the right. The contents of AH are not changed. ■ RORC (Rotate Byte Data of Accumulator with Carry to Right) Operation AL C Assembler format RORC A Condition code (CCR) N Z V C + + - + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases. Z: Set to 1 if the result of the shift is 00H and set to 0 in other cases. V: Not changed C: LSB of A before entering shift Number of execution cycle: 1 Byte count: 1 OP code: 03 186 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RORC A Memory A XX FFFFH A 55 T T IX IX SP SP PC PC Byte XX Memory FFFFH Byte 0000H AA 0000H EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 1 0 0 1 (After execution) 187 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.71 SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Subtract the byte data of AL from that of TL, subtract a carry and then return the result to AL. The contents of AH are not changed. ■ SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Operation (AL) ← (TL) - (AL) - C (Byte subtraction with carry) Assembler format SUBC A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycle: 1 Byte count: 1 OP code: 32 188 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBC A Memory FFFFH A 12 23 A 12 11 T 76 34 T 76 34 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 189 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.72 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) Subtract the byte data of the EA memory (memory expressed in each type of addressing) from that of AL, subtract a carry and then return the results to AL. The contents of AH are not changed. ■ SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) Operation (AL) ← (AL) - (EA) - C (Byte subtraction with carry) Assembler format SUBC A, EA Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Table 6.72-1 Number of Execution Cycles / Byte Count / OP Code EA 190 #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 34 35 36 37 38 to 3F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBC A, #37H Memory A 12 FFFFH A 34 T T IX IX SP SP PC PC Byte 12 Memory FFFFH Byte 0000H FD 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 1 (After execution) 191 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.73 SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Subtract the word data of A from that of T, subtract a carry and then return the result to A. ■ SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Operation (AL) ← (T) - (A) - C (Word subtraction with carry) Assembler format SUBCW A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases. C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases. Number of execution cycle: 1 Byte count: 1 OP code: 33 192 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBCW A Memory FFFFH A 32 14 A 24 20 T 56 34 T 56 34 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 193 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.74 SETB (Set Direct Memory Bit) Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) for the direct area to 1. ■ SETB (Set Direct Memory Bit) Operation (dir:b) ← 1 Assembler format SETB dir:b Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 4 Byte count: 2 OP code: A8 to AF 194 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETB 32H : 5 Memory Memory FFFFH A A T T IX IX 00X0 0000 0032H 0010 0000 0032H SP SP PC PC Byte 0000H Byte 0000H EP EP PS FFFFH 05 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 05 Byte Byte N Z V C 0 0 0 0 (After execution) 195 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.75 SETC (SET Carry flag) Set the C-flag to 1. ■ SETC (SET Carry flag) Operation (C) ← 1 Assembler format SETC Condition code (CCR) N Z V C - - - S +: Changed by executing instruction -: Not changed S: Set to 1 by executing instruction N: Not changed Z: Not changed V: Not changed C: Set to 1 Number of execution cycle: 1 Byte count: 1 OP code: 91 196 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETC Memory FFFFH A A T T IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 1 (After execution) 197 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.76 SETI (SET Interrupt flag) Set the I-flag to 1 (enable an interrupt). ■ SETI (SET Interrupt flag) Operation (I) ← 1 Assembler format SETI Condition code (CCR) I N Z V C S - - - - +: Changed by executing instruction -: Not changed S: Set to 1 by executing instruction I: Set to 1 N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 90 198 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETI Memory FFFFH A A T T IX IX SP SP PC PC Byte 0000H EP H PS 0 Byte I 0 Byte IL1 IL0 1 1 N 0 Z 0 V 0 (Before execution) FFFFH Byte 0000H EP C 1 Memory PS Byte H I 0 1 Byte IL1 IL0 1 1 N Z V C 0 0 0 1 (After execution) 199 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.77 SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L") Exchange the byte data of AH for that of AL. ■ SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L") Operation (AH) ↔ (AL) (Byte data exchange) Assembler format SWAP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 10 200 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SWAP Memory A 32 FFFFH AA A T T IX IX SP SP PC PC Byte AA Memory FFFFH Byte 0000H 32 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 201 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.78 XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L") Exchange the byte data of AL for that of TL. ■ XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L") Operation (AL) ↔ (TL) (conversion of byte data) Assembler format XCH A, T Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 42 202 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCH A, T Memory FFFFH A 32 AA A 32 79 T 55 79 T 55 AA IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 203 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.79 XCHW (eXCHange Word Data Accumulator and Extrapointer) Exchange the word data of A for that of EP. ■ XCHW (eXCHange Word Data Accumulator and Extrapointer) Operation (A) ↔ (EP) (conversion of word data) Assembler format XCHW A, EP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: F7 204 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, EP Memory A 32 FFFFH AA A T T IX IX SP SP PC PC Byte EP 55 Byte Byte 79 32 AA FFFFH Byte 0000H 0000H EP 79 PS 55 Memory N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 205 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.80 XCHW (eXCHange Word Data Accumulator and Index Register) Exchange the word data of A for that of IX. ■ XCHW (eXCHange Word Data Accumulator and Index Register) Operation (A) ↔ (IX) (conversion of word data) Assembler format XCHW A, IX Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: F6 206 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, IX Memory A 32 FFFFH AA A 79 32 AA FFFFH Byte 0000H T T IX 55 Memory 55 IX 79 SP SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 207 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.81 XCHW (eXCHange Word Data Accumulator and Program Counter) Exchange the word data of PC for that of A. ■ XCHW (eXCHange Word Data Accumulator and Program Counter) Operation (PC) ← (A) (word transfer) (A) ← (PC) +1 (word addition, word transfer) Assembler format XCHW A, PC Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 3 Byte count: 1 OP code: F4 208 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, PC Memory A F0 FFFFH C7 A T T IX IX SP SP PC F1 PC 79 Byte F1 7A F0 C7 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 209 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.82 XCHW (eXCHange Word Data Accumulator and Stack Pointer) Exchange the word data of A for that of SP. ■ XCHW (eXCHange Word Data Accumulator and Stack Pointer) Operation (A) ↔ (SP) (conversion of word data) Assembler format XCHW A, SP Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycles: 2 Byte count: 1 OP code: F5 210 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, SP Memory A 32 FFFFH AA A T T IX IX SP 55 SP 79 55 79 32 AA Memory FFFFH Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 211 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.83 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator) Exchange the word data of A for that of T. ■ XCHW (eXCHange Word Data Accumulator and Temporary Accumulator) Operation (A) ↔ (T) (conversion of word data) Assembler format XCHW A, T Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 43 212 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, T Memory FFFFH A 32 AA A 55 79 T 55 79 T 32 AA IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 213 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.84 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical exclusive-OR on the byte data of AL and TL for every bit and return the results to AL. The contents of AH are not changed. ■ XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Operation (AL) ← (AL) ∀ (TL) (byte logical exclusive-OR) Assembler format XOR A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 52 214 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XOR A Memory FFFFH A 76 23 A 76 62 T XX 41 T XX 41 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 215 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.85 XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator) Carry out the logical exclusive-OR for the byte data of AL and EA memory (memory expressed in each type of addressing) for every bit and return the results to AL. The contents of AH are not changed. ■ XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator) Operation (AL) ← (AL) ∀ (EA) (byte logical exclusive-OR) Assembler format XOR A, EA Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 00H and set to 0 in other cases. V: Always set to 0 C: Not changed Table 6.85-1 Number of Execution Cycles / Byte Count / OP Code EA 216 #d8 dir @IX+off @EP Ri Number of execution cycles 2 3 3 2 2 Byte count 2 2 2 1 1 OP code 54 55 56 57 58 to 5F CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XOR A, @EP Memory A 54 Memory FFFFH 32 A 20 T T IX IX 12 0122H SP SP PC PC Byte EP 54 FFFFH 01 PS Byte 0000H EP 22 Byte N Z V C 0 0 0 0 (Before execution) 01 0122H Byte 0000H 22 PS Byte 12 Byte N Z V C 0 0 0 0 (After execution) 217 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.86 XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator) Carry out the logical exclusive-OR on the word data of A and T for every bit and return the results to A. ■ XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator) Operation (A) ← (A) ∀ (T) (word logical exclusive-OR) Assembler format XORW A Condition code (CCR) N Z V C + + R - +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases. V: Always set to 0 C: Not changed Number of execution cycle: 1 Byte count: 1 OP code: 53 218 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XORW A Memory FFFFH A 57 23 A 64 62 T 33 41 T 33 41 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 219 CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 220 APPENDIX The appendix contains instruction and bus operation lists and an instruction map. APPENDIX A Instruction List APPENDIX B Bus Operation List APPENDIX C Instruction Map 221 APPENDIX APPENDIX A Instruction List Appendix A contains lists of instructions used in the assembler. A.1 F2MC-8FX CPU Instruction Overview A.2 Operation List A.3 Flag Change Table 222 APPENDIX A Instruction List A.1 F2MC-8FX CPU Instruction Overview This section explains the F2MC-8FX CPU instructions. ■ F2MC-8FX CPU Instruction Overview In the F2MC-8FX CPU, there is 140 kinds of one byte machine instruction (as the map, 256 bytes), and the instruction code is composed of the instruction and the operand following it. Figure A.1-1 shows the instruction code and the correspondence of the instruction map. Figure A.1-1 Correspondence between the Instruction Code and the Instruction Map 1 byte Instruction code Machine instruction Give 0 to 2 bytes according to the instruction. Operand [Instruction map] Lower 4 bits Upper 4 bits Operand The following are enumerated as a feature of F2MC-8FX CPU instruction. • The instruction is classified into 4 types: transfer, operation, branch, and others. • There is various methods of address specification, and ten kinds of addressing can be selected by the selection of the instruction and the operand specification. • It provides with the bit operation instruction, and the read modification write can operate. • There is an instruction that directs special operation. 223 APPENDIX ■ Sign of the Instruction List Table A.1-1 explains the sign used by describing the instruction code in the table. Table A.1-1 Sign of the Instruction List Notation Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir:b Bit direct address (8 bits: 3 bits) rel Relative branch address (8 bits) @ Register indirect (example: @A, @IX, @EP) A Accumulator (8-bit or 16-bit length is determined by instruction to be used.) AH Upper 8 bits of accumulator (8 bits) AL Lower 8 bits of accumulator (8 bits) T Temporary accumulator (8-bit or 16-bit length is determined by instruction to be used.) TH Upper 8 bits of temporary accumulator (8 bits) TL Lower 8 bits of temporary accumulator (8 bits) IX Index register (16 bits) EP Extra pointer (16 bits) PC Program counter (16 bits) SP Stack pointer (16 bits) PS Program status (16 bits) dr Accumulator or index register (16 bits) CCR Condition code register (8 bits) RP Register bank pointer (5 bits) DP Direct bank pointer (3 bits) Ri General-purpose register (8 bits, i = 0 to 7) X X indicates immediate data. (8-bit or 16-bit length is determined by instruction to be used.) (X) The contents of X are to be accessed. (8-bit or 16-bit length is determined by instruction to be used.) ((X)) The address indicated by the contents of X is to be accessed. (8-bit or 16-bit length is determined by instruction to be used.) 224 APPENDIX A Instruction List ■ Item in Instruction Table Table A.1-2 explains the item of instruction table. Table A.1-2 Item in Instruction Table Item Description NMEMONIC The assembly description of the instruction is shown. RD The read of an internal bus is shown. WR The write of an internal bus is shown. RMW The read modification write signal of an internal bus is shown. ~ Cycle of the instruction number is shown. One instruction cycle is one machine cycle. Note: The instruction cycle number might be postponed one cycle by the immediately preceding instruction. Moreover, cycle of the instruction number might be extended in the access to the IO area. # The number of bytes for the instruction is shown. Operation The operation of the instruction is shown. TL, TH, AH The change in the content when TL, TH, and AH each instruction is executed is shown. The sign in the column shows the following respectively. • - : Do not change. • dH : Upper 8 bits of the data written in operation • AL, AH : Become the contents of AL or AH immediately before instruction. • 00 : Become 00. N, Z, V, C The flag changed when each instruction is executed is shown. The sign in the column shows the following respectively. • - : Do not change. • + : Change. • R : Become 0. • S : Become 1. OP CODE The code of the instruction is shown. When a pertinent instruction occupies two or more codes, it follows the following description rules. 48 to 4F: 48, 49, ..., 4F are shown. 225 APPENDIX A.2 Operation List Table A.2-1 is the operation list for transfer instructions. Table A.2-2 is the operation list for operation instructions. Table A.2-3 is the operation list for branch instructions. Table A.2-4 is the operation list for other instructions. ■ Operation List Table A.2-1 Operation List (for Transfer Instructions) (1/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 1 MOV dir, A 3 2 (dir) ← (A) – – – –––– 45 2 MOV @IX+off, A 3 2 (IX)+off) ← (A) – – – –––– 46 3 MOV ext, A 4 3 (ext) ← (A) – – – –––– 61 4 MOV @EP, A 2 1 ((EP)) ← (A) – – – –––– 47 5 MOV Ri, A 2 1 (Ri) ← (A) – – – –––– 48 to 4F 6 MOV A, #d8 2 2 (A) ← d8 AL – – ++–– 04 7 MOV A, dir 3 2 (A) ← (dir) AL – – ++–– 05 8 MOV A, @IX+off 3 2 (A) ← ((IX)+off) AL – – ++–– 06 9 MOV A, ext 4 3 (A) ← (ext) AL – – ++–– 60 10 MOV A, @A 2 1 (A) ← ((A)) AL – – ++–– 92 11 MOV A, @EP 2 1 (A) ← ((EP)) AL – – ++–– 07 12 MOV A, Ri 2 1 (A) ← (Ri) AL – – ++–– 08 to 0F 13 MOV dir, #d8 4 3 (dir) ← d8 – – – –––– 85 14 MOV @IX+off, #d8 4 3 ((IX)+off) ← d8 – – – –––– 86 15 MOV @EP, #d8 3 2 ((EP)) ← d8 – – – –––– 87 16 MOV Ri, #d8 3 2 (Ri) ← d8 – – – –––– 88 to 8F 17 MOVW dir, A 4 2 (dir) ← (AH), (dir+1)←(AL) – – – –––– D5 18 MOVW @IX+off, A 4 2 ((IX)+off) ← (AH), ((IX)+off+1) ← (AL) – – – –––– D6 226 APPENDIX A Instruction List Table A.2-1 Operation List (for Transfer Instructions) (2/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 19 MOVW ext, A 5 3 (ext) ← (AH), (ext+1) ← (AL) – – – –––– D4 20 MOVW @EP, A 3 1 ((EP)) ← (AH), ((EP)+1) ← (AL) – – – –––– D7 21 MOVW EP, A 1 1 (EP) ← (A) – – – –––– E3 22 MOVW A, #d16 3 3 (A) ← d16 AL AH dH ++–– E4 23 MOVW A, dir 4 2 (AH) ← (dir), (AL) ← (dir+1) AL AH dH ++–– C5 24 MOVW A, @IX+off 4 2 (AH) ← ((IX)+off), (AL) ← ((IX)+off+1) AL AH dH ++–– C6 25 MOVW A, ext 5 3 (AH) ← (ext), (AL) ← (ext+1) AL AH dH ++–– C4 26 MOVW A, @A 3 1 (AH) ← ((A)), (AL) ← ((A)+1) AL AH dH ++–– 93 27 MOVW A, @EP 3 1 (AH) ← ((EP)), (AL) ← ((EP)+1) AL AH dH ++–– C7 28 MOVW A, EP 1 1 (A) ← (EP) – – dH –––– F3 29 MOVW EP, #d16 3 3 (EP) ← d16 – – – –––– E7 30 MOVW IX, A 1 1 (IX) ← (A) – – – –––– E2 31 MOVW A, IX 1 1 (A) ← (IX) – – dH –––– F2 32 MOVW SP, A 1 1 (SP) ← (A) – – – –––– E1 33 MOVW A, SP 1 1 (A) ← (SP) – – dH –––– F1 34 MOV @A, T 2 1 ((A)) ← (T) – – – –––– 82 35 MOVW @A, T 3 1 ((A)) ← (TH), ((A)+1) ← (TL) – – – –––– 83 36 MOVW IX, #d16 3 3 (IX) ← d16 – – – –––– E6 37 MOVW A, PS 1 1 (A) ← (PS) – – dH –––– 70 38 MOVW PS, A 1 1 (PS) ← (A) – – – ++++ 71 39 MOVW SP, #d16 3 3 (SP) ← d16 – – – –––– E5 40 SWAP 1 1 (AH) ↔ (AL) – – AL –––– 10 227 APPENDIX Table A.2-1 Operation List (for Transfer Instructions) (3/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 41 SETB dir:b 4 2 (dir):b ← 1 – – – –––– A8 to AF 42 CLRB dir:b 4 2 (dir):b ← 0 – – – –––– A0 to A7 43 XCH A, T 1 1 (AL) ↔ (TL) AL – – –––– 42 44 XCHW A, T 1 1 (A) ↔ (T) AL AH dH –––– 43 45 XCHW A, EP 1 1 (A) ↔ (EP) – – dH –––– F7 46 XCHW A, IX 1 1 (A) ↔ (IX) – – dH –––– F6 47 XCHW A, SP 1 1 (A) ↔ (SP) – – dH –––– F5 48 MOVW A, PC 2 1 (A) ← (PC) – – dH –––– F0 Notes: 1. In byte transfer to A, T ← A is only low bytes. 2. The operands of an instruction with two or more operands should be stored in the order designated in MNEMONIC. Table A.2-2 Operation List (for Operation Instructions) (1/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 1 ADDC A, Ri 2 1 (A) ← (A)+(Ri)+C – – – ++++ 28 to 2F 2 ADDC A, #d8 2 2 (A) ← (A)+d8+C – – – ++++ 24 3 ADDC A, dir 3 2 (A) ← (A)+(dir)+C – – – ++++ 25 4 ADDC A, @IX+off 3 2 (A) ← (A)+((IX)+off)+C – – – ++++ 26 5 ADDC A, @EP 2 1 (A) ← (A)+((EP))+C – – – ++++ 27 6 ADDCW A 1 1 (A) ← (A)+(T)+C – – dH ++++ 23 7 ADDC A 1 1 (AL) ← (AL)+(TL)+C – – – ++++ 22 8 SUBC A, Ri 2 1 (A) ← (A)-(Ri)-C – – – ++++ 38 to 3F 9 SUBC A, #d8 2 2 (A) ← (A)-d8-C – – – ++++ 34 10 SUBC A, dir 3 2 (A) ← (A)-(dir)-C – – – ++++ 35 11 SUBC A, @IX+off 3 2 (A) ← (A)-((IX)+off)-C – – – ++++ 36 12 SUBC A, @EP 2 1 (A) ← (A)-((EP))-C – – – ++++ 37 13 SUBCW A 1 1 (A) ← (T)-(A)-C – – dH ++++ 33 14 SUBC 1 1 (AL) ← (TL)-(AL)-C – – – ++++ 32 228 A APPENDIX A Instruction List Table A.2-2 Operation List (for Operation Instructions) (2/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 15 IINC Ri 3 1 (Ri) ← (Ri)+1 – – – +++– C8 to CF 16 INCW EP 1 1 (EP) ← (EP)+1 – – – –––– C3 17 INCW IX 1 1 (IX) ← (IX)+1 – – – –––– C2 18 INCW A 1 1 (A) ← (A)+1 – – dH ++–– C0 19 DEC Ri 3 1 (Ri) ← (Ri)-1 – – – +++– D8 to DF 20 DECW EP 1 1 (EP) ← (EP)-1 – – – –––– D3 21 DECW IX 1 1 (IX) ← (IX)-1 – – – –––– D2 22 DECW A 1 1 (A) ← (A)-1 – – dH ++–– D0 23 MULU A 8 1 (A) ← (AL)*(TL) – – dH –––– 01 24 DIVU A 17 1 (A) ← (T)/(A), MOD → (T) dL dH dH –+–– 11 25 ANDW A 1 1 (A) ← (A) ^ (T) – – dH ++R– 63 26 ORW A 1 1 (A) ← (A) ∨ (T) – – dH ++R– 73 27 XORW A 1 1 (A) ← (A) ∀ (T) – – dH ++R– 53 28 CMP A 1 1 (TL)-(AL) – – – ++++ 12 29 CMPW A 1 1 (T)- (A) – – – ++++ 13 30 RORC A 1 1 – – – ++–+ 03 31 ROLC A 1 1 – – – ++–+ 02 32 CMP A, #d8 2 2 (A)- d8 – – – ++++ 14 33 CMP A, dir 3 2 (A)- (dir) – – – ++++ 15 34 CMP A, @EP 2 1 (A)- ((EP)) – – – ++++ 17 35 CMP A, @IX+off 3 2 (A)- ((IX)+off) – – – ++++ 16 36 CMP A, Ri 2 1 (A)- (Ri) – – – ++++ 18 to 1F 37 DAA 1 1 decimal adjust for addition – – – ++++ 84 C→A C←A 229 APPENDIX Table A.2-2 Operation List (for Operation Instructions) (3/3) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 38 DAS 1 1 decimal adjust for subtraction – – – ++++ 94 39 XOR A 1 1 (A) ← (AL) ∀ (TL) – – – ++R– 52 40 XOR A, #d8 2 2 (A) ← (AL) ∀ d8 – – – ++R– 54 41 XOR A, dir 3 2 (A) ← (AL) ∀ (dir) – – – ++R– 55 42 XOR A, @EP 3 1 (A) ← (AL) ∀ ((EP)) – – – ++R– 57 43 XOR A, @IX+off 4 2 (A) ← (AL) ∀ ((IX)+off) – – – ++R– 56 44 XOR A, Ri 2 1 (A) ← (AL) ∀ (Ri) – – – ++R– 58 to 5F 45 AND A 1 1 (A) ← (AL) ^ (TL) – – – ++R– 62 46 AND A, #d8 2 2 (A) ← (AL) ^ d8 – – – ++R– 64 47 AND A, dir 3 2 (A) ← (AL) ^ (dir) – – – ++R– 65 48 AND A, @EP 2 1 (A) ← (AL) ^ ((EP)) – – – ++R– 67 49 AND A, @IX+off 3 2 (A) ← (AL) ^ ((IX)+off) – – – ++R– 66 50 AND A, Ri 2 1 (A) ← (AL) ^ (Ri) – – – ++R– 68 to 6F 51 OR A 1 1 (A) ← (AL) ∨ (TL) – – – ++R– 72 52 OR A, #d8 2 2 (A) ← (AL) ∨ d8 – – – ++R– 74 53 OR A, dir 3 2 (A) ← (AL) ∨ (dir) – – – ++R– 75 54 OR A,@EP 2 1 (A) ← (AL) ∨ ((EP)) – – – ++R– 77 55 OR A, @IX,off 3 2 (A) ← (AL) ∨ ((IX)+off) – – – ++R– 76 56 OR A, Ri 2 1 (A) ← (AL) ∨ (Ri) – – – ++R– 78 to 7F 57 CMP dir, #d8 4 3 (dir) - d8 – – – ++++ 95 58 CMP @EP, #d8 3 2 ((EP))- d8 – – – ++++ 97 59 CMP @IX+off, #d8 4 3 ((IX)+off) - d8 – – – ++++ 96 60 CMP Ri, #d8 3 2 (Ri) - d8 – – – –––– 98 to 9F 61 INCW SP 1 1 (SP) ← (SP) + 1 – – – –––– C1 62 DECW SP 1 1 (SP) ← (SP) - 1 – – – –––– D1 230 APPENDIX A Instruction List Table A.2-3 Operation List (for Branch Instructions) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 1 BZ/BEQ rel (divergence) (no divergence) 4 2 2 if Z=1 then PC ← PC+rel – – – –––– FD 2 BNZ/BNE rel (divergence) (no divergence) 4 2 2 if Z=0 then PC ← PC+rel – – – –––– FC 3 BC/BLO rel (divergence) (no divergence) 4 2 2 if C=1 then PC ← PC+rel – – – –––– F9 4 BNC/BHS rel (divergence) (no divergence) 4 2 2 if C=0 then PC ← PC+rel – – – –––– F8 5 BN rel (divergence) (no divergence) 4 2 2 if N=1 then PC ← PC+rel – – – –––– FB 6 BP rel (divergence) (no divergence) 4 2 2 if N=0 then PC ← PC+rel – – – –––– FA 7 BLT rel (divergence) (no divergence) 4 2 2 if V ∀ N=1 then PC ← PC+rel – – – –––– FF 8 BGE rel (divergence) (no divergence) 4 2 2 if V ∀ N=0 then PC ← PC+rel – – – –––– FE 9 BBC dir:b, rel 5 3 if (dir:b)=0 then PC ← PC+rel – – – –+–– B0 to B7 10 BBS dir:b, rel 5 3 if (dir:b)=1 then PC ← PC+rel – – – –+–– B8 to BF 11 JMP @A 3 1 (PC) ← (A) – – – –––– E0 12 JMP ext 4 3 (PC) ← ext – – – –––– 21 13 CALLV #vct 7 1 vector call – – – –––– E8 to EF 14 CALL ext 6 3 subroutine call – – – –––– 31 15 XCHW A, PC 3 1 (PC) ← (A), (A) ← (PC)+1 – – dH –––– F4 16 RET 6 1 return from subroutine – – – –––– 20 17 RETI 8 1 return from interrupt – – – restore 30 231 APPENDIX Table A.2-4 Operation List (for Other Instructions) No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE 1 PUSHW A 4 1 (SP) ← (SP)-2, ((SP)) ← (A) – – – –––– 40 2 POPW A 3 1 (A) ← ((SP)), (SP ) ← (SP)+2 – – dH –––– 50 3 PUSHW IX 4 1 (SP) ← (SP)-2, ((SP)) ← (IX) – – – –––– 41 4 POPW IX 3 1 (IX) ← ((SP)), (SP) ← (SP)+2 – – – –––– 51 5 NOP 1 1 No operation – – – –––– 00 6 CLRC 1 1 (C) ← 0 – – – –––R 81 7 SETC 1 1 (C) ← 1 – – – –––S 91 8 CLRI 1 1 (I) ← 0 – – – –––– 80 9 SETI 1 1 (I) ← 1 – – – –––– 90 232 APPENDIX A Instruction List A.3 Flag Change Table Table A.3-1 is the flag change table for transfer instructions. Table A.3-2 is the flag change table for operation instructions. Table A.3-3 is the flag change table for branch instructions. Table A.3-4 is the flag change table for other instructions. ■ Flag Change Table Table A.3-1 Flag Change Table (for Transfer Instructions) (1/2) Instruction Flag change MOV dir, A N: Not changed MOV @IX+off, A Z: Not changed MOV ext, A V: Not changed MOV @EP, A C: Not changed MOV Ri, A MOV , #d8 N: Set to 1 if the transferred data is negative and set to 0 in other cases. MOV A, dir Z: Set to 1 if the transferred data is 0 and set to 0 in other cases MOV A, @IX+off V: Not changed MOV A, ext C: Not changed MOV A, @A MOV A, @EP MOV A, Ri MOV dir, #d8 N: Not changed MOV @IX+off, #d8 Z: Not changed MOV @EP, #d8 V: Not changed MOV Ri, #d8 C: Not changed MOVW dir, A N: Not changed MOVW @IX+off, A Z: Not changed MOVW ext, A V: Not changed MOVW @EP, A C: Not changed MOVW A, #d16 N: Set to 1 if the transferred data is negative and set to 0 in other cases. MOVW A, dir Z: Set to 1 if the transferred data is 0 and set to 0 in other cases MOVW A, @IX+off V: Not changed MOVW A, ext C: Not changed MOVW A, @A MOVW A, @EP 233 APPENDIX Table A.3-1 Flag Change Table (for Transfer Instructions) (2/2) Instruction Flag change MOVW A, EP N: Not changed MOVW EP, #d16 Z: Not changed MOVW IX, A V: Not changed MOVW A, IX C: Not changed MOVW SP, A MOVW A, SP MOVW SP, #d16 MOV @A, T N: Not changed MOVW @A, T Z: Not changed V: Not changed C: Not changed MOVW IX, #d16 N: Not changed MOVW A, PS Z: Not changed MOVW A, PC V: Not changed JMP @A C: Not changed MOVW PS, A N: Set to 1 if bit 3 of A is 1 and set to 0 if 0. Z: Set to 1 if bit 2 of A is 1 and set to 0 if 0. V: Set to 1 if bit 1 of A is 1 and set to 0 if 0. C: Set to 1 if bit 0 of A is 1 and set to 0 if 0. SETB dir:b N: Not changed CLRB dir:b Z: Not changed V: Not changed C: Not changed SWAP N: Not changed XCH A, T Z: Not changed V: Not changed C: Not changed XCHW A, T N: Not changed XCHW A, EP Z: Not changed XCHW A, IX V: Not changed XCHW A, SP C: Not changed XCHW A, PC 234 APPENDIX A Instruction List Table A.3-2 Flag Change Table (for Operation Instructions) (1/3) Instruction Flag change ADDC A, Ri N: Set to 1 if the result of operation is negative and set to 0 in other cases. ADDC A, #d8 Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. ADDC A, dir V: Set to 1 if an overflow occurs and set to 0 in other cases. ADDC A, @IX+off C: Set to 1 if a carry occurs and set to 0 in other cases. ADDC A, @EP ADDC A N: Set to 1 if the result of operation is negative and set to 0 in other cases. ADDCW A Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Set to 1 if a carry occurs and set to 0 in other cases. SUBC A, Ri N: Set to 1 if the result of operation is negative and set to 0 in other cases. SUBC A, #d8 Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. SUBC A, dir V: Set to 1 if an overflow occurs and set to 0 in other cases. SUBC A, @IX+off C: Set to 1 if a borrow occurs and set to 0 in other cases. SUBC A, @EP SUBC A N: Set to 1 if the result of operation is negative and set to 0 in other cases. SUBCW A Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Set to 1 if a borrow occurs and set to 0 in other cases. INC Ri N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Not changed INCW EP N: Not changed INCW IX Z: Not changed INCW SP V: Not changed C: Not changed INCW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Not changed C: Not changed DEC Ri N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Not changed 235 APPENDIX Table A.3-2 Flag Change Table (for Operation Instructions) (2/3) Instruction Flag change DECW EP N: Not changed DECW IX Z: Not changed DECW SP V: Not changed C: Not changed DECW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Not changed C: Not changed MULU A N: Not changed Z: Not changed V: Not changed C: Not changed DIVU A N: Not changed Z: Set to 1 if A before operation is 0000H and set to 0 in other cases. V: Not changed C: Not changed ANDW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Always Set to 0 C: Not changed AND A, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. AND A, dir Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. AND A, @EP V: Always set to 0 AND A, @IX+off C: Not changed AND A, Ri ORW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Always set to 0 C: Not changed OR A, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. OR A, dir Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. OR A, @EP V: Always set to 0 OR A, @IX+off C: Not changed OR A, Ri 236 APPENDIX A Instruction List Table A.3-2 Flag Change Table (for Operation Instructions) (3/3) Instruction XORW A Flag change N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Always set to 0 C: Not changed XOR A, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. XOR A, dir Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. XOR A, @EP V: Always set to 0 XOR A, @IX+off C: Not changed XOR A, Ri CMP A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Set to 1 if a borrow occurs and set to 0 in other cases. CMPW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Set to 1 if a borrow occurs and set to 0 in other cases. CMP A, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. CMP A, dir Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. CMP A, @EP V: Set to 1 if an overflow occurs and set to 0 in other cases. CMP A, @IX+off C: Set to 1 if a borrow occurs and set to 0 in other cases. CMP A, Ri CMP dir, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. CMP @EP #d8 Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. CMP @IX+off, #d8 V: Set to 1 if an overflow occurs and set to 0 in other cases. CMP Ri, #d8 C: Set to 1 if a borrow occurs and set to 0 in other cases. RORC A N: Set to 1 if the result of operation is negative and set to 0 in other cases. ROLC A Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Not changed C: Enter bit 0 (when RORA) or bit 7 (when ROLA) of A before the operation. DAA N: Set to 1 if the result of operation is negative and set to 0 in other cases. DAS Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Set to 1 if an overflow occurs and set to 0 in other cases. C: Set to 1 if a carry (borrow) occurs and set to 0 in other cases. 237 APPENDIX Table A.3-3 Flag Change Table (for Branch Instructions) Instruction Flag change BZ rel/BEQ rel N: Not changed BNZ rel/BNE rel Z: Not changed BC rel/BLO rel V: Not changed BNC rel/BHS rel C: Not changed BN rel BP rel BLT rel BGE rel JMP addr16 N: Not changed Z: Not changed V: Not changed C: Not changed BBC dir:b, rel N: Not changed BBS dir:b, rel Z: Set to 1 if bit b is 0 and set to 0 if 1. V: Not changed C: Not changed CALL addr16 N: Not changed CALLV #vct Z: Not changed RET V: Not changed C: Not changed RETI N: N value of saved CCR is entered. Z: Z value of saved CCR is entered. V: V value of saved CCR is entered. C: C value of saved CCR is entered. 238 APPENDIX A Instruction List Table A.3-4 Flag Change Table (for Other Instructions) Instruction Flag change PUSHW A N: Not changed PUSHW IX Z: Not changed V: Not changed C: Not changed POPW A N: Not changed POPW IX Z: Not changed V: Not changed C: Not changed NOP N: Not changed Z: Not changed V: Not changed C: Not changed CLRC N: Not changed Z: Not changed V: Not changed C: Become to 0 SETC N: Not changed Z: Not changed V: Not changed C: Become to 1 CLRI N: Not changed Z: Not changed V: Not changed C: Not changed I: Become to 0 SETI N: Not changed Z: Not changed V: Not changed C: Not changed I: Become to 1 239 APPENDIX APPENDIX B Bus Operation List Table B-1 is a bus operation list. ■ Bus Operation List Table B-1 Bus Operation List (1/11) CODE 240 MNEMONIC 00 NOP 80 CLRI 90 SETI 81 CLRC 91 SETC 10 SWAP 12 CMP A 22 ADDC A 32 SUBC A 42 XCH A, T 52 XOR A 62 AND A 72 OR 13 CMPW A 23 ADDCW A 33 SUBCW A 43 XCHW A, T 53 XORW A 63 ANDW A 73 ORW 04 MOV A, #d8 14 CMP A, #d8 24 ADDC A, #d8 34 SUBC A, #d8 54 XOR A, #d8 64 AND A, #d8 74 OR ~ Cycle 1 1 1 Address bus Data bus RD WR RMW N +2 The following following instruction 1 0 0 1 N +2 The following following instruction 1 0 0 1 1 N +2 The following following instruction 1 0 0 2 1 N +2 The following instruction 1 0 0 2 N +3 The following following instruction 1 0 0 A A A, #d8 APPENDIX B Bus Operation List Table B-1 Bus Operation List (2/11) CODE MNEMONIC ~ Cycle Address bus 3 1 N +2 Data bus RD WR RMW The following instruction 1 0 0 05 MOV A, dir 15 CMP A, dir 2 dir address Data 1 0 0 25 ADDC A, dir 3 N +3 1 0 0 35 SUBC A, dir The following following instruction 55 XOR A, dir 65 AND A, dir 75 OR 45 MOV dir, A 1 N +2 The following instruction 1 0 0 2 dir address Data 0 1 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 A, dir 3 06 MOV A, @IX+off 3 16 CMP A, @IX+off 2 N +3 The following following instruction 1 0 0 26 ADDC A, @IX+off 3 (IX)+off address Data 1 0 0 36 SUBC A, @IX+off 56 XOR A, @IX+off 66 AND A, @IX+off 76 OR 46 MOV @IX+off, A 1 N +2 The following instruction 1 0 0 2 N +3 The following following instruction 1 0 0 3 (IX)+off address Data 0 1 0 1 N +2 The following following instruction 1 0 0 2 (EP) address Data 1 0 0 1 N +2 The following following instruction 1 0 0 2 (EP) address Data 0 1 0 A, @IX+off 07 MOV A, @EP 17 CMP A, @EP 27 ADDC A, @EP 37 SUBC A, @EP 57 XOR A, @EP 67 AND A, @EP 77 OR 47 MOV @EP, A 3 2 A, @EP 2 241 APPENDIX Table B-1 Bus Operation List (3/11) CODE MNEMONIC 08 - 0F MOV A, Ri 18 - 1F CMP A, Ri 28 - 2F ADDC A, Ri 38 - 3F SUBC A, Ri 58 - 5F XOR A, Ri 68 - 6F AND A, Ri 78 - 7F OR 48 - 4F MOV Ri, A 242 ~ Cycle 2 1 Address bus Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 Rn address Data 1 0 0 1 N +2 The following following instruction 1 0 0 2 Rn address Data 0 1 0 1 1 N +2 The following following instruction 1 0 0 2 1 N +2 The following following instruction 1 0 0 2 − − 0 0 0 1 1 N +2 The following following instruction 1 0 0 3 1 N +2 Data of N +2 1 0 0 2 Address divergence The following instruction 1 0 0 3 Address divergence +1 The following following instruction 1 0 0 1 N +2 The following following instruction 1 0 0 A, Ri C0 INCW A D0 DECW A C1 INCW SP D1 DECW SP C2 INCW IX D2 DECW IX C3 INCW EP D3 DECW EP F0 MOVW A, PC E1 MOVW SP, A F1 MOVW A, SP E2 MOVW IX, A F2 MOVW A, IX E3 MOVW EP, A F3 MOVW A, EP E0 JMP @A F5 XCHW A, SP F6 XCHW A, IX F7 XCHW A, EP 2 1 APPENDIX B Bus Operation List Table B-1 Bus Operation List (4/11) CODE F4 MNEMONIC XCHW A, PC A0 - A7 CLRB dir:n A8 - AF SETB dir:n B0 - B7 BBC dir:n, rel B8 - BF BBS dir:n, rel ~ Cycle 3 1 N +2 2 4 Address bus Data bus RD WR RMW Data of N +2 1 0 0 Address divergence The following instruction 1 0 0 3 Address divergence +1 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 1 2 dir address Data 1 0 1 3 dir address Data 0 1 0 4 N +3 The following following instruction 1 0 0 1 N +2 rel 1 0 0 2 dir address Data 1 0 0 3 N +3 Data of N+3 1 0 0 4 Address divergence The following instruction 1 0 0 5 Address divergence +1 The following following instruction 1 0 0 1 N +2 rel 1 0 0 2 dir address Data 1 0 0 3 N +3 The following instruction 1 0 0 4 − − 0 0 0 5 N +4 The following following instruction 1 0 0 1 N +2 ext (L byte) 1 0 0 2 N +3 The following instruction 1 0 0 3 ext address Data 1 0 0 4 N +4 The following following instruction 1 0 0 1 N +2 ext (L byte) 1 0 0 2 N +3 The following instruction 1 0 0 3 ext address Data 0 1 0 4 N +4 The following following instruction 1 0 0 Divergence 5 No divergence 5 60 61 MOV A, ext MOV ext, A 4 4 243 APPENDIX Table B-1 Bus Operation List (5/11) CODE C4 D4 C5 D5 C6 D6 244 MNEMONIC MOVW A, ext MOVW ext, A MOVW A, dir MOVW dir, A MOVW A, @IX+off MOVW @IX+off, A ~ Cycle 5 1 N +2 2 5 4 4 4 4 Address bus Data bus RD WR RMW ext (L byte) 1 0 0 N +3 The following instruction 1 0 0 3 ext address Data (H byte) 1 0 0 4 ext+1 address Data (L byte) 1 0 0 5 N +4 The following following instruction 1 0 0 1 N +2 ext (L byte) 1 0 0 2 N +3 The following instruction 1 0 0 3 ext address Data (H byte) 0 1 0 4 ext+1 address Data (L byte) 0 1 0 5 N +4 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 dir address Data (H byte) 1 0 0 3 dir+1 address Data (L byte) 1 0 0 4 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 dir address Data (H byte) 0 1 0 3 dir+1 address Data (L byte) 0 1 0 4 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 N +3 The following following instruction 1 0 0 3 (IX)+off address Data (H byte) 1 0 0 4 (IX)+off+1 address Data (L byte) 1 0 0 1 N +2 The following instruction 1 0 0 2 N +3 The following following instruction 1 0 0 3 (IX)+off address Data (H byte) 0 1 0 4 (IX)+off+1 address Data (L byte) 0 1 0 APPENDIX B Bus Operation List Table B-1 Bus Operation List (6/11) CODE C7 D7 85 95 86 96 MNEMONIC ~ Cycle MOVW A, @EP 3 1 MOVW @EP, A MOV dir, #d8 CMP dir, #d8 MOV @IX+off, #d8 CMP @IX+off, #d8 3 4 4 4 4 Address bus Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 (EP) address Data(H byte) 1 0 0 3 (EP)+1 address Data(L byte) 1 0 0 1 N +2 The following following instruction 1 0 0 2 (EP) address Data(H byte) 0 1 0 3 (EP)+1 address Data(L byte) 0 1 0 1 N +2 #d8 1 0 0 2 dir address Data 0 1 0 3 N +3 The following instruction 1 0 0 4 N +4 The following following instruction 1 0 0 1 N +2 #d8 1 0 0 2 dir address Data 1 0 0 3 N +3 The following instruction 1 0 0 1 N +2 #d8 1 0 0 2 N +3 The following instruction 1 0 0 3 (IX)+off address Data 0 1 0 4 N +4 The following following instruction 1 0 0 1 N +2 #d8 1 0 0 2 N +3 The following instruction 1 0 0 3 (IX)+off address Data 1 0 0 4 N +4 The following following instruction 1 0 0 245 APPENDIX Table B-1 Bus Operation List (7/11) CODE 87 97 88 - 8F 98 - 9F 82 92 83 246 MNEMONIC ~ Cycle MOV @EP, #d8 3 1 N +2 2 CMP @EP, #d8 MOV Ri, #d8 CMP Ri, #d8 MOV @A, T MOV A, @A MOVW @A, T 3 3 3 2 2 3 Address bus Data bus RD WR RMW The following instruction 1 0 0 (EP) address Data 0 1 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 (EP) address Data 1 0 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 Rn address Data 0 1 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 Rn address Data 1 0 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following following instruction 1 0 0 2 (A) address Data 0 1 0 1 N +2 The following following instruction 1 0 0 2 (A) address Data 1 0 0 1 N +2 The following following instruction 1 0 0 2 (A) address Data (H byte) 0 1 0 3 (A) +1 address Data (L byte) 0 1 0 APPENDIX B Bus Operation List Table B-1 Bus Operation List (8/11) CODE 93 MNEMONIC MOVW A, @A ~ Cycle 3 1 Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 (A) address Data (H byte) 1 0 0 3 (A) +1 address Data (L byte) 1 0 0 1 N +2 Data (L byte) 1 0 0 E4 MOVW A, #d16 E5 MOVW SP, #d16 2 N +3 The following instruction 1 0 0 E6 MOVW IX, #d16 3 N +4 The following following instruction 1 0 0 E7 MOVW EP, #d16 84 DAA 1 1 N +2 The following following instruction 1 0 0 94 DAS 02 ROLC A 03 RORC A 70 MOVW A, PS 71 MOVW PS, A 3 1 N +2 The following following instruction 1 0 1 2 Rn address Data 1 0 1 3 Rn address Data 0 1 0 1 N +2 Data of N +2 1 0 0 2 Vector address Vector (H) 1 0 0 3 Vector address +1 Vector (L) 1 0 0 4 SP -1 Return address (L) 0 1 0 5 SP -2 Return address (H) 0 1 0 6 Address divergence ahead The following instruction 1 0 0 7 Address divergence ahead +1 The following following instruction 1 0 0 C8 - CF INC Ri D8 - DF DEC Ri E8 - EF CALLV #n 3 Address bus 7 247 APPENDIX Table B-1 Bus Operation List (9/11) CODE F8 BNC rel F9 BC rel FA ~ Cycle Address bus Data bus RD WR RMW Divergence 1 N +2 Data of N +2 1 0 0 BP rel 2 N +3 Data of N +3 1 0 0 FB BN rel 3 Address divergence ahead The following instruction 1 0 0 FC BNZ rel 4 Address divergence ahead +1 The following following instruction 1 0 0 FD BZ rel FE BGE rel 1 N +2 The following instruction 1 0 0 FF BLT rel 2 N +3 The following following instruction 1 0 0 40 PUSHW A 1 N +2 The following following instruction 1 0 0 41 PUSHW IX 2 − − 0 0 0 3 SP -1 Save data (L) 0 1 0 4 SP -2 Save data (H) 0 1 0 1 N +2 The following following instruction 1 0 0 2 SP Return data (H) 1 0 0 3 SP +1 Return data (L) 1 0 0 1 N +2 Data of N +2 1 0 0 2 SP Return address (H) 1 0 0 3 SP +1 Return address (L) 1 0 0 4 − − 0 0 0 5 Return address The following instruction 1 0 0 6 Return address +1 The following following instruction 1 0 0 1 N +2 Data of N +2 1 0 0 2 SP PSH (RP, DP) 1 0 0 3 SP +1 PSL (CCR) 1 0 0 4 SP +2 Return address (H) 1 0 0 5 SP +3 Return address (L) 1 0 0 6 − − 0 0 0 7 Return address The following instruction 1 0 0 8 Return address +1 The following following instruction 1 0 0 50 POPW A 51 POPW IX 20 30 248 MNEMONIC RET RETI 4 No divergence 2 4 3 6 8 APPENDIX B Bus Operation List Table B-1 Bus Operation List (10/11) CODE 31 21 01 MNEMONIC CALL ext JMP ext MULU A ~ Cycle 6 1 4 8 Address bus Data bus RD WR RMW N +2 Address divergence ahead (L) 1 0 0 2 − − 0 0 0 3 SP -1 Return address (L) 0 1 0 4 SP -2 Return address (H) 0 1 0 5 Address divergence ahead The following instruction 1 0 0 6 Address divergence ahead +1 The following following instruction 1 0 0 1 N +2 Address divergence ahead (L) 1 0 0 2 − − 0 0 0 3 Address divergence ahead The following instruction 1 0 0 4 Address divergence ahead +1 The following following instruction 1 0 0 1 N +2 The following following instruction 1 0 0 2 − − 0 0 0 8 − − 0 0 0 1 N +2 The following following instruction 1 0 0 2 − − 0 0 0 17 − − 0 0 0 1 − − 0 0 0 2 0FFFDH Mode data 1 0 0 3 0FFFEH Reset vector (H) 1 0 0 4 0FFFFH Reset vector (L) 1 0 0 5 − − 0 0 0 6 Start address The following instruction 1 0 0 7 Start address +1 The following following instruction 1 0 0 to 11 DIVU A 17 to − RESET 7 249 APPENDIX Table B-1 Bus Operation List (11/11) CODE − MNEMONIC INTERRUPT ~ Cycle Address bus 9 1 N +2 2 Data bus RD WR RMW Data of N +2 1 0 0 Vector address Vector (H) 1 0 0 3 Vector address +1 Vector (L) 1 0 0 4 SP -1 Return address (L) 0 1 0 5 SP -2 Return address (H) 0 1 0 6 SP -3 PSL (CCR) 0 1 0 7 SP -4 PSH (RP, DP) 0 1 0 8 Address divergence ahead The following instruction 1 0 0 9 Address divergence ahead +1 The following following instruction 1 0 0 -: Invalid bus cycle N: Address where instruction under execution is stored Note: The cycle of the instruction might be extended by the immediately preceding instruction by one cycle. Moreover, cycle of the instruction number might be extended in the access to the IO area. 250 APPENDIX C Instruction Map APPENDIX C Instruction Map Table C-1 is an instruction map. ■ Instruction Map Table C-1 Instruction Map 251 APPENDIX 252 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 253 INDEX Index Symbols A #imm Immediate Addressing (#imm) ............................ 41 #k Vector Addressing (#k)....................................... 42 @EP Pointer Addressing (@EP) .................................. 41 @IX+off Index Addressing (@IX+off)............................... 41 A Numerics 16-bit Data Arrangement of 16-bit Data in Memory Space ...... 13 Accumulator (A)................................................ 18 Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 Accumulator Accumulator (A)................................................ 18 Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 ADDC ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) ................... 50 ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator) ....................................... 48 ADDCW ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator) ....................................... 52 Addressing Memory Space and Addressing ............................. 7 AND AND (AND Byte Data of Accumulator and Memory to Accumulator).................................... 56 AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) ........................................................... 54 ANDW ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) ........................................................... 58 B BBC BBC (Branch if Bit is Clear) ............................... 60 BBS BBS (Branch if Bit is Set)................................... 62 BC BC (Branch relative if C=1)/BLO (Branch if LOwer) ........................................................... 64 BEQ BZ (Branch relative if Z=1)/BEQ (Branch if Equal) ........................................................... 78 BGE BGE (Branch Great or Equal: relative if larger than or equal to Zero) ....................................... 66 254 INDEX BHS BNC (Branch relative if C=0)/BHS (Branch if Higher or Same) .............................................. 74 Bit Direct Addressing Bit Direct Addressing (dir:b) ............................... 40 BLO BC (Branch relative if C=1)/BLO (Branch if LOwer) ............................................................ 64 BLT BLT (Branch Less Than zero: relative if < Zero) ............................................................ 68 BN BN (Branch relative if N=1)................................ 70 BNC BNC (Branch relative if C=0)/BHS (Branch if Higher or Same) .............................................. 74 BNE BNZ (Branch relative if Z=0)/BNE (Branch if Not Equal) .................................................. 72 BNZ BNZ (Branch relative if Z=0)/BNE (Branch if Not Equal) .................................................. 72 BP BP (Branch relative if N=0: PLUS)...................... 76 Bus Operation Bus Operation List ........................................... 240 Byte Data Processing Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 BZ BZ (Branch relative if Z=1)/BEQ (Branch if Equal) ............................................................ 78 C CALL CALL (CALL subroutine) .................................. 80 CALLV CALLV #k ........................................................ 45 CALLV (CALL Vectored subroutine).................. 82 CLRB CLRB (Clear direct Memory Bit) ........................ 84 CLRC CLRC (Clear Carry flag) .................................... 86 CLRI CLRI (CLeaR Interrupt flag) ............................... 88 CMP CMP (CoMPare Byte Data of Accumulator and Memory) .............................................. 92 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator)....................... 90 CMP (CoMPare Byte Data of Immediate Data and Memory) .............................................. 94 CMPW CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) .......................96 CPU Configuration Example of Device Using F2MC-8FX CPU .......................................................3 F2MC-8FX CPU Features......................................2 F2MC-8FX CPU Instruction Overview ...............223 Outline of F2MC-8FX CPU ...................................2 D DAA DAA (Decimal Adjust for Addition).....................98 DAS DAS (Decimal Adjust for Subtraction) ...............100 DEC DEC (DECrement Byte Data of General-purpose Register) .............................................102 DECW DECW (DECrement Word Data of Accumulator) ..........................................................104 DECW (DECrement Word Data of Extra Pointer) ..........................................................106 DECW (DECrement Word Data of Index Pointer) ..........................................................108 DECW (DECrement Word Data of Stack Pointer) ..........................................................110 Dedicated Register F2MC-8FX Dedicated Registers...........................16 dir Direct Addressing (dir)........................................40 dir:b Bit Direct Addressing (dir:b) ...............................40 Direct Addressing Direct Addressing (dir)........................................40 Direct Area Direct Area ........................................................10 Direct Bank Direct Bank........................................................28 Direct Bank Pointer Access to Register Bank Pointer and Direct Bank Pointer..................................................25 Direct Data Transfer Direct Data Transfer from Temporary Accumulator (T)........................................................22 DIVU DIVU (DIVide Unsigned) .................................112 DIVU A.............................................................44 E EP Extra Pointer (EP)...............................................26 255 INDEX ext Extended Addressing (ext) .................................. 40 Extended Addressing Extended Addressing (ext) .................................. 40 Extra Pointer Extra Pointer (EP) .............................................. 26 F Flag Program Status (PS) Flags................................... 24 Flag Change Flag Change Table ........................................... 233 G General-Purpose Register F2MC-8FX General-Purpose Registers................. 16 General-Purpose Register Addressing General-Purpose Register Addressing (Ri)............ 41 General-Purpose Register Bank Area General-Purpose Register Bank Area ..................... 9 I Immediate Addressing Immediate Addressing (#imm) ............................ 41 INC INC (INCrement Byte Data of General-purpose Register)............................................. 114 INCW INCW (INCrement Word Data of Accumulator) .......................................................... 116 INCW (INCrement Word Data of Extra Pointer) .......................................................... 118 INCW (INCrement Word Data of Index Register) .......................................................... 120 INCW (INCrement Word Data of Stack Pointer) .......................................................... 122 Index Addressing Index Addressing (@IX+off)............................... 41 Index Register Index Register (IX)............................................. 26 Inherent Addressing Inherent Addressing............................................ 42 Instruction F2MC-8FX CPU Instruction Overview............... 223 Instruction List Sign of the Instruction List ................................ 224 Instruction Map Instruction Map................................................ 251 Instruction Table Item in Instruction Table ................................... 225 Interrupt Creating an Interrupt Processing Program ............. 34 256 Interrupt Enable/Disable Functions ...................... 32 Interrupt Requests in Resources........................... 32 Multiple Interrupt............................................... 36 Outline of Interrupt Operation ............................. 30 Reset and Interrupt Vector Table ......................... 11 Item Item in Instruction Table................................... 225 IX Index Register (IX) ............................................ 26 J JMP JMP (JuMP to address pointed by Accumulator) ......................................................... 124 JMP (JuMP to effective Address) ...................... 126 JMP @A ........................................................... 43 M Memory Space Arrangement of 16-bit Data in Memory Space ...... 13 CPU Memory Space............................................. 6 Memory Space and Addressing ............................. 7 MOV MOV (MOVE Byte Data from Accumulator to memory) ............................................ 134 MOV (MOVE Byte Data from Memory to Accumulator) ..................................... 130 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) ..................................... 128 MOV (MOVE Immediate Byte Data to Memory) ......................................................... 132 MOVW MOVW (MOVE Immediate Word Data to Extra Pointer) .............................................. 154 MOVW (MOVE Immediate Word Data to Index Register) ............................................ 158 MOVW (MOVE Immediate Word Data to Stack Pointer) .............................................. 162 MOVW (MOVE Word Data from Accumulator to Extra Pointer) ..................................... 152 MOVW (MOVE Word Data from Accumulator to Index Register) ................................... 156 MOVW (MOVE Word Data from Accumulator to Memory) ............................................ 150 MOVW (MOVE Word data from Accumulator to Program Status Register) ..................... 160 MOVW (MOVE Word data from Accumulator to Stack Pointer) ..................................... 164 MOVW (MOVE Word Data from Extra Pointer to Accumulator) ..................................... 140 MOVW (MOVE Word Data from Index Register to Accumulator) ..................................... 142 MOVW (MOVE Word Data from Memory to Accumulator) ..................................... 138 INDEX MOVW (MOVE Word Data from Program Counter to Accumulator)...................................... 146 MOVW (MOVE Word Data from Program Status Register to Accumulator) ..................... 144 MOVW (MOVE Word Data from Stack Pointer to Accumulator)...................................... 148 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator)...................................... 136 MOVW A,PC .................................................... 43 Multiple Interrupt Multiple Interrupt............................................... 36 MULU MULU (MULtiply Unsigned) ........................... 166 MULU A .......................................................... 44 N NOP NOP (NoOPeration) ......................................... 168 O Operation Operation List.................................................. 226 OR OR (OR Byte Data of Accumulator and Memory to Accumulator)...................................... 172 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) .............. 170 ORW ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) .............. 174 P PC Program Counter (PC) ........................................ 17 Pointer Addressing Pointer Addressing (@EP) .................................. 41 POPW POPW (POP Word Data of Intherent Register from Stack Memory) ................................... 178 Program Counter Program Counter (PC) ........................................ 17 Program Status Program Status (PS) Flags .................................. 24 Structure of Program Status (PS) ......................... 23 PS Program Status (PS) Flags .................................. 24 Structure of Program Status (PS) ......................... 23 PUSHW PUSHW (PUSH Word Data of Inherent Register to Stack Memory) ................................... 176 R Register Bank Register Bank Register........................................27 Register Bank Pointer Access to Register Bank Pointer and Direct Bank Pointer..................................................25 rel Relative Addressing (rel).....................................42 Relative Addressing Relative Addressing (rel).....................................42 Reset Reset and Interrupt Vector Table..........................11 Reset Operation ..................................................37 RET RET (RETurn from subroutine) .........................180 RETI RETI (RETurn from Interrupt) ...........................182 Ri General-Purpose Register Addressing (Ri) ............41 ROLC ROLC (Rotate Byte Data of Accumulator with Carry to Left) ...............................................184 RORC RORC (Rotate Byte Data of Accumulator with Carry to Right) .............................................186 S SETB SETB (Set Direct Memory Bit) ..........................194 SETC SETC (SET Carry flag) .....................................196 SETI SETI (SET Interrupt flag) ..................................198 Sign Sign of the Instruction List ................................224 SP Stack Pointer (SP)...............................................17 Stack Area Stack Area ...........................................................9 Stack Pointer Stack Pointer (SP)...............................................17 SUBC SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator) ......................................188 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) ..........................................................190 SUBCW SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator) ......................................192 257 INDEX SWAP SWAP (SWAP Byte Data Accumulator ’H’and Accumulator ’L’) ................................ 200 Vector Table Reset and Interrupt Vector Table ......................... 11 X T T Direct Data Transfer from Temporary Accumulator (T) ....................................................... 22 Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 How to Use the Temporary Accumulator (T) ........ 20 Temporary Accumulator (T)................................ 18 Temporary Accumulator Direct Data Transfer from Temporary Accumulator (T) ....................................................... 22 Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 How to Use the Temporary Accumulator (T) ........ 20 Temporary Accumulator (T)................................ 18 V Vector Addressing Vector Addressing (#k)....................................... 42 Vector Call Vector Call Instruction Table............................... 11 258 XCH XCH (eXCHange Byte Data Accumulator ’L’and Temporary Accumulator ’L’) ............... 202 XCHW XCHW (eXCHange Word Data Accumulator and Extrapointer) ...................................... 204 XCHW (eXCHange Word Data Accumulator and Index Register) ................................... 206 XCHW (eXCHange Word Data Accumulator and Program Counter) ............................... 208 XCHW (eXCHange Word Data Accumulator and Stack Pointer) ..................................... 210 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator)..................... 212 XCHW A,PC..................................................... 44 XOR XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator)..................... 216 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) ......................................................... 214 XORW XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator) ......................................................... 218 CM26-00301-2E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL February 2008 the second edition Published FUJITSU LIMITED Edited Strategic Business Development Dept. Electronic Devices