LC88 SERIES CHAPTER 5 INSTRUCTIONS USER'S MANUAL

AND9352/D
CMOS 16-BIT MICROCONTROLLER
LC88 SERIES CHAPTER 5
INSTRUCTIONS
USER’S MANUAL
www.onsemi.com
APPLICATION NOTE
Microcontroller Business Unit
ON Semiconductor
© Semiconductor Components Industries, LLC, 2015
December 2015 - Rev. 0
Publication Order Number :
AND9352/D
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Contents
Chapter 5
Instructions ··································································5-1
5.1 Overview ····················································································· 5-1
5.2 Addressing Modes ········································································ 5-2
5.2.1 Overview ·························································································· 5-2
5.2.2 Addressing (immediate) ······································································· 5-2
5.2.3 Addressing (general-purpose register) ···················································· 5-2
5.2.4 Addressing (bit) ·················································································· 5-2
5.2.5 Addressing (shift amount)····································································· 5-2
5.2.6 Addressing (memory:0 to 0FFFFH) ························································ 5-3
5.2.7 Addressing (memory:0 to FFFF_FFFFH) ················································· 5-4
5.2.8 Addressing (program counter(PC)) ························································· 5-5
5.3 Coding Conventions ······································································ 5-6
5.4 Instruction Descriptions ·························································· 5-(7-216)
－1－
Contents
－2－
LC88 Series Chapter 5
5. Instructions
5.1
Overview
The Ｘstormy16 instructions are classified as shown below. The supported instruction word lengths are word
and its multiples. The number of possible operands is from 0 to 3.
•
Xstormy16 Instruction Types
Type
Instruction
Operand
Operation
Data transfer
MOV, MOVF, MASK
2
op1Åop2
PUSH, POP
PUSH, POP
1
SPÙop1
SWAP
SWPN, SWPB, SWPW
Logical
operation
Arithmetic
operation
Logical shift
AND, OR, XOR, NOT
RRC, RLC, SHR, SHL
2
op1Åf(op1, op2),
op1Åinc/dec(op1)
Shift/Rotate op1 by op2.
Arithmetic shift
ASR
2
Shift op1 by op2.
Bit manipulation SET1, CLR1
2
Set/Clear bit op2 of op1.
Data conversion
CBW, REV
1
op1[15:8]Åop1[7]
Conditional
branch
Bit conditional
branch
Flag conditional
branch
Unconditional
branch
Unconditional
call
BGE, BNC, BLT, BC, BGT, BHI, BLE,
BLS, BPL, BNV, BMI, BV, BNZ, BZ
BN, BP
Return
IRET, RET
1/2
1/2
ADD, ADC, SUB, SBC, INC, DEC
BGE, BNC, BLT, BC, BGT, BHI, BLE,
BLS, BPL, BNV, BMI, BV, BNZ, BZ
BR, JMP, JMPF
CALLR, CALL, CALLF, ICALLR,
ICALL, ICALLF
1/2
3
3
1
1/2
1/2
0
Multiplication/di MUL, DIV, DIVLH, SDIV, SDIVLH
vision
System control
NOP, HALT, HOLD, HOLDX, BRK,
RESET
5-1
op1Ùop1 or op1Ùop2
op1Åf(op1, op2), op1Ånot(op1)
If test(op1-op2), then branch by
op3.
If test(bit op2 of op1), then branch
by op3.
If flag, then branch by op1.
Branch by op1. Jump to op1(, 2).
Branch by op1. Jump to op1(, 2).
Return from subroutine call.
0
0
Control system.
Instructions
5.2
Addressing Modes
5.2.1
Overview
Xstormy16 addresses data on a 64KB bank basis. It can handle a maximum of 4GB of data (0 to FFFF_FFFFH).
This 4GB data includes the programming ROM data.
The program counter (PC) can handle a linear 4GB addressing space (8000H to FFFF_FFFFH). However, only
16 MB space (8000H to 00FF_FFFFH) can be specified with absolute addresses.
5.2.2
1
5.2.3
2
3
5.2.4
Addressing (immediate)
Addressing Mode
Immediate data
Symbol
#imm16, #imm8,
#imm4, #imm2
Addressing (general-purpose register)
Addressing Mode
Register direct
(R0 to R15)
PSW register indirect
(R0 to R15)
Description
The general-purpose register designated by the data in the
instruction code is the operand of the instruction.
The general-purpose register designated by bits 15 to 12 of the
PSW is the operand of the instruction.
Symbol
Rd
Rs
Rx,
RxL, RxH
Addressing (bit)
4
Addressing Mode
Immediate data
5
Register indirect
5.2.5
Description
The data in the instruction code is the operand of the
instruction.
Description
The required bits are designated by the data in the instruction
code.
The required bits are designated by the contents of the
general-purpose register specified by the data in the instruction
code.
Symbol
#imm4
Rs
Addressing (shift amount)
6
Addressing Mode
Immediate data
７
Register indirect
Description
The shift or rotation amount is designated by the data in the
instruction code.
The required shift or rotation amount is designated by the
contents of the general-purpose register specified by the data in
the instruction code.
5-2
Symbol
#imm3,
#imm4
Rs
LC88 Series Chapter 5
5.2.6
8
9
10
Addressing (memory: 0 to 0FFFFH)
Addressing Mode
SFR direct
(7F00 to 7FFFH)
RAM direct
(0000H to 00FFH)
Register indirect
(0000 to FFFFH)
11
Post-increment register
indirect
(0000 to FFFFH)
12
Predecrement register
indirect
(0000 to FFFFH)
13
Register indirect with
offset
(0000 to FFFFH)
14
Post-increment register
indirect with offset
(0000 to FFFFH)
15
Predecrement register
indirect with offset
(0000 to FFFFH)
Description
The result of adding 7F00H to the 8-bit data in the instruction
code is regarded as an address and used to designate the
operand (SFR) in memory.
The 8-bit data in the instruction code is regarded as an address
and used to designate the operand in memory.
The contents of the general-purpose register specified by the
data in the instruction code are regarded as an address*1 and
used to designate the operand in memory.
The contents of the general-purpose register specified by the
data in the instruction code are regarded as an address*1 and
used to designate the operand in memory.
Subsequently, the contents of this general-purpose register are
incremented by 1 (byte access) or 2 (word access).
The contents of the general-purpose register specified by the
data in the instruction code are decremented by 1 (byte access)
or 2 (word access). This value is regarded as an address*1 and
used to designate the operand in memory.
The result*2 of adding the 12-bit singed offset data in the
instruction code to the contents of the general-purpose register
specified by the data in the instruction code is regarded as an
address *1 and used to designate the operand in memory.
The result*2 of adding the 12-bit singed offset data in the
instruction code to the contents of the general-purpose register
specified by the data in the instruction code is regarded as an
address *1 and used to designate the operand in memory.
Subsequently, the contents of this general-purpose register are
incremented by 1 (byte access) or 2 (word access).
The contents of the general-purpose register specified by the
data in the instruction code are decremented by 1 (byte access)
or 2 (word access). The result*2 of adding this value to the
12-bit signed offset data in the instruction code is regarded as
an address*1 and used to designate the operand in memory.
Symbol
m16
m16
(Rd)
(Rs)
(Rd++)
(Rs++)
(--Rd)
(--Rs)
(Rd, ±n)
(Rs, ±n)
(Rd++, ±n)
(Rs++, ±n)
(--Rd, ±n)
(--Rs, ±n)
*1: When a word is accessed, the higher-order byte of the operand is designated if LSB of the address data is 1
and the lower-order byte if the LSB is 0.
*2: Any carry or borrow occurring as the result of the 16-bit arithmetic operation is ignored.
5-3
Instructions
5.2.7
16
Addressing (memory: 0 to FFFF_FFFFH)
Addressing Mode
Extended address
register indirect
(0000_0000 to
FFFF_FFFFH)
17
Extended address
post-increment register
indirect
(0000_0000 to
FFFF_FFFFH)
18
Extended address
pre-decrement register
indirect
(0000_0000 to
FFFF_FFFFH)
19
Extended address
register indirect with
offset *2
(0000_0000 to
FFFF_FFFFH)
20
Extended address
post-increment register
indirect with offset *2
(0000_0000 to
FFFF_FFFFH)
21
Extended address
pre-decrement register
indirect with offset*2
(0000_0000 to
FFFF_FFFFH)
Description
The 32-bit address that contains the contents of the
general-purpose register specified by the data in the instruction
code in its lower-order 16 bit positions and the contents of the
register R8 in its higher-order 16 bit positions is used to
designate the operand in memory.
The 32-bit address*1 that contains the contents of the
general-purpose register specified by the data in the instruction
code in its lower-order 16 bit positions and the contents of the
register R8 in its higher-order 16 bit positions is used to
designate the operand in memory. Subsequently, the contents
of this general-purpose register are incremented by 1 (byte
access) or 2 (word access).
The contents of the general-purpose register specified by the
data in the instruction code are decremented by 1 (byte access)
or 2 (word access). The 32-bit address*1 that contains this
value in its lower-order 16 bit positions and the contents of
register R8 in its higher-order 16 bit positions is used to
designate the operand in memory.
The operand in memory is designated by the 32-bit address*1
of which the lower-order 16 bits are the contents of the result*2
of adding the 12-bit signed offset data in the instruction code
to the contents of the general-purpose register specified by the
data in the instruction code and the higher-order 16 bits are the
contents of the base register specified in the instruction code.
The operand in memory is designated by the 32-bit address*1
of which the lower-order 16 bits are the contents of the result*2
of adding the 12-bit signed offset data in the instruction code
to the contents of the general-purpose register specified by the
data in the instruction code and the higher-order 16 bits are the
contents of the base register specified in the instruction code.
Subsequently, the contents of this general-purpose register are
incremented by 1 (byte access) or 2 (word access).
The contents of the general-purpose register specified by the
data in the instruction code are decremented by 1 (byte access)
or 2 (word access). The 32-bit address*1 of which the
lower-order 16 bits are the results*2 of adding to this value the
12-bit signed offset data in the instruction code and the
higher-order 16 bits are the contents of the base register
specified in the instruction coded is used to designate the
operand in memory.
*1
Symbol
(Rd)
(Rs)
(Rd++)
(Rs++)
(--Rd)
(--Rs)
(Rb, Rd, ±n)
(Rb, Rs, ±n)
(Rb, Rd++, ±n)
(Rb, Rs++, ±n)
(Rb, --Rd, ±n)
(Rb, --Rs, ±n)
*1: When a word is accessed, the higher-order byte of the operand is designated if LSB of the address data is 1
and the lower-order byte if the LSB is 0.
*2: Any carry or borrow occurring as the result of the 16-bit arithmetic operation is ignored.
5-4
LC88 Series Chapter 5
5.2.8
22
23
24
25
Addressing (program counter (PC))
Addressing Mode
Direct absolute PC
(00_0000 to
FF_FFFFH)
Register indirect
absolute PC
(0000_0000H to
FFFF_FFFFH)
Direct relative PC
(0000_0000H to
FFFF_FFFFH)
Register indirect
relative PC
(0000_0000H to
FFFF_FFFFH)
Description
The 24-bit data in the instruction code is used to designate the
PC value directly.
Symbol
a24
The PC value is designated directly by the concatenation of the
contents of the two general-purpose registers (32-bit data)
specified by the data in the instruction code.
(Rb, Rs)
The PC value is designated by the current value of the PC plus
the 8- or 12-bit signed data in the instruction code.
r8
r12
The PC value is designated by the current value of the PC plus
the contents of the general-purpose register specified by the
data in the instruction code that is regarded as 16-bit signed
data.
Rs
5-5
Instructions
5.3
Coding Conventions
This chapter provides a description of a set of Xstormy16 instructions. The symbols used in the individual
instruction descriptions are explained below.
［］
: Indicates that the item(s) are optional.
Underscore
: Underscores identifies argument descriptions.
These include immediate data, memory addresses, and labels.
#immD
: The "#" in the first place denotes the keyword which indicates that the following argument is
immediate data. "immD" following the "#" represents the immediate data. "D" indicates the
allowable bit length of the immediate data.
The valid value range of "D" varies with each instruction.
Rd
: The first "R" denotes the keyword which indicates that the argument is a general-purpose register.
"d" following "R" represents the number of the general-purpose register. The valid value range of
"d" varies with each instruction.
(Example: R0, r0, R7, r7, R8, r8, R13, r13)
Rs
: The basic coding conventions are identical to those for the above Rd.
In this manual, the source of transfer operation is identified by Rs and the destination by Rd.
Rx
: Denotes a general-purpose register that is designated indirectly by the value of bits 12 to 15 (N0
to N3) of the PSW. When coding, write Rx directly.
m16
: Denotes the target address. The value range of m16 is from 00H to FFH (0000H to 00FFH) when
RAM is to be manipulated. When SFRs are to be manipulated, the value range is form 7F00H to
７FFFH.
()
: Denote the contents on which the operation is to be performed.
(m16), for example, represents the contents of the designated RAM or SFR. (PC) represents the
value of the program counter.
Hibyte
: Denote the higher-order 8 bits of 16-bit data or general-purpose register.
Lobyte
: Denote the lower-order 8 bits of 16-bit data or general-purpose register.
++
: Denotes post incrementing (incremented by 1 after the operation is performed).
――
: Denotes predecrementing (decremented by 1 before the operation is performed).
PC
: Denotes the program counter.
SP
: Denotes the stack pointer.
PSW
: Denotes the program status word.
CY
: Denotes the flag containing the carry/borrow from bit 15.
HC
: Denotes the flag containing the carry/borrow from bit 3.
OV
: Denotes the overflow flag.
Z8
: Denotes the zero flag for the lower-order 8 bits.
Z16
: Denotes the zero flag for the data.
P
: Denotes the parity flag.
S
: Denotes the sign flag.
&
: Denotes the logical AND operator.
｜
: Denotes the logical OR operator.
＾
: Denotes the exclusive OR operator.
5-6
LC88 Series Chapter 5
5.4
ADC
Instruction Descriptions
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 0 0 1 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select), imm4 = 4bit(immediate data)
1
1
(Rd) ← (Rd) + #imm4 + CY, (PC) ← (PC) +2
Z8, Z16, CY, HC, OV, P, S, N0 to N3
5300H
[Description]
This instruction adds the contents of the general-purpose register designated by Rd, immediate data
desaignated by imm4, and the value of the carry flag (CY) and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 from 0 to Fh.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
ADC
ADC
ADC
ADC
R0, #0x7FFF
R1, #0x8766
R2, #0xFFFF
R3, #0x3456
R0, #0x06
R1, #0x0A
R2, #0x01
R3, #0x0F
R0
R1
R2
R3
7FFFh
7FFFh
7FFFh
7FFFh
8005h
8005h
8005h
8005h
8766h
8766h
8766h
8766h
8770h
8770h
8770h
FFFFh
FFFFh
FFFFh
FFFFh
0000h
0000h
3456h
3456h
3456h
3456h
3466h
5-7
N3 to
N0
0
1
2
3
0
1
2
3
Z8 Z16 CY HC OV P
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
0
1
S
0
1
1
0
1
1
0
0
Instructions
ADC
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
0 0 1 1 0 0 0 1][0 1 0 1 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select), imm16 = 16bit(immediate data)
2
2
(Rd) ← (Rd) + #imm16 + CY, (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
3150H
[Description]
This instruction adds the contents of the general-purpose register designated by Rd, immediate data
desaignated by imm16, and the value of the carry flag (CY) and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 from 0 to FFFFh.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
ADC
ADC
ADC
ADC
R0, #0x7FFF
R1, #0x8766
R2, #0xFFFF
R3, #0x3456
R0, #0x00F6
R1, #0xA987
R2, #0x0001
R3, #0x0055
R1
7FFFh
7FFFh 8766h
7FFFh 8766h
7FFFh 8766h
80F5h 8766h
80F5h 30EDh
80F5h 30EDh
80F5h 30EDh
R2
R3
FFFFh
FFFFh
FFFFh
FFFFh
0001h
0001h
3456h
3456h
3456h
3456h
34Ach
5-8
N3 to
N0
0
1
2
3
0
1
2
3
Z8 Z16 CY HC OV P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
1
1
S
0
1
1
0
1
0
0
0
LC88 Series Chapter 5
ADC Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 1 0 1 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
1
(Rd) ← (Rd) + (Rs) + CY, (PC) ← (PC)+2
Z8, Z16, CY, HC, OV, P, S, N0 to N3
4B00H
[Description]
This instruction adds the contents of general-purpose register designated by Rd, the contents of the
general-purpose register designated by Rs, and the value of the carry flag (CY) and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
ADC
ADC
ADC
ADC
ADC
ADC
R0, #0x789A
R1, #0x8766
R2, #0xFEDC
R3, #0x3456
R0, R1
R1, R2
R2, R3
R3, R0
R3, R2
R3, R2
R0
R1
R2
R3
789Ah
789Ah
789Ah
789Ah
0000h
0000h
0000h
0000h
0000h
0000h
8766h
8766h
8766h
8766h
8643h
8643h
8643h
8643h
8643h
FEDCh
FEDCh
FEDCh
FEDCh
3333h
3333h
3333h
3333h
3456h
3456h
3456h
3456h
3457h
678Ah
9ABDh
5-9
N3 to
N0
0
1
2
3
0
1
2
3
3
3
Z8 Z16 CY HC OV P
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
S
0
1
1
0
0
1
0
0
0
1
Instructions
ADC
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 1 0 1 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx) ← (Rx) + #imm8 + CY, (PC) ← (PC)+2
Z8, Z16, CY, HC, OV, P, S
5B00H
[Description]
This instruction adds the contents of the general-purpose register Rx designated indirectly by bits 12 to 15
(N0 to N3) of the PSW, immediate data designated by imm8, and the value of the carry flag (CY) and places
the result in Rx.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
ADC
INC
ADC
NOT
ADC
SWPB
ADC
R3, #0x3456
R2, #0x0000
R1, #0x8766
R0, #0x7FFF
Rx, #0xF6
R1
Rx, #0x99
R2
Rx, #0x01
R3
Rx, #0x55
R0
R1
7FFFh
80F5h
80F5h
80F5h
80F5h
80F5h
80F5h
80F5h
8766h
8766h
8766h
8767h
8800h
8800h
8800h
8800h
8800h
R2
R3
3456h
0000h 3456h
0000h 3456h
0000h 3456h
0000h 3456h
0000h 3456h
0000h 3456h
FFFFh 3456h
0000h 3456h
0000h 5634h
0000h 568Ah
5-10
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8 Z16 CY HC OV P
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
1
S
0
0
1
0
1
1
1
1
0
0
0
LC88 Series Chapter 5
ADD
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 0 0 0 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select), imm4 = 4bit(immediate data)
1
1
(Rd) ← (Rd) + #imm4, (PC)←(PC)+2
Z8, Z16, CY, HC, OV, P, S, N0 to N3
5100H
[Description]
This instruction adds the contents of the general-purpose register designated by Rd and immediate data
designated by imm4 and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 from 0 to Fh.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
ADD
ADD
ADD
ADD
R0, #0x7FFF
R1, #0x8766
R2, #0xFFFF
R3, #0x3456
R0, #0x06
R1, #0x0A
R2, #0x01
R3, #0x0F
7FFFh
7FFFh
7FFFh
7FFFh
8005h
8005h
8005h
8005h
R1
R2
R3
8766h
8766h FFFFh
8766h FFFFh 3456h
8766h FFFFH 3456h
8770h FFFFh 3456h
8770h 0000h 3456h
8770h 0000h 3465h
5-11
N3 to
N0
0
1
2
3
0
1
2
3
Z8 Z16 CY HC OV P
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
0
1
S
0
1
1
0
1
1
0
0
Instructions
ADD
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 1 0 0 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select), imm16 = 16bit(immediate data)
2
2
(Rd) ← (Rd) + #imm16, (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
3140H
[Description]
This instruction adds the contents of the general-purpose register designated by Rd and immediate data
designated by imm16 and places the result in Rd. The legitimate value range designated by Rd is from R0 to
R15 and that by imm16 from 0 to FFFFh.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
ADD
ADD
ADD
ADD
R0, #0x7FFF
R1, #0x8766
R2, #0xFFFF
R3, #0x3456
R0, #0x00F6
R1, #0xA987
R2, #0x0001
R3, #0x0055
R1
7FFFh
7FFFh 8766h
7FFFh 8766h
7FFFh 8766h
80F5h 8766h
80F5h 30EDh
80F5h 30EDh
80F5h 30EDh
R2
R3
FFFFh
FFFFh 3456h
FFFFh 3456h
FFFFh 3456h
0000h 3456h
0000h 34ABh
5-12
N3 to
N0
0
1
2
3
0
1
2
3
Z8 Z16 CY HC OV P
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
S
0
1
1
0
1
0
0
0
LC88 Series Chapter 5
ADD
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 1 0 0 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
1
(Rd) ← (Rd) + (Rs), (PC) ← (PC)+2
Z8, Z16, CY, HC, OV, P, S, N0 to N3
4900H
[Description]
This instruction adds the contents of the general-purpose register designated by Rd and the general-purpose
register designated by Rs and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs from R0 to R15.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
ADD
ADD
ADD
ADD
ADD
ADD
R0, #0x789A 789Ah
R1, #0x8766 789Ah
R2, #0xFEDC 789Ah
R3, #0x3456 789Ah
R0, R1
0000h
R1, R2
0000h
R2, R3
0000h
R3, R0
0000h
R3, R2
0000h
R3, R2
0000h
R1
R2
R3
8766h
8766h
8766h
8766h
8642h
8642h
8642h
8642h
8642h
FEDCh
FEDCh
FEDCh
FEDCh
3332h
3332h
3332h
3332h
3456h
3456h
3456h
3456h
3456h
6788h
9ABAh
5-13
N3 to
N0
0
1
2
3
0
1
2
3
3
3
Z8 Z16 CY HC OV P
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
S
0
1
1
0
0
1
0
0
0
1
Instructions
ADD
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 1 0 0 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx) ← (Rx) + #imm8, (PC) ← (PC)+2
Z8, Z16, CY, HC, OV, P, S
5900H
[Description]
This instruction adds the contents of the general-purpose register Rx designated indirectly by bits 12 to 15
(N0 to N3) of the PSW and immediate data designated by imm8 and places the result in Rx.
The legitimate value range designated by imm8 is from 0 to FFh.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
ADD
INC
ADD
NOT
ADD
SWPB
ADD
R3,
R2,
R1,
R0,
Rx,
R1
Rx,
R2
Rx,
R3
Rx,
#0x3456
#0x0000
#0x8766
#0x7FFF
#0xF6
#0x99
#0x01
#0x55
R0
R1
R2
R3
7FFFh
80F5h
80F5h
80F5h
80F5h
80F5h
80F5h
80F5h
8766h
8766h
8766h
8767h
8800h
8800h
8800h
8800h
8800h
0000h
0000h
0000h
0000h
0000h
0000h
FFFFh
0000h
0000h
0000h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5634h
5689h
5-14
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8 Z16 CY HC OV P
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
1
S
0
0
1
0
1
1
1
1
0
0
0
LC88 Series Chapter 5
AND
Rd, #imm16
Instruction code
[0 0 1 1 0 0 0 1][0 0 0 0 d3d2d1d0][i15 to i8][i7 to i0]
Argument
Rd = 4bit(R select), imm16 = 16bit(immediate data)
Word count
2
Cycle count
2
Function
(Rd) ← (Rd) & #imm16,
Affected flags
Z8, Z16, P, S, N0 to N3
3100H
(PC) ← (PC)+4
[Description]
This instruction takes the AND of the contents of general-purpose register designated by Rd and immediate
data designated by imm16 and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 from 0 to FFFFｈ.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
AND
AND
AND
AND
R0, #0x5678 5678h
R1, #0x0000 5678h
R2, #0xFEDC 5678h
R3, #0x3456 5678h
R0, #0xFFFF 5678h
R1, #0x89AB 5678h
R2, #0x9ABC 5678h
R3, #0x1234 5678h
R1
R2
R3
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FEDCh
FEDCh
FEDCh
FEDCh
9A9Ch
9A9Ch
3456h
3456h
3456h
3456h
1014h
5-15
N3 to
N0
0
1
2
3
0
1
2
3
Z8 Z16 CY HC OV P
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
1
1
S
0
1
1
0
1
0
0
0
Instructions
AND
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 0 0 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
1
(Rd) ← (Rd) & (Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
4000H
[Description]
This instruction takes the AND of the contents of the general-purpose register designated by Rd and the
general-purpose register designated by Rs and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
AND
AND
AND
AND
MOV.W
MOV.W
MOV.W
AND
AND
AND
AND
R0,
R1,
R2,
R3,
R0,
R1,
R2,
R2,
R0,
R1,
R3,
R0,
R1,
R2,
R2,
#0x5678
#0x0000
#0x1200
#0xFFFF
R3
R3
R3
R0
#0x8118
#0x5678
#0x3456
R3
R3
R3
R0
R0
R1
R2
R3
5678h
5678h
5678h
5678h
5678h
5678h
5678h
5678h
8118h
8118h
8118h
8118h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5678h
5678h
5678h
5678h
5678h
5678h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
3456h
3456h
3456h
3456h
0010h
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
5-16
N3 to
N0
0
1
2
3
0
1
2
2
0
1
2
0
1
2
2
Z8
Z16
P
S
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
LC88 Series Chapter 5
AND
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 0 0 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx) ← (Rx) & 16bit data(Hibyte=00H, Lobyte=#imm8),
Z8, Z16, P, S
4100H
(PC) ← (PC)+2
[Description]
This instruction takes the AND of the contents of the general-purpose register (Rx) designated indirectly by
bits 12 to 15 (N0 to N3) of the PSW and 16-bit data (of which the higher-order 8 bits are 00H and the
lower-order 8 bits are #imm8) and places the result in Rx.
The legitimate value range designated by imm8 is from 0 to FFh.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
AND
INC
AND
SWPB
AND
DEC
AND
R3,
R2,
R1,
R0,
Rx,
R1
Rx,
R2
Rx,
R3
Rx,
#0x0000
#0x0012
#0x0000
#0x5678
#0x08
#0x01
#0x41
#0xFF
R0
R1
5678h
0008h
0008h
0008h
0008h
0008h
0008h
0008h
0000h
0000h
0000h
0001h
0001h
0001h
0001h
0001h
0001h
R2
R3
0000h
0012h 0000h
0012h 0000h
0012h 0000h
0012h 0000h
0012h 0000h
0012h 0000h
1200h 0000h
0000h 0000h
0000h FFFFh
0000h 00FFh
5-17
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8
Z16
P
S
1
0
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Instructions
ASR
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 1 1 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select), imm4 = 4bit(immediate data)
1
1
(Rd) ← (Rd) arithmetic shift right #imm4 bit
(CY) ← last shift bit, (PC) ← (PC)+2
Z8, Z16, CY, P, S, N0 to N3
3700H
[Description]
This instruction performs an arithmetic shift right of the contents of the general-purpose register designated
by Rd by value (arithmetic shift amount) indicated by immediate data designated by imm4 and places the
carryover bit out of the LSB in the carry flag (CY).
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 from 0 to Fh.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
ASR
ASR
ASR
ASR
R0, #0xCDEF
R1, #0x5432
R2, #0x0000
R3, #0x7654
R14, #2
R0, #0x02
R1, #0x00
R2, #0x04
R3, #0x0B
R0
R1
CDEFh
CDEFh
CDEFh
CDEFh
CDEFh
F37Bh
F37Bh
F37Bh
F37Bh
5432h
5432h
5432h
5432h
5432h
5432h
5432h
5432h
R2
R3
0000h
0000h 7654h
0000h 7654h
0000h 7654h
0000h 7654h
0000h 7654h
0000h 000Eh
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
<Note>
During the execution of an arithmetic shift instruction, the MSB of Rd is regarded as the sign bit and its value
remains unchanged during the shift operations. The value of the MSB is copied to the right bit position on
each shift operation.
5-18
LC88 Series Chapter 5
ASR
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 1 1 0 ][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
1
(Rd) ← (Rd) arithmetic shift right (Lower 4bit value of Rs) bit
(CY) ← last shift bit, (PC) ← (PC)+2
Z8, Z16, CY, P, S, N0 to N3
3600H
[Description]
This instruction performs an arithmetic shift right of the contents of the general-purpose register designated
by Rd by the value (arithmetic shift amount) indicated by the lower-order 4 bits of the general-purpose
register designated by Rs and places the carryover bit out of the LSB in the carry flag (CY).
The legitimate value range indicated by Rd is from R0 to R15 and that by RsR0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
ASR
ASR
ASR
ASR
R0, #0xCDEF
R1, #0x5432
R2, #0x0000
R3, #0x7654
R14, #2
R0, R1
R1, R2
R2, R3
R3, R0
R0
R1
R2
R3
CDEFh
CDEFh
CDEFh
CDEFh
CDEFh
F37Bh
F37Bh
F37Bh
F37Bh
5432h
5432h
5432h
5432h
5432h
5432h
5432h
5432h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
7654h
7654h
7654h
7654h
7654h
000Eh
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
<Note>
During the execution of an arithmetic shift instruction, the MSB of Rd is regarded as the sign bit and its value
remains unchanged during the shift operations. The value of the MSB is copied to the right bit position on
each shift operation.
5-19
Instructions
BC r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 0 1 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If CY=1, then (PC) ← (PC)+2±(r8)
If CY=0, then (PC) ← (PC)+2
D300H
Affected flags
[Description]
This instruction adds the value of relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the carry flag (CY) is 1. If CY is 0, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W
MOV.W
RRC
R2, #0x0002
R3, 0xFFFF
R2, #1
BC
RRC
BC
BR
LA
R2, #1
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
PC
R2
R3
PSW
9002h
9006h
9008h
0002h
0002h
0001h
FFFFh
FFFFh
2020h
3040h
2020h
900Ah
900Ch
9014h
-
0001h
0000h
0000h
-
FFFFh
FFFFh
FFFFh
-
2020h
2007h
2007h
-
-
-
-
-
9016h
9018h
0000h
0000h
0000h
0000h
3007h
3007h
loop:
;; NOT JUMP LA
;; JUMP LB
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-20
LC88 Series Chapter 5
BC
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 0 1 1 r11 to r8][r7 to r0]
20003000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd) < #imm8, then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd) ≧#imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
of the general-purpose register designated by Rd is negative. If the result of the subtraction is nonnegative, 4
is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
#0x0056
#0x0012
#0x0056
#0xFFFF
R0
R1
R2
R3
0056h
0056h 0012h
0056h 0012h 0056h
0056h 0012h 0056h FFFFh
PSW
0000h
1000h
2000h
3040h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BC
BC
BR
R0,#0x56, LA ;; NOT JUMP LA 900Eh 0056h 0012h 0056h FFFFh 0003h
R1,#0x56, LB ;; JUMP LB
9018h 0056h 0012h 0056h FFFFh 106Ch
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
LA:
-
-
-
-
-
-
LB:
901Ah 0056h 0012h 0056h 0000h 300Fh
901Ch 0056h 0012h 0056h 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-21
Instructions
BC
Rd, Rs, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 0 1 1 r11 to r8][r7 to r0]
0D003000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd) < (Rs), then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd)≧(Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents of the general-purpose register designated
by Rs from the contents of the general-purpose register designated by Rd is negative. If the result of the
subtraction is nonnegative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BC
BC
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x5678
#0x1234
#0x5678
#0xFFFF
R0
R1
R2
R3
5678h
5678h 1234h
5678h 1234h 5678h
5678h 1234h 5678h FFFFh
PSW
0000h
1020h
2000h
3040h
loop:
;; NOT JUMP LA 9014h 5678h 1234h 5678h FFFFh 0003h
;; JUMP LB
901Eh 5678h 1234h 5678h FFFFh 106Ch
-
LA:
-
-
-
-
-
-
LB:
9020h 5678h 1234h 5678h 0000h 300Fh
9022h 5678h 1234h 5678h 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-22
LC88 Series Chapter 5
BC
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 0 1 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C3000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of unsigned comparison is (Rx) < #imm16, then (PC)←(PC)+4±(r8)
If result of unsigned comparison is (Rx)≧#imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 from the contents
of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3) of the PSW is negative. If
the result of the subtraction is nonnegative, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0x5678
MOV.W R3, #0xFFFF
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
5678h
2000h
5678h FFFFh 3040h
loop:
MOV.W
BC
MOV.W
BC
BR
R0, #0x5678
900Ch 5678h
5678h
Rx, #0x5678, LA ;; NOT JUMP LA 9010h 5678h
5678h
R1, #0x1234
9014h 5678h 1234h 5678h
Rx, #0x5678, LB ;; JUMP LB
901Eh 5678h 1234h 5678h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
FFFFh
FFFFh
FFFFh
FFFFh
-
0000h
0003h
1020h
106Ch
-
-
-
LA:
-
-
-
-
LB:
9020h 5678h 1234h 5678h 0000h 300Fh
9022h 5678h 1234h 5678h 0000h 300Fh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-23
Instructions
BGE r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 0 0 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S ^ OV = 0, then (PC)←(PC)+2±(r8)
If S ^ OV = 1, then (PC)←(PC)+2
D000H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the exclusive logical OR of the sign flag (S) and overflow flag (OV)
is 0. If the result of the logical operation is 1, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
MOV.W
R3,#0xFFFF
9004h
FFFFh
3040h
BGE
MOV.W
BGE
BR
LA
;; NOT JUMP LA
R3, #0x0000
LB
;; JUMP LB
loop
9006h
9008h
9010h
-
FFFFh
0000h
0000h
-
3040h
3003h
3003h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0001h
0001h
3020h
3020h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-24
LC88 Series Chapter 5
BGE
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 0 0 0 r11 to r8][r7 to r0]
20000000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd)≧#imm8, then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd) < #imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
(signed 16-bit data) of the general-purpose register designated by Rd is nonnegative. If the result of the
subtraction is negative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ch
9010h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0xCDEF
#0x789A
#0x1234
#0xFFFF
BGE
BGE
BR
R0, #0x12, LA ;; NOT JUMP LA 9014h
R1, #0x12, LB ;; JUMP LB
901Eh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
CDEFh
CDEFh 789Ah
CDEFh 789Ah 1234h
CDEFh 789Ah 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
CDEFh 789Ah 1234h FFFFh 0060h
CDEFh 789Ah 1234h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
9020h
9022h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-25
CDEFh 789Ah 1234h 0000h 3003h
CDEFh 789Ah 1234h 0000h 3003h
Instructions
BGE
Rd, Rs, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 0 0 0 r11 to r8][r7 to r0]
0D000000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd)≧(Rs), then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd) < (Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents (signed 16-bit data) of the general-purpose
register designated by Rs from the contents (signed 16-bit data) of the general-purpose register designated by
Rd is nonnegative. If the result of the subtraction is negative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BGE
BGE
BR
R0, R2 , LA
R1, R2 , LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0xCDEF
#0x789A
#0x1234
#0xFFFF
R0
R1
R2
R3
CDEFh
CDEFh 789Ah
CDEFh 789Ah 1234h
CDEFh 789Ah 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h CDEFh 789Ah 1234h FFFFh 0040h
901Eh CDEFh 789Ah 1234h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
9020h CDEFh 789Ah 1234h 0000h 3003h
9022h CDEFh 789Ah 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-26
LC88 Series Chapter 5
BGE
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 0 0 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C0000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of signed comparison is (Rx)≧#imm16, then (PC)←(PC)+4±(r8)
If result of signed comparison is (Rx) < #imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 (signed 16-bit
data) from the contents (signed 16-bit data) of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW is nonnegative. If the result of the subtraction is negative, 4 is added to the
PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0x1234
MOV.W R3, #0xFFFF
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
MOV.W
BGE
MOV.W
BGE
BR
R0, #0xCDEF
900Ch CDEFh
1234h
Rx, #0x1234, LA ;; NOT JUMP LA 9010h CDEFh
1234h
R1, #0x789A
9014h CDEFh 789Ah 1234h
Rx, #0x1234, LB ;; JUMP LB
901Eh CDEFh 789Ah 1234h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
FFFFh
FFFFh
FFFFh
FFFFh
-
0040h
0040h
1000h
1000h
-
-
-
LA:
-
-
-
-
LB:
9020h CDEFh 789Ah 1234h 0000h 3003h
9022h CDEFh 789Ah 1234h 0000h 3003h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-27
Instructions
BGT
r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 1 0 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S ^ OV | Z16 = 0, then (PC)←(PC)+2±(r8)
If S ^ OV | Z16 = 1, then (PC)←(PC)+2
D400H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the logical OR between the 16-bit operation flag (Z16) and the
result of an exclusive logical OR of the sign flag (S) and overflow flag (OV) is 0. If the result of the logical
operations is 1, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
MOV.W
R3,#0xFFFF
9004h
FFFFh
3040h
BGT
MOV.W
BGT
BR
LA
;; NOT JUMP LA
R3, #0x1200
LB
;; JUMP LB
loop
9006h FFFFh
900Ah 1200h
9012h 1200h
-
3040h
3001h
3001h
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
LA:
-
-
-
9014h
9016h
1201h
1201h
3020h
3020h
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-28
LC88 Series Chapter 5
BGT
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 1 0 0 r11 to r8][r7 to r0]
20004000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd) > #imm8, then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd)≦#imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
(signed 16-bit data) of the general-purpose register designated by Rd is positive. If the result of the
subtraction is nonpositive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9006h
9008h
900Ch
#0x0056
#0x7654
#0x0056
#0xFFFF
R0
R1
R2
R3
0056h
0056h 7654h
0056h 7654h 0056h
0056h 7654h 0056h FFFFh
PSW
0000h
1000h
2000h
3040h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BGT
BGT
BR
R0, #0x56, LA ;; NOT JUMP LA 9010h 0056h 7654h 0056h FFFFh 0003h
R1, #0x56, LB ;; JUMP LB
901Ah 0056h 7654h 0056h FFFFh 1008h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
LA:
-
-
-
-
-
-
LB:
901Ch 0056h 7654h 0056h 0000h 300Bh
901Eh 0056h 7654h 0056h 0000h 300Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-29
Instructions
BGT
Rd, Rs, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 1 0 0 r11 to r8][r7 to r0]
0D004000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd) > (Rs), then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd)≦(Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents (signed 16-bit data) of the general-purpose
register designated by Rs from the contents (signed 16-bit data) of the general-purpose register designated by
Rd is positive. If the result of the subtraction is nonpositive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BGT
BGT
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x89AB
#0x789A
#0x89AB
#0xFFFF
R0
R1
Ｒ2
R3
89ABh
89ABh 789Ah
89ABh 789Ah 89ABh
89ABh 789Ah 89ABh FFFFh
PSW
0040h
1000h
2040h
3040h
loop:
;; NOT JUMP LA 9014h 89ABh 789Ah 89ABh FFFFh 0003h
;; JUMP LB
901Eh 89ABh 789Ah 89ABh FFFFh 107Ch
-
LA:
-
-
-
-
-
-
LB:
9020h
9022h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-30
89ABh 789Ah 89ABh 0000h 301Fh
89ABh 789Ah 89ABh 0000h 301Fh
LC88 Series Chapter 5
BGT
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 1 0 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C4000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of signed comparison is (Rx) > #imm16, then (PC)←(PC)+4±(r8)
If result of signed comparison is (Rx)≦ #imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 (signed 16-bit
data) from the contents (signed 16-bit data) of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW is positive. If the result of the subtraction is nonpositive, 4 is added to the
PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0x89AB
MOV.W R3, #0xFFFF
PC
R0
R1
R2
R3
PSW
9004h
9008h
-
-
89ABh
2040h
89ABh FFFFh 3040h
89ABh
-
89ABh FFFFh 0040h
loop:
900C
h
BGT
Rx,#0x89AB, LA ;; NOT JUMP LA 9010h
MOV.W R1, #0x789A
9014h
BGT
Rx,#0x89AB, LB ;; JUMP LB
901Eh
BR
loop
MOV.W R0, #0x89AB
89ABh
89ABh FFFFh 0003h
89ABh 789Ah 89ABh FFFFh 1000h
89ABh 789Ah 89ABh FFFFh 107Ch
-
LA:
DEC
BR
R3
loop
INC
NOP
R3
-
-
-
-
-
-
LB:
9020h 89ABh 789Ah 89ABh 0000h 301Fh
9022h 89ABh 789Ah 89ABh 0000h 301Fh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-31
Instructions
BHI
r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 1 0 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If CY | Z16 = 0, then (PC)←(PC)+2±(r8)
If CY | Z16 = 1, then (PC)←(PC)+2
D500H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the logical OR of the carry flag (CY) and the 16-bit operation flag
(Z16) is 0. If the result of the logical operation is 1, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W
MOV.W
RRC
R2, #0x0001
R3,#0xFFFF
R2, #1
BHI
RRC
BHI
BR
LA
R2, #1
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
PC
R2
R3
PSW
9002h
9006h
9008h
0001h
0001h
0000h
FFFFh
FFFFh
2020h
3040h
2007h
900Ah
900Ch
9014h
-
0000h
8000h
8000h
-
FFFFh
FFFFh
FFFFh
-
2007h
2061h
2061h
-
-
-
-
-
9016h
9018h
8000h
8000h
0000h
0000h
3003h
3003h
loop:
;; NOT JUMP LA
;; JUMP LB
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-32
LC88 Series Chapter 5
BHI
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 1 0 1 r11 to r8][r7 to r0]
20005000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd) > #imm8, then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd)≦#imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
of the general-purpose register designated by Rd is positive. If the result of the subtraction is nonpositive, 4 is
added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x0089
#0x0098
#0x0089
#0xFFFF
BHI
BHI
BR
R0,#0x89, LA ;; NOT JUMP LA
R1,#0x89, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
0089h
0089h 0098h
0089h 0098h 0089h
0089h 0098h 0089h FFFFh
PSW
0020h
1020h
2020h
3040h
loop:
900Eh 0089h 0098h 0089h FFFFh 0003h
9018h 0089h 0098h 0089h FFFFh 1008h
-
LA:
-
-
-
-
-
-
LB:
901Ah 0089h 0098h 0089h 0000h 300Bh
901Ch 0089h 0098h 0089h 0000h 300Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-33
Instructions
BHI Rd,
Rs, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 1 0 1 r11 to r8][r7 to r0]
0D005000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd) > (Rs), then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd)≦(Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents of the general-purpose register designated
by Rs from the contents of the general-purpose register designated by Rd is positive. If the result of the
subtraction is nonpositive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BHI
BHI
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x89AB
#0x9876
#0x89AB
#0xFFFF
R0
R1
R2
R3
89ABh
89ABh 9876h
89ABh 9876h 89ABh
89ABh 9876h 89ABh FFFFh
PSW
0040h
1040h
2040h
3040h
loop:
;; NOT JUMP LA 9014h 89ABh 9876h 89ABh FFFFh 0003h
;; JUMP LB
901Eh 89ABh 9876h 89ABh FFFFh 1008h
-
LA:
-
-
-
-
-
-
LB:
9020h 89ABh 9876h 89ABh 0000h 300Bh
9022h 89ABh 9876h 89ABh 0000h 300Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-34
LC88 Series Chapter 5
BHI
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 1 0 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C5000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of unsigned comparison is (Rx) > #imm16, then (PC)←(PC)+4±(r8)
If result of unsigned comparison is (Rx)≦#imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 from the contents
of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3) of the PSW is positive. If
the result of the subtraction is nonpositive, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0x89AB
MOV.W R3, #0xFFFF
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
89ABh
2040h
89ABh FFFFh 3040h
loop:
MOV.W
BHI
MOV.W
BHI
BR
R0, #0x89AB
900Ch 89ABh
89ABh
Rx,#0x89AB, LA ;; NOT JUMP LA 9010h 89ABh
89ABh
R1, #0x9876
9014h 89ABh 9876h 89ABh
Rx,#0x89AB, LB ;; JUMP LB
901Eh 89ABh 9876h 89ABh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
FFFFh
FFFFh
FFFFh
FFFFh
-
0040h
0003h
1040h
1008h
-
-
-
LA:
-
-
-
-
LB:
9020h 89ABh 9876h 89ABh 0000h 300Bh
9022h 89ABh 9876h 89ABh 0000h 300Bh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-35
Instructions
BLE r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 1 1 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S ^ OV | Z16 =1, then (PC)←(PC)+2±(r8)
If S ^ OV | Z16 =0, then (PC)←(PC)+2
D600H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the logical OR between the 16-bit operation flag (Z16) and the
result of exclusive logical OR of the sign flag (S) and the overflow flag (OV) is 1. If the result of the logical
operations is 0, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
MOV.W
R3, #0x1200
9004h
1200h
3001h
BLE
MOV.W
BLE
BR
LA
;; NOT JUMP LA
R3, #0x0000
LB
;; JUMP LB
loop
9006h
9008h
9010h
-
1200h
0000h
0000h
-
3001h
3003h
3003h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0001h
0001h
3020h
3020h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-36
LC88 Series Chapter 5
BLE
Rd, #imm8, r12
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 1 1 0 r11 to r8][r7 to r0]
20006000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd)≦#imm8, then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd) > #imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
(signed 16-bit data) of the general-purpose register designated by Rd is nonpositive. If the result of the
subtraction is positive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x00EF
#0x0098
#0x00CD
#0xFFFF
BLE
BLE
BR
R0,#0xCD, LA ;; NOT JUMP LA
R1,#0xCD, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
00EFh
00EFh 0098h
00EFh 0098h 00CDh
00EFh 0098h 00CDh FFFFh
PSW
0020h
1020h
2020h
3040h
loop:
900Eh 00EFh 0098h 00CDh FFFFh 0000h
9018h 00EFh 0098h 00CDh FFFFh 106Ch
-
LA:
-
-
-
-
-
-
LB:
901Ah 00EFh 0098h 00CDh 0000h 300Fh
901Ch 00EFh 0098h 00CDh 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-37
Instructions
BLE
Rd, Rs, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 1 1 0 r11 to r8][r7 to r0]
0D006000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd)≦(Rs), then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd) > (Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents (signed 16-bit data) of the general-purpose
register designated by Rs from the contents (signed 16-bit data) of the general-purpose register designated by
Rd is nonpositive. If the result of the subtraction is positive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BLE
BLE
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x7654
#0x9876
#0xCDEF
#0xFFFF
R0
R1
R2
R3
7654h
7654h 9876h
7654h 9876h CDEFh
7654h 9876h CDEFh FFFFh
PSW
0000h
1040h
2040h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 7654h 9876h CDEFh FFFFh 007Ch
901Eh 7654h 9876h CDEFh FFFFh 104Ch
-
LA:
-
-
-
-
-
-
LB:
9020h 7654h 9876h CDEFh 0000h 300Fh
9022h 7654h 9876h CDEFh 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-38
LC88 Series Chapter 5
BLE
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 1 1 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C6000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of signed comparison is (Rx)≦#imm16, then (PC)←(PC)+4±(r8)
If result of signed comparison is (Rx) > #imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 (signed 16-bit
data) from the contents (signed 16-bit data) of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW is nonpositive. If the result of the subtraction is positive, 4 is added to the
PC.
The legitimate value range designated by imm16 is signed 16-bit data (-32768 to 32767), and that by the
relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
CDEFh
2040h
CDEFh FFFFh 3040h
MOV.W
MOV.W
R2, #0xCDEF
R3, #0xFFFF
MOV.W
BLE
MOV.W
BLE
BR
R0, #0x7654
900Ch 7654h
CDEFh
Rx,#0xCDEF,LA ;; NOT JUMP LA 9010h 7654h
CDEFh
R1, #0x9876
9014h 7654h 9876h CDEFh
Rx,#0xCDEF,LB ;; JUMP LB
901Eh 7654h 9876h CDEFh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
FFFFh
FFFFh
FFFFh
FFFFh
-
0000h
007Ch
105Ch
104Ch
-
-
-
LA:
-
-
-
-
LB:
9020h 7654h 9876h CDEFh 0000h 300Fh
9022h 7654h 9876h CDEFh 0000h 300Fh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-39
Instructions
BLS r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 1 1 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If CY | Z16 = 1, then (PC)←(PC)+2±(r8)
If CY | Z16 = 0, then (PC)←(PC)+2
D700H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the logical OR of the carry flag (CY) and the 16-bit operation flag
(Z16) is 1. If the result of the logical operation is 0, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W
MOV.W
RRC
R2, #0x0002
R3,#0xFFFFh
R2, #1
BLS
RRC
BLS
BR
LA
R2, #1
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
PC
R2
R3
PSW
9002h
9006h
9008h
0002h
0002h
0001h
FFFFh
FFFFh
2020h
3040h
2020h
900Ah
900Ch
9014h
-
0001h
0000h
0000h
-
FFFFh
FFFFh
FFFFh
-
2020h
2007h
2007h
-
-
-
-
-
9016h
9018h
0000h
0000h
0000h
0000h
3007h
3007h
loop:
;; NOT JUMP LA
;; JUMP LB
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-40
LC88 Series Chapter 5
BLS
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 1 1 1 r11 to r8][r7 to r0]
20007000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd)≦#imm8, then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd) > #imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
of the general-purpose register designated by Rd is nonpositive. If the result of the subtraction is positive, 4 is
added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
#0x00FE
#0x0098
#0x00CD
#0xFFFF
R0
R1
R2
R3
00FEh
00FEh 0098h
00FEh 0098h 00CDh
00FEh 0098h 00CDh FFFFh
PSW
0020h
1020h
2020h
3040h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BLS
BLS
BR
R0, #0xCD, LA ;; NOT JUMP LA 900Eh 00FEh 0098h 00CDh FFFFh 0020h
R1, #0xCD, LB ;; JUMP LB
9018h 00FEh 0098h 00CDh FFFFh 106Ch
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
LA:
-
-
-
-
-
-
LB:
901Ah 00FEh 0098h 00CDh 0000h 300Fh
901Ch 00FEh 0098h 00CDh 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-41
Instructions
BLS
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 1 1 1 r11 to r8][r7 to r0]
0D007000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd)≦(Rs), then (PC)←(PC)+4±(r12)
If result of unsigned comparison is (Rd) > (Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents of the general-purpose register designated
by Rs from the contents of the general-purpose register designated by Rd is nonpositive. If the result of the
subtraction is positive, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BLS
BLS
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0xFEDC
#0x9876
#0xCDEF
#0xFFFF
R0
R1
R2
R3
FEDCh
FEDCh 9876h
FEDCh 9876h CDEFh
FEDCh 9876h CDEFh FFFFh
PSW
0040h
1040h
2040h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h FEDCh 9876h CDEFh FFFFh 0008h
901Eh FEDCh 9876h CDEFh FFFFh 104Ch
-
LA:
-
-
-
-
-
-
LB:
9020h FEDCh 9876h CDEFh 0000h 300Fh
9022h FEDCh 9876h CDEFh 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-42
LC88 Series Chapter 5
BLS
Rx, #imm16, r8
[1 1 0 0 0 1 1 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C7000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of unsigned comparison is (Rx)≦#imm16, then (PC)←(PC)+4±(r8)
If result of unsigned comparison is (Rx) > #imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 from the contents
of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3) of the PSW is
nonpositive. If the result of the subtraction is positive, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0xCDEF
MOV.W R3, #0xFFFF
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
CDEFh
2040h
CDEFh FFFFh 3040h
loop:
MOV.W
BLS
MOV.W
BLS
BR
R0, #0xFEDC
900Ch FEDCh
CDEFh
Rx,#0xCDEF,LA ;; NOT JUMP LA 9010h FEDCh
CDEFh
R1, #0x9876
9014h FEDCh 9876h CDEFh
Rx,#0xCDEF,LB ;; JUMP LB
901Eh FEDCh 9876h CDEFh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
FFFFh
FFFFh
FFFFh
FFFFh
-
0040h
0008h
1048h
104Ch
-
-
-
LA:
-
-
-
-
LB:
9020h FEDCh 9876h CDEFh 0000h 300Fh
9022h FEDCh 9876h CDEFh 0000h 300Fh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-43
Instructions
BLT
r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 0 1 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S ^ OV = 1, then (PC)←(PC)+2±(r8)
If S ^ OV = 0, then (PC)←(PC)+2
D200H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the result of the exclusive logical OR of the sign flag (S) and the overflow flag
(OV) is 1. If the result of the logical operation is 0, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
MOV.W
R3, #0x0000
9002h
0000h
3003h
BLT
MOV.W
BLT
BR
LA
;; NOT JUMP LA
R3,#0xFFFF
LB
;; JUMP LB
loop
9004h
9008h
9010h
-
0000h
FFFFh
FFFFh
-
3003h
3040h
3040h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0000h
0000h
3003h
3003h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-44
LC88 Series Chapter 5
BLT
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 0 1 0 r11 to r8][r7 to r0]
20002000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd) < #imm8, then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd)≧#imm8, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
(signed 16-bit data) of the general-purpose register designated by Rd is negative. If the result of the
subtraction is nonnegative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x0056
#0x0034
#0x0056
#0xFFFF
BLT
BLT
BR
R0, #0x56, LA ;; NOT JUMP LA
R1, #0x56, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
0056h
0056h 0034h
0056h 0034h 0056h
0056h 0034h 0056h FFFFh
PSW
0000h
1020h
2000h
3040h
loop:
900Eh 0056h 0034h 0056h FFFFh 0003h
9018h 0056h 0034h 0056h FFFFh 104Ch
-
LA:
-
-
-
-
-
-
LB:
901Ah 0056h 0034h 0056h 0000h 300Fh
901Ch 0056h 0034h 0056h 0000h 300Fh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-45
Instructions
BLT
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 0 1 0 r11 to r8][r7 to r0]
0D002000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of signed comparison is (Rd) < (Rs), then (PC)←(PC)+4±(r12)
If result of signed comparison is (Rd)≧(Rs), then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents (signed 16-bit data) of the general-purpose
register designated by Rs from the contents (signed 16-bit data) of the general-purpose register designated by
Rd is negative. If the result of the subtraction is nonnegative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BLT
BLT
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x5678
#0xCDEF
#0x5678
#0xFFFF
R0
R1
R2
R3
5678h
5678h CDEFh
5678h CDEFh 5678h
5678h CDEFh 5678h FFFFh
PSW
0000h
1040h
2000h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 5678h CDEFh 5678h FFFFh 0003h
901Eh 5678h CDEFh 5678h FFFFh 1010h
-
LA:
-
-
-
-
-
-
LB:
9020h 5678h CDEFh 5678h 0000h 3013h
9022h 5678h CDEFh 5678h 0000h 3013h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-46
LC88 Series Chapter 5
BLT
Rx, #imm16, r8
[1 1 0 0 0 0 1 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C2000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of signed comparison is (Rx) < #imm16, then (PC)←(PC)+4±(r8)
If result of signed comparison is (Rx)≧#imm16, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 (signed 16-bit
data) from the contents (signed 16-bit data) of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW is negative. If the result of the subtraction is nonnegative, 4 is added to the
PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W R2, #0xCDEF
MOV.W R3, #0xFFFF
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
CDEFh
2040h
CDEFh FFFFh 3040h
loop:
MOV.W
BLT
MOV.W
BLT
BR
R0, #0x5678
900Ch 5678h
CDEFh
Rx, #0x5678, LA ;; NOT JUMP LA 9010h 5678h
CDEFh
R1, #0xCDEF
9014h 5678h CDEFh CDEFh
Rx, #0x5678, LB ;; JUMP LB
901Eh 5678h CDEFh CDEFh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
FFFFh
FFFFh
FFFFh
FFFFh
-
0000h
0003h
1040h
1010h
-
-
-
LA:
-
-
-
-
LB:
9020h 5678h CDEFh CDEFh 0000h 3013h
9022h 5678h CDEFh CDEFh 0000h 3013h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-47
Instructions
BMI
r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 0 1 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S = 1, then (PC)←(PC)+2±(r8)
If S = 0, then (PC)←(PC)+2
DA00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the sign flag (S) is 1. If the value of S is 0, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
MOV.W
R3, #0x000
9002h
0000h
3003h
BMI
MOV.W
BMI
BR
LA
;; NOT JUMP LA
R3,#0xFFFF
LB
;; JUMP LB
loop
9004h
9008h
9010h
-
0000h
FFFFh
FFFFh
-
3003h
3040h
3040h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0000h
0000h
3003h
3003h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-48
LC88 Series Chapter 5
BMI
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 0 1 0 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is S = 1, then (PC) ← (PC)+4±(r12)
If result of (Rd) - #imm8 is S = 0, then (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000A000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 1 as the result of subtracting immediate data designated
by imm8 from the contents of the general-purpose register designated by Rd. If S is set to 0 as the result of
the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ah
900Eh
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x9876
#0x5678
#0x0012
#0xFFFF
BMI
BMI
BR
R1, #0x12, LA ;; NOT JUMP LA
R0, #0x12, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
9876h
9876h 5678h
9876h 5678h 0012h
9876h 5678h 0012h FFFFh
PSW
0040h
1000h
2000h
3040h
loop:
9012h 9876h 5678h 0012h FFFFh 1000h
901Ch 9876h 5678h 0012h FFFFh 0040h
-
LA:
-
-
-
-
-
-
LB:
901Eh 9876h 5678h 0012h 0000h 3003h
9020h 9876h 5678h 0012h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-49
Instructions
BMI
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 0 1 0 r11 to r8][r7 to r0]
0D00A000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is S = 1, then (PC) ← (PC)+4±(r12)
If result of (Rd) – (Rs) is S = 0, then (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 1 as the result of subtracting the contents of the
general-purpose register designated by Rs from the contents of the general-purpose register designated by R.
If S is set to 0 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BMI
BMI
BR
R1, R2, LA
R0, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x9876
#0x5678
#0x1234
#0xFFFF
R0
R1
R2
R3
9876h
9876h 5678h
9876h 5678h 1234h
9876h 5678h 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 9876h 5678h 1234h FFFFh 1000h
901Eh 9876h 5678h 1234h FFFFh 0060h
-
LA:
-
-
-
-
-
-
LB:
9020h 9876h 5678h 1234h 0000h 3003h
9022h 9876h 5678h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-50
LC88 Series Chapter 5
BMI
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 0 1 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
CA000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) – #imm16 is S = 1 , then (PC) ← (PC)+4±(r8)
If result of (Rx) – #imm16 is S = 0 , then (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 1 as the result of subtracting immediate data designated
by imm16 from the contents of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to
N3) of the PSW. If S is set to 0 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
9004h
9008h
MOV.W
BMI
MOV.W
BMI
BR
R1, #0x5678
Rx, #0x1234, LA ;; NOT JUMP LA
R0, #0x9876
Rx, #0x1234, LB ;; JUMP LB
loop
900Ch
5678h
9010h
5678h
9014h 9876h 5678h
901Eh 9876h 5678h
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
1234h
1234h
1234h
1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
1000h
1000h
0040h
0060h
-
-
-
-
LA:
-
-
-
LB:
9020h 9876h 5678h 1234h 0000h 3003h
9022h 9876h 5678h 1234h 0000h 3003h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-51
Instructions
BN
m16, #imm3, r12
Instruction code
Argument
Word count
Cycle count
Function
[0 1 1 1 1 1 X 0][m7m6m5m4m3m2m1m0][0 i2i1i0 r11 to r8][r7 to r0]
7C00H(RAM), 7E00H(SFR)
m16 = 16bit(Lower 8bit valid for operation code), imm3 = 3bit(bit select)
r12 = 12bit(relative address, signed)
2
3 or 4
If (m16) of bit #imm3 = 0, then (PC)←(PC)+4±(r12)
If (m16) of bit #imm3 = 1, then (PC)←(PC)+4
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the bit designated by immediate data imm3 in the RAM (data memory) location
or the SFR (one of the registers dedicated to control the internal peripheral functions) designated by m16 is 0.
If the specified bit in the memory location m16 is 1, 4 is added to the PC.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH. The basic types of generated
instruction code are 7C00H (RAM) and 7E00H (SFR), respectively, The lower-order 8 bits of m16 are
reflected in the behavior of the instruction code.
The legitimate value range designated by imm3 is from 0 to 8ｈ and that by the relative address designated by
r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
MOV.W
MOV.W
0x50,#0x1221
R3, #0xFFFF
9004h
9008h
RAM
(51h)
12h
12h
BN
BN
BR
0x50, #0, LA ;; NOT JUMP LA
0x51, #0, LB ;; JUMP LB
loop
900Ch
9016h
-
12h
12h
-
21h
21h
-
FFFFh
FFFFh
-
DEC
BR
R3
loop
-
-
-
-
INC
NOP
R3
9018h
901Ah
12h
12h
21h
21h
0000h
0000h
PC
RAM
(50h)
21h
21h
FFFFh
R3
loop:
LA:
LB:
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-52
LC88 Series Chapter 5
BN
Rd, #imm4, r12
[0 0 0 0 0 1 0 0][i3i2i1i0d3d2d1d0][0 0 0 0 r11 to r8][r7 to r0]
0400H
Rd = 4bit(R select),imm4 = 4bit(bit select),r12 = 12bit(relative address, signed)
2
2 or 3
If (Rd) of bit #imm4 = 0, then (PC)←(PC)+4±(r12)
If (Rd) of bit #imm4 = 1, then (PC)←(PC)+4
N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the bit of the general-purpose register designated by Rd designated by immediate
data designated by imm4 is 0. If the specified bit of Rd is 1, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by imm4 is from 0 to 0Fh, and that by
the relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BN
BN
BR
R0, #0, LA
R1, #0, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9002h
9006h
9008h
900Ch
#0x0001
#0x1234
#0x0000
#0xFFFF
R0
R1
R2
R3
0001h
0001h 1234h
0001h 1234h 0000h
0001h 1234h 0000h FFFFh
PSW
0020h
1020h
2003h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9010h 0001h 1234h 0000h FFFFh 0040h
901Ah 0001h 1234h 0000h FFFFh 1040h
-
LA:
-
-
-
-
-
-
LB:
901Ch 0001h 1234h 0000h 0000h 3003h
901Eh 0001h 1234h 0000h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-53
Instructions
BN
Rd, Rs, r12
[0 0 0 0 0 1 1 0][s3s2s1s0d3d2d1d0][0 0 0 0 r11 to r8][r7 to r0]
0600H
Rd = 4bit(R select), Rs = 4bit(bit select), r12 = 12bit(relative address, signed)
2
2 or 3
If (Rd) of bit (Rs)&000Fh =0, then (PC)←(PC)+4±(r12)
If (Rd) of bit (Rs)&000Fh =1, then (PC)←(PC)+4
N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the bit of the general-purpose register Rd that is designated by the lower-order 4
bits of the general-purpose register designated by Rs is 0. If the specified bit of Rd is 1, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BN
BN
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9002h
9006h
9008h
900Ch
#0x0001
#0x1234
#0x0000
#0xFFFF
R0
R1
R2
R3
0001h
0001h 1234h
0001h 1234h 0000h
0001h 1234h 0000h FFFFh
PSW
0020h
1020h
2003h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9010h 0001h 1234h 0000h FFFFh 0040h
901Ah 0001h 1234h 0000h FFFFh 1040h
-
LA:
-
-
-
-
-
-
LB:
901Ch 0001h 1234h 0000h 0000h 3003h
901Eh 0001h 1234h 0000h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-54
LC88 Series Chapter 5
BNC r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 0 0 0 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If CY = 0, then (PC)←(PC)+2±(r8)
If CY = 1, then (PC)←(PC)+2
D100H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the carry flag (CY) is 0. If the value of CY is 1, 2 is added to the
PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W
MOV.W
RRC
R2, #0x0001
R3, #0xFFFF
R2, #1
BNC
RRC
BNC
BR
LA
R2, #1
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
PC
R2
R3
PSW
9002h
9006h
9008h
0001h
0001h
0000h
FFFFh
FFFFh
2020h
3040h
2007h
900Ah
900Ch
9014h
-
0000h
8000h
8000h
-
FFFFh
FFFFh
FFFFh
-
2007h
2061h
2061h
-
-
-
-
-
9016h
9018h
8000h
8000h
0000h
0000h
3003h
3003h
loop:
;; NOT JUMP LA
;; JUMP LB
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-55
Instructions
BNC
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][0 0 0 1 r11 to r8][r7 to r0]
20001000H
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd)≧#imm8, then (PC) ←(PC)+4±(r12)
If result of unsigned comparison is (Rd) < #imm8, then (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm8 from the contents
of the general-purpose register designated by Rd is nonnegative. If the result of the subtraction is negative, 4
is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9004h
9006h
900Ah
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x0012
#0x00CD
#0x0056
#0xFFFF
BNC
BNC
BR
R0, #0x56, LA ;; NOT JUMP LA
R1, #0x56, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
0012h
0012h 00CDh
0012h 00CDh 0056h
0012h 00CDh 0056h FFFFh
PSW
0000h
1020h
2000h
3040h
loop:
900Eh 0012h 00CDh 0056h FFFFh 006Ch
9018h 0012h 00CDh 0056h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
901Ah 0012h 00CDh 0056h 0000h 3003h
901Ch 0012h 00CDh 0056h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-56
LC88 Series Chapter 5
BNC
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][0 0 0 1 r11 to r8][r7 to r0]
0D001000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of unsigned comparison is (Rd)≧(Rs), then (PC) ←(PC)+4±(r12)
If result of unsigned comparison is (Rd) < (Rs), then (PC) ← (PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting the contents of the general-purpose register designated
by Rs from the contents of the general-purpose register designated by Rd is nonnegative. If the result of the
subtraction is negative, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BNC
BNC
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x1234
#0xCDEF
#0x5678
#0xFFFF
R0
R1
R2
R3
1234h
1234h CDEFh
1234h CDEFh 5678h
1234h CDEFh 5678h FFFFh
PSW
0020h
1040h
2000h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 1234h CDEFh 5678h FFFFh 006Ch
901Eh 1234h CDEFh 5678h FFFFh 1010h
-
LA:
-
-
-
-
-
-
LB:
9020h 1234h CDEFh 5678h 0000h 3013h
9022h 1234h CDEFh 5678h 0000h 3013h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-57
Instructions
BNC
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 0 0 0 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C1000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of unsigned comparison is (Rx)≧#imm16, then (PC) ←(PC)+4±(r8)
If result of unsigned comparison is (Rx) < #imm16, then (PC) ←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the result of subtracting immediate data designated by imm16 from the contents
of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3) of the PSW is
nonnegative. If the result of the subtraction is negative, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
-
-
MOV.W
MOV.W
R2, #0x5678
R3, #0xFFFF
9004h
9008h
MOV.W
BNC
MOV.W
BNC
BR
R0, #0x1234
Rx, #0x5678, LA ;; NOT JUMP LA
R1, #0xCDEF
Rx, #0x5678, LB ;; JUMP LB
loop
900Ch
9010h
9014h
901Eh
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
5678h
2000h
5678h FFFFh 3040h
loop:
1234h
5678h
1234h
5678h
1234h CDEFh 5678h
1234h CDEFh 5678h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
0020h
006Ch
104Ch
1010h
-
-
-
LA:
-
-
-
-
LB:
9020h 1234h CDEFh 5678h 0000h 3013h
9022h 1234h CDEFh 5678h 0000h 3013h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-58
LC88 Series Chapter 5
BNV r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 0 0 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If OV = 0 then (PC)←(PC)+2±(r8)
If OV = 1 then (PC)←(PC)+2
D900H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the overflow flag (OV) is 0. If the value of OV is 1, 2 is added to the
PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R2
R3
PSW
MOV.W
MOV.W
R2, #0x789A
R3, #0xFFFF
9004h
9008h
789Ah
789Ah FFFFh
2000h
3040h
ADD
BNV
ADD
BNV
BR
R2, #0x2345
LA
;; NOT JUMP LA
R2, #0x2345
LB
;; JUMP LB
loop
900Ch
900Eh
9012h
901Ah
-
9BDFh
9BDFh
BF24h
BF24h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
2050h
2050h
2068h
2068h
-
DEC
BR
R3
loop
-
-
-
-
INC
NOP
R3
0000h
0000h
300Bh
300Bh
loop:
LA:
LB:
901Ch BF24h
901Eh BF24h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-59
Instructions
BNV
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 0 0 1 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is OV=0, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is OV=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
20009000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the OV flag (OV) is set to 0 as the result of subtracting immediate data
designated by imm8 from the contents of the general-purpose register designated by Rd. If OV is set to 1 as
the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ah
900Eh
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x8000
#0x5678
#0x0012
#0xFFFF
BNV
BNV
BR
R0, #0x12, LA ;; NOT JUMP LA
R1, #0x12, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
8000h
8000h 5678h
8000h 5678h 0012h
8000h 5678h 0012h FFFFh
PSW
0061h
1000h
2000h
3040h
loop:
9012h 8000h 5678h 0012h FFFFh 0038h
901Ch 8000h 5678h 0012h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
901Eh 8000h 5678h 0012h 0000h 3003h
9020h 8000h 5678h 0012h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-60
LC88 Series Chapter 5
BNV
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 0 0 1 r11 to r8][r7 to r0]
0D009000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is OV=0, then (PC)←(PC)+4±(r12)
If result of (Rd) – (Rs) is OV=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the value of the overflow flag (OV) is set to 0 as the result of subtracting the
contents of the general-purpose register designated by Rs from the contents of the general-purpose register
designated by Rd. If OV is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BNV
BNV
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x89AB
#0x5678
#0x1234
#0xFFFF
R0
R1
R2
R3
89ABh
89ABh 5678h
89ABh 5678h 1234h
89ABh 5678h 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 89ABh 5678h 1234h FFFFh 0010h
901Eh 89ABh 5678h 1234h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
9020h 89ABh 5678h 1234h 0000h 3003h
9022h 89ABh 5678h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-61
Instructions
BNV
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 0 0 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
C9000000H
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is OV=0, then (PC)←(PC)+4±(r8)
If result of (Rx) - #imm16 is OV=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the value of the overflow flag (OV) is set to 0 as result of subtracting immediate
data designated by imm16 from the contents of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW. If OV is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
9004h
9008h
MOV.W
BNV
MOV.W
BNV
BR
R0, #0x8000
Rx, #0x1234, LA ;; NOT JUMP LA
R1, #0x5678
Rx, #0x1234, LB ;; JUMP LB
Loop
900Ch
9010h
9014h
901Eh
-
DEC
BR
R3
Loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
8000h
1234h
8000h
1234h
8000h 5678h 1234h
8000h 5678h 1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
0061h
0038h
1018h
1000h
-
-
-
LA:
-
-
-
-
LB:
9020h 8000h 5678h 1234h 0000h 3003h
9022h 8000h 5678h 1234h 0000h 3003h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-62
LC88 Series Chapter 5
BNZ r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 1 0 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If Z16 = 0, then (PC)←(PC)+2±(r8)
If Z16 = 1, then (PC)←(PC)+2
DD00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the16-bit operation flag (Z16) is 0. If the value of Z16 is 1, 2 is
added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
MOV.W
R3,
#0x0000
BNZ
MOV.W
BNZ
BR
LA
R3,#0x1234
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
PC
R3
PSW
-
-
-
9002h
0000h
3003h
9004h
9008h
9010h
-
0000h
1234h
1234h
-
3003h
3020h
3020h
-
-
-
-
9012h
9014h
1235h
1235h
3000h
3000h
loop:
;; NOT JUMP LA
;; JUMP LB
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-63
Instructions
BNZ
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 1 0 1 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is Z16 = 0, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is Z16 = 1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000D000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 0 as the result of subtracting immediate
data designated by imm8 from the contents of the general-purpose register designated by Rd. If Z16 is set to
1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that of the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
9002h
9006h
9008h
900Ch
#0x0034
#0x8234
#0x0034
#0xFFFF
R0
R1
R2
R3
0034h
0034h 8234h
0034h 8234h 0034h
0034h 8234h 0034h FFFFh
PSW
0020h
1060h
2020h
3040h
loop:
BR
R0,
LA
R1,
LB
loop
DEC
BR
R3
loop
INC
NOP
R3
BNZ
BNZ
#0x34,
#0x34,
;; NOT JUMP LA 9010h 0034h 8234h 0034h FFFFh 0003h
;; JUMP LB
901Ah 0034h 8234h 0034h FFFFh 1041h
-
-
-
-
-
-
-
-
-
-
-
-
LA:
LB:
901Ch 0034h 8234h 0034h 0000h 3003h
901Eh 0034h 8234h 0034h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-64
LC88 Series Chapter 5
BNZ
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 1 0 1 r11 to r8][r7 to r0]
0D00D000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - (Rs) is Z16 = 0, then (PC)←(PC)+4±(r12)
If result of (Rd) - (Rs) is Z16 = 1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 0 as the result of subtracting the contents
of the general-purpose register designated by Rs from the contents of the general-purpose register designated
by Rd. If Z16 is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that of the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BNZ
BNZ
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x1234
#0x8234
#0x1234
#0xFFFF
R0
R1
R2
R3
1234h
1234h 8234h
1234h 8234h 1234h
1234h 8234h 1234h FFFFh
PSW
0020h
1060h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 1234h 8234h 1234h FFFFh 0003h
901Eh 1234h 8234h 1234h FFFFh 1031h
-
LA:
-
-
-
-
-
-
LB:
9020h 1234h 8234h 1234h 0000h 3013h
9022h 1234h 8234h 1234h 0000h 3013h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-65
Instructions
BNZ
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 1 0 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is Z16 =0, then (PC)←(PC)+4±(r8)
If result of (Rx) - #imm16 is Z16 =1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
CD000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 0 as the result of subtracting immediate
data designated by imm16 from the contents of the general-purpose register Rx designated indirectly by bits
12 to 15 (N0 to N3) of the PSW. If Z16 is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that of the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
MOV.W
BNZ
MOV.W
BNZ
BR
R0, #0x1234
900Ch 1234h
1234h
Rx, #0x1234, LA ;; NOT JUMP LA 9010h 1234h
1234h
R1, #0x8234
9014h 1234h 8234h 1234h
Rx, #0x1234, LB ;; JUMP LB
901Eh 1234h 8234h 1234h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
FFFFh
FFFFh
FFFFh
FFFFh
-
0020h
0003h
1060h
1031h
-
-
-
LA:
-
-
-
-
LB:
9020h 1234h 8234h 1234h 0000h 3013h
9020h 1234h 8234h 1234h 0000h 3013h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-66
LC88 Series Chapter 5
BNZ．B
r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 1 0 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If Z8 = 0, then (PC)←(PC)+2±(r8)
If Z8 = 1, then (PC)←(PC)+2
DC00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the 8-bit operation flag (Z8) is 0. If the value of Z8 is 1, 2 is added
to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
1200h
3001h
MOV.W
R3, #0x1200
9004h
BNZ.B
MOV.W
BNZ.B
BR
LA
;;NOT JUMP LA
R3, #0x1234
LB
;;JUMP LB
loop
9006h
900Ah
9012h
-
1200h
1234h
1234h
-
3001h
3020h
3020h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9014h
9016h
1235h
1235h
3000h
3000h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-67
Instructions
BNZ．B
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 1 0 0 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is Z8 = 0, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is Z8 = 1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000C000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 0 as the result of subtracting immediate data
designated by imm8 from the contents of the general-purpose register designated by Rd. If Z8 is set to 1 as
the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that of the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ch
9010h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x5634
#0x8000
#0x1234
#0xFFFF
BNZ.B
BNZ.B
BR
R0, #0x34, LA ;; NOT JUMP LA
R1, #0x34, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
5634h
5634h 8000h
5634h 8000h 1234h
5634h 8000h 1234h FFFFh
PSW
0020h
1061h
2020h
3040h
loop:
9014h 5634h 8000h 1234h FFFFh 0001h
901Eh 5634h 8000h 1234h FFFFh 1038h
-
LA:
-
-
-
-
-
-
LB:
9020h 5634h 8000h 1234h 0000h 301Bh
9022h 5634h 8000h 1234h 0000h 301Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-68
LC88 Series Chapter 5
BNZ．B
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 1 0 0 r11 to r8][r7 to r0]
0D00C000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is Z8 = 0, then (PC)←(PC)+4±(r12)
If result of (Rd) – (Rs) is Z8 = 1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 0 as the result of subtracting the contents of
the general-purpose register designated by Rs from the contents of the general-purpose register designated by
Rd. If Z8 is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that of the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BNZ.B
BNZ.B
BR
R0, R2, LA
R1, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x5634
#0x8000
#0x1234
#0xFFFF
R0
R1
R2
R3
5634h
5634h 8000h
5634h 8000h 1234h
5634h 8000h 1234h FFFFh
PSW
0020h
1061h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 5634h 8000h 1234h FFFFh 0001h
901Eh 5634h 8000h 1234h FFFFh 1038h
-
LA:
-
-
-
-
-
-
LB:
9020h 5634h 8000h 1234h 0000h 301Bh
9022h 5634h 8000h 1234h 0000h 301Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-69
Instructions
BNZ．B
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 1 0 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) – #imm16 is Z8 = 0, then (PC)←(PC)+4±(r8)
If result of (Rx) – #imm16 is Z8 = 1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
CC000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 0 as the result of subtracting immediate data
designated by imm16 from the contents of the general-purpose register Rx designated indirectly by bits 12 to
15 (N0 to N3) of the PSW. If Z8 is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that of the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
9004h
9008h
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
MOV.W
BNZ.B
MOV.W
BNZ.B
BR
R0, #0x5634
900Ch
Rx, #0x1234, LA ;; NOT JUMP LA 9010h
R1, #0x8000
9014h
Rx, #0x1234, LB ;; JUMP LB
901Eh
loop
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
5634h
1234h
5634h
1234h
5634h 8000h 1234h
5634h 8000h 1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
0020h
0001h
1061h
1038h
-
-
-
LA:
-
-
-
-
LB:
9020h 5634h 8000h 1234h
9022h 5634h 8000h 1234h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-70
0000h 301Bh
0000h 301Bh
LC88 Series Chapter 5
BP
m16, #imm3, r12
Instruction code
Argument
Word count
Cycle count
Function
[0 1 1 1 1 1 X 1][m7m6m5m4m3m2m1m0][0 i2i1i0 r11 to r8][r7 to r0]
7D00H(RAM), 7F00H(SFR)
m16 = 16bit(Lower 8bit valid for operation code), imm3 = 3bit(bit select)
r12 = 12bit(relative address, signed)
2
3 or 4
if (m16) of bit #imm3 = 1, then (PC)←(PC)+4±(r12)
if (m16) of bit #imm3 = 0, then (PC)←(PC)+4
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC, if the bit indicated by immediate data designated by imm3 in the data memory
location designated by m16, is 1. If the bit designated by m16 is 0, 4 is added to the PC.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH.
The basic types of generated instruction code are 7D00H (RAM) and 7F00H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
The legitimate value range designated by imm3 is from 0 to 8ｈ and that of the relative address designated by
r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
MOV.W
MOV.W
0x50, #01221
R3, #0FFFF
9004h
9008h
RAM
(51h)
12h
12h
BP
BP
BR
0x51, #0, LA ;; NOT JUMP LA
0x50, #0, LB ;; JUMP LB
loop
900Ch
9016h
-
12h
12h
-
21h
21h
-
FFFFh
FFFFh
-
DEC
BR
R3
loop
-
-
-
-
INC
NOP
R3
9018h
901Ah
12h
12h
21h
21h
0000h
0000h
PC
RAM
(50h)
21h
21h
FFFFh
R3
loop:
LA:
LB:
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-71
Instructions
BP
Rd, #imm4, r12
[0 0 0 0 0 1 0 1][i3i2i1i0d3d2d1d0][0 0 0 0 r11 to r8][r7 to r0]
0500H
Rd = 4bit(R select), imm4 = 4bit(bit select), r12 = 12bit(relative address, signed)
2
2 or 3
If (Rd) of bit #imm4 = 1, then (PC)←(PC)+4±(r12)
If (Rd) of bit #imm4 =0, then (PC)←(PC)+4
N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the bit, in the contents of the general-purpose register designated by Rd, that is
specified by immediate data designated by imm4 is 1. If the bit specified in the contents of Rd is 0, 4 is added
to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by imm4 is from 0 to 0Fh, and that by
the relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BP
BP
BR
R1, #0, LA
R0, #0, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9002h
9006h
9008h
900Ch
#0x0001
#0x1234
#0x0000
#0xFFFF
R0
R1
R2
R3
0001h
0001h 1234h
0001h 1234h 0000h
0001h 1234h 0000h FFFFh
PSW
0020h
1020h
2003h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9010h 0001h 1234h 0000h FFFFh 1040h
901Ah 0001h 1234h 0000h FFFFh 0040h
-
LA:
-
-
-
-
-
-
LB:
901Ch 0001h 1234h 0000h 0000h 3003h
901Eh 0001h 1234h 0000h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-72
LC88 Series Chapter 5
BP
Rd, Rs, r12
[0 0 0 0 0 1 1 1][s3s2s1s0d3d2d1d0][0 0 0 0 r11 to r8][r7 to r0]
0700H
Rd = 4bit(R select), Rs = 4bit(bit select), r12 = 12bit(relative address, signed)
2
2 or 3
If (Rd) of bit (Rs)&000Fh =1, then (PC)←(PC)+4±(r12)
If (Rd) of bit (Rs)&000Fh =0, then (PC)←(PC)+4
N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the bit, in the contents of the general-purpose register designated by Rd, that is is
specified by the lower-order 4 bits of the general-purpose register designated by Rs is 1. If the specified bit of
Rd is 0, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BP
BP
BR
R1, R2, LA
R0, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9002h
9006h
9008h
900Ch
#0x0001
#0x1234
#0x0000
#0xFFFF
R0
R1
R2
R3
0001h
0001h 1234h
0001h 1234h 0000h
0001h 1234h 0000h FFFFh
PSW
0020h
1020h
2003h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9010h 0001h 1234h 0000h FFFFh 1040h
901Ah 0001h 1234h 0000h FFFFh 0040h
-
LA:
-
-
-
-
-
-
LB:
901Ch 0001h 1234h 0000h 0000h 3003h
901Eh 0001h 1234h 0000h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-73
Instructions
BPL r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 0 0 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If S = 0, then (PC)←(PC)+2±(r8)
If S = 1, then (PC)←(PC)+2
D800H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the sign flag (S) is 0. If the value of S is 1, 2 is added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
-
-
-
MOV.W
R3,
#0xFFFF
9004h
FFFFh
3040h
BPL
MOV.W
BPL
BR
LA
;; NOT JUMP LA
R3, #0x0000
LB
;; JUMP LB
loop
9006h
9008h
9010h
-
FFFFh
0000h
0000h
-
3040h
3003h
3003h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0001h
0001h
3020h
3020h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-74
LC88 Series Chapter 5
BPL
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 0 0 0 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is S=0, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is S=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
20008000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 0 as the result of subtracting immediate data designated
by imm8 from the contents of the general-purpose register designated by Rd. If S is set to 1 as the result of
the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R7, that by imm8 is from 0 to FFh, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ah
900Eh
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x9876
#0x5678
#0x0012
#0xFFFF
BPL
BPL
BR
R0, #0x12, LA ;; NOT JUMP LA
R1, #0x12, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
9876h
9876h 5678h
9876h 5678h 0012h
9876h 5678h 0012h FFFFh
PSW
0040h
1000h
2000h
3040h
loop:
9012h 9876h 5678h 0012h FFFFh 0040h
901Ch 9876h 5678h 0012h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
901Eh 9876h 5678h 0012h 0000h 3003h
9020h 9876h 5678h 0012h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-75
Instructions
BPL
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 0 0 0 r11 to r8][r7 to r0]
0D008000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - (Rs) is S=0, then (PC)←(PC)+4±(r12)
If result of (Rd) - (Rs) is S=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 0 as the result of subtracting the contents of the
general-purpose register designated by Rs from the contents of the general-purpose register designated by Rd.
If S is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R15, and that by the
relative address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BPL
BPL
BR
R0, R2, LA
R1, R2, LB
Loop
DEC
BR
R3
Loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x9876
#0x5678
#0x1234
#0xFFFF
R0
R1
R2
R3
9876h
9876h 5678h
9876h 5678h 1234h
9876h 5678h 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 9876h 5678h 1234h FFFFh 0060h
901Eh 9876h 5678h 1234h FFFFh 1000h
-
LA:
-
-
-
-
-
-
LB:
9020h 9876h 5678h 1234h 0000h 3003h
9022h 9876h 5678h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-76
LC88 Series Chapter 5
BPL
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 0 0 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is S=0, then (PC)←(PC)+4±(r8)
If result of (Rx) - #imm16 is S=1, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
C8000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the sign flag (S) is set to 0 as the result of subtracting immediate data designated
by imm16 from the contents of the general-purpose register Rx designated indirectly by the value of bits 12
to 15 (N0 to N3) of the PSW. If S is set to 1 as the result of the subtraction, 4 is added to the PC.
The legitimate value range designated by imm16 is from 0 to FFFFh, and that by the relative address
designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
9004h
9008h
-
-
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
MOV.W
BPL
MOV.W
BPL
BR
R0, #0x9876
900Ch 9876h
1234h
Rx, #0x1234, LA ;; NOT JUMP LA 9010h 9876h
1234h
R1, #0x5678
9014h 9876h 5678h 1234h
Rx, #0x1234, LB ;; JUMP LB
901Eh 9876h 5678h 1234h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
loop:
FFFFh
FFFFh
FFFFh
FFFFh
-
0040h
0060h
1000h
1000h
-
-
-
LA:
-
-
-
-
LB:
9020h 9876h 5678h 1234h 0000h 3003h
9022h 9876h 5678h 1234h 0000h 3003h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-77
Instructions
BR r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 1 r11r10r9r8][r7r6r5r4r3r2r1 0]
r12 = 12bit(relative address, signed)
1
2
(PC)←(PC)+2±(r12)
1000H
[Description]
This instruction adds the value of the relative address designated by r12 + 2 to the program counter (PC) and
places the result in the PC.
The legitimate value range of the relative address designated by r12 is that of signed 12-bit data (-2078 to
2047).
[Example] The value of label LA is 9106H.
MOV.W
R3, #0x0200
BR
NOP
NOP
.
.
.
LA
INC
NOP
R3
PC
R3
PSW
9004h
0200h
3021h
9106h
-
0200h
-
3021h
-
9108h
910Ah
0201h
0201h
3000h
3000h
loop:
;; JUMP LA
LA:
5-78
LC88 Series Chapter 5
BR
Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 1 0 s3s2s1s0]
Rs = 4bit(relative address, signed)
1
2
(PC)←(PC)+2±(Rs)
0020H
[Description]
This instruction adds the value of the relative address (the contents of the general-purpose register designated
by Rs) + 2 to the program counter (PC) and places the result in the PC
The legitimate value range odesignated by Rs is from R0 to R15, and that by the relative address (the
contents of the general-purpose register designated by Rs) is that of signed 16-bit data (-32768 to 32767).
[Example] The value of label LA is 9106H.
MOV.W
R3, #0x0100
BR
NOP
NOP
.
.
.
R3
INC
NOP
R3
PC
R3
PSW
9004h
0100h
3021h
9106h
-
0100h
-
3021h
-
9108h
910Ah
0101h
0101h
3000h
3000h
loop:
;; JUMP LA
LA:
5-79
Instructions
BRK
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 0 1 0 1]
0005H
1
1
(PC)←(PC): This instruction sequence 1 time
[Description]
This instruction halts the program counter (PC) while preserving the current CPU state. The halt state can be
reset by generating an interrupt or reset.
5-80
LC88 Series Chapter 5
BV r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 0 1 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If OV = 1, then (PC)←(PC)+2±(r8)
If OV = 0, then (PC)←(PC)+2
DB00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the overflow flag (OS) is 1. If the value of OV is 0, 2 is added to the
PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R2
R3
MOV.W
MOV.W
R2, #0x789A
R3, #0xFFFF
9004h
9008h
ADD
BV
ADD
BV
BR
R2, #0x0234
LA
;; NOT JUMP LA
R2, #0x2345
LB
;; JUMP LB
loop
900Ch 7ACEh FFFFh
900Eh 7ACEh FFFFh
9012h 9E13h FFFFh
901Ah 9E13h FFFFh
-
DEC
BR
R3
loop
INC
NOP
R3
PSW
789Ah
789Ah FFFFh
2000h
3040h
2000h
2000h
2058h
2058h
-
loop:
LA:
-
-
-
-
901Ch
901Eh
9E13h
9E13h
0000h
0000h
301Bh
301Bh
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-81
Instructions
BV
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 0 1 1 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is OV = 1, then (PC) ←(PC)+4±(r12)
If result of (Rd) - #imm8 is OV = 0, then (PC) ←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000B000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the overflow flag (OV) is set to 1 as the result of subtracting immediate data
imm8 from the contents of the general-purpose register Rd. If OV is set to 0 as the result of the subtraction, 4
is added to the PC.
The legitimate value range of Rd is from R0 to R7, that of imm8 is from 0 to FFh, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ah
900Eh
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x8000
#0x5678
#0x0012
#0xFFFF
BV
BV
BR
R1, #0x12, LA ;; NOT JUMP LA
R0, #0x12, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
8000h
8000h 5678h
8000h 5678h 0012h
8000h 5678h 0012h FFFFh
PSW
0061h
1000h
2000h
3040h
loop:
9012h 8000h 5678h 0012h FFFFh 1000h
901Ch 8000h 5678h 0012h FFFFh 0038h
-
LA:
-
-
-
-
-
-
LB:
901Eh 8000h 5678h 0012h 0000h 301Bh
9020h 8000h 5678h 0012h 0000h 301Bh
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-82
LC88 Series Chapter 5
BV
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 0 1 1 r11 to r8][r7 to r0]
0D00B000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is OV = 1, then (PC) ←(PC)+4±(r12)
If result of (Rd) – (Rs) is OV= 0, then (PC) ←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the overflow flag (OV) is set to 1 as the result of subtracting the contents of the
general-purpose register Rs from the contents of the general-purpose register Rd. If OV is set to 0 as the
result of the subtraction, 4 is added to the PC.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R15, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BV
BV
BR
R1, R2, LA
R0, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x89AB
#0x5678
#0x1234
#0xFFFF
R0
R1
R2
R3
89ABh
89ABh 5678h
89ABh 5678h 1234h
89ABh 5678h 1234h FFFFh
PSW
0040h
1000h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 89ABh 5678h 1234h FFFFh 1000h
901Eh 89ABh 5678h 1234h FFFFh 0010h
-
LA:
-
-
-
-
-
-
LB:
9020h 89ABh 5678h 1234h 0000h 3013h
9022h 89ABh 5678h 1234h 0000h 3013h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-83
Instructions
BV
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 0 1 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is OV = 1, then (PC) ←(PC)+4±(r8)
If result of (Rx) - #imm16 is OV = 0, then (PC) ←(PC)+4
Z8, Z16, CY, HC, OV, P, S
CB000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the overflow flag (OV) is set to 1 as the result of subtracting immediate data
imm16 from the contents of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3)
of the PSW. If OV is set to 0 as the result of the subtraction, 4 is added to the PC.
The legitimate value range of imm16 is from 0 to FFFFh, and that of the relative address designated by r8 is
that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
9004h
9008h
MOV.W
BV
MOV.W
BV
BR
R1, #0x5678
Rx, #0x1234, LA ;; NOT JUMP LA
R0, #0x8000
Rx, #0x1234, LB ;; JUMP LB
loop
900Ch
5678h
9010h
5678h
9014h 8000h 5678h
901Eh 8000h 5678h
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
1234h
1234h
1234h
1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
1000h
1000h
0061h
0038h
-
-
-
-
LA:
-
-
-
LB:
9020h 8000h 5678h 1234h 0000h 301Bh
9022h 8000h 5678h 1234h 0000h 301Bh
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-84
LC88 Series Chapter 5
BZ r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 1 1 1][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If Z16 = 1, then (PC)←(PC)+2±(r8)
If Z16 = 0, then (PC)←(PC)+2
DF00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the 16-bit operation flag (Z16) is 1. If the value of Z16 is 0, 2 is
added to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
1234h
3020h
MOV.W
R3, #0x1234
9004h
BZ
MOV.W
BZ
BR
LA
;; NOT JUMP LA
R3, #0x0000
LB
;; JUMP LB
loop
9006h
9008h
9010h
-
1234h
0000h
0000h
-
3020h
3003h
3003h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9012h
9014h
0001h
0001h
3020h
3020h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-85
Instructions
BZ
Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 1 1 1 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is Z16 = 1, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is Z16 = 0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000F000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 1 as the result of subtracting immediate
data imm8 from the contents of the general-purpose register Rd. If Z16 is set to 0 as the result of the
subtraction, 4 is added to the PC.
The legitimate value range of Rd is from R0 to R7, that of imm8 is from 0 to FFh, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9002h
9006h
9008h
900Ch
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x0034
#0x8234
#0x0034
#0xFFFF
BZ
BZ
BR
R1, #0x34, LA ;; NOT JUMP LA
R0, #0x34, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
0034h
0034h 8234h
0034h 8234h 0034h
0034h 8234h 0034h FFFFh
PSW
0020h
1060h
2020h
3040h
loop:
9010h 0034h 8234h 0034h FFFFh 1041h
901Ah 0034h 8234h 0034h FFFFh 0003h
-
LA:
-
-
-
-
-
-
LB:
901Ch 0034h 8234h 0034h 0000h 3003h
901Eh 0034h 8234h 0034h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-86
LC88 Series Chapter 5
BZ
Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 1 1 1 r11 to r8][r7 to r0]
0D00F000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is Z16 = 1, then (PC)←(PC)+4±(r12)
If result of (Rd) – (Rs) is Z16 = 0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 1 as the result of subtracting the contents
of the general-purpose register Rs from the contents of the general-purpose register Rd. If Z16 is set to 0 as
the result of the subtraction, 4 is added to the PC.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R15, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BZ
BZ
BR
R1, R2, LA
R0, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x1234
#0x8234
#0x1234
#0xFFFF
R0
R1
R2
R3
1234h
1234h 8234h
1234h 8234h 1234h
1234h 8234h 1234h FFFFh
PSW
0020h
1060h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 1234h 8234h 1234h FFFFh 1031h
901Eh 1234h 8234h 1234h FFFFh 0003h
-
LA:
-
-
-
-
-
-
LB:
9020h 1234h 8234h 1234h 0000h 3003h
9022h 1234h 8234h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-87
Instructions
BZ
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 1 1 1][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is Z16 = 1, then (PC)←(PC)+4±(r8)
If result of (Rx) - #imm16 is Z16 = 0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
CF000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the 16-bit operation flag (Z16) is set to 1 as the result of subtracting immediate
data imm16 from the contents of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to
N3) of the PSW. If Z16 is set to 0 as the result of the subtraction, 4 is added to the PC.
The legitimate value range of imm16 is from 0 to FFFFh, and that of the relative address designated by r8 is
that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
9004h
9008h
MOV.W
BZ
MOV.W
BZ
BR
R1, #0x8234
Rx, #0x1234, LA ;; NOT JUMP LA
R0, #0x1234
Rx, #0x1234, LB ;; JUMP LB
loop
900Ch
8234h
9010h
8234h
9014h 1234h 8234h
901Eh 1234h 8234h
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
1234h
1234h
1234h
1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
1060h
1031h
0030h
0003h
-
-
-
-
LA:
-
-
-
LB:
9020h 1234h 8234h 1234h 0000h 3003h
9020h 1234h 8234h 1234h 0000h 3003h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-88
LC88 Series Chapter 5
BZ． B r8
Instruction code
Argument
Word count
Cycle count
Function
[1 1 0 1 1 1 1 0][r7r6r5r4r3r2r1r0]
r8 = 8bit(relative address, signed)
1
2 or 3
If Z8 = 1, then (PC)←(PC)+2± (r8)
If Z8 = 0, then (PC)←(PC)+2
DE00H
Affected flags
[Description]
This instruction adds the value of the relative address designated by r8 + 2 to the program counter (PC) and
places the result in the PC if the value of the 8-bit operation flag (Z8) is 1. If the value of Z8 is 0, 2 is added
to the PC.
The legitimate value range of the relative address designated by r8 is that of signed 8-bit data (-128 to 127).
[Example]
PC
R3
PSW
1234h
3020h
MOV.W
R3, #0x1234
9004h
BZ.B
MOV.W
BZ.B
BR
LA
;; NOT JUMP LA
R3, #0x1200
LB
;; JUMP LB
loop
9006h
900Ah
9012h
-
1234h
1200h
1200h
-
3020h
3001h
3001h
-
DEC
BR
R3
loop
-
-
-
INC
NOP
R3
9014h
9016h
1201h
1201h
3020h
3020h
loop:
LA:
LB:
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-89
Instructions
BZ．B Rd, #imm8, r12
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 0][i7i6i5i4i3i2i1i0][1 1 1 0 r11 to r8][r7 to r0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) - #imm8 is Z8 =1, then (PC)←(PC)+4±(r12)
If result of (Rd) - #imm8 is Z8 =0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
2000E000H
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 1 as the result of subtracting immediate data
imm8 from the contents of the general-purpose register Rd. If Z8 is set to 0 as the result of the subtraction, 4
is added to the PC.
The legitimate value range of Rd is from R0 to R7, that of imm8 is from 0 to FFh, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
9004h
9008h
900Ch
9010h
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
#0x5634
#0x8000
#0x1234
#0xFFFF
BZ.B
BZ.B
BR
R1, #0x34, LA ;; NOT JUMP LA
R0, #0x34, LB ;; JUMP LB
loop
DEC
BR
R3
loop
INC
NOP
R3
R0
R1
R2
R3
5634h
5634h 8000h
5634h 8000h 1234h
5634h 8000h 1234h FFFFh
PSW
0020h
1061h
2020h
3040h
loop:
9014h 5634h 8000h 1234h FFFFh 1038h
901Eh 5634h 8000h 1234h FFFFh 0001h
-
LA:
-
-
-
-
-
-
LB:
9020h 5634h 8000h 1234h 0000h 3003h
9022h 5634h 8000h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-90
LC88 Series Chapter 5
BZ．B Rd, Rs, r12
[0 0 0 0 1 1 0 1][s3s2s1s0d3d2d1d0][1 1 1 0 r11 to r8][r7 to r0]
0D00E000H
Rd = 4bit(R select), Rs = 4bit(R select), r12 = 12bit(relative address, signed)
2
2 or 3
If result of (Rd) – (Rs) is Z8 =1, then (PC)←(PC)+4±(r12)
If result of (Rd) – (Rs) is Z8 =0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S, N0 to N3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[Description]
This instruction adds the value of the relative address designated by r12 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 1 as the result of subtracting the contents of
the general-purpose register Rs from the contents of the general-purpose register Rd. If Z8 is set to 0 as the
result of the subtraction, 4 is added to the PC.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R15, and that of the relative
address designated by r12 is that of signed 12-bit data (-2048 to 2047).
[Example]
PC
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
BZ.B
BZ.B
BR
R1, R2, LA
R0, R2, LB
loop
DEC
BR
R3
loop
INC
NOP
R3
9004h
9008h
900Ch
9010h
#0x5634
#0x8000
#0x1234
#0xFFFF
R0
R1
R2
R3
5634h
5634h 8000h
5634h 8000h 1234h
5634h 8000h 1234h FFFFh
PSW
0020h
1061h
2020h
3040h
loop:
;; NOT JUMP LA
;; JUMP LB
9014h 5634h 8000h 1234h FFFFh 1038h
901Eh 5634h 8000h 1234h FFFFh 0001h
-
LA:
-
-
-
-
-
-
LB:
9020h 5634h 8000h 1234h 0000h 3003h
9022h 5634h 8000h 1234h 0000h 3003h
<Note>
This instruction takes 3 cycles to execute if the conditions are met.
5-91
Instructions
BZ．B
Rx, #imm16, r8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 0 0 1 1 1 0][r7r6r5r4r3r2r1r0][i15 to i8][i7 to i0]
imm16 = 16bit(immediate data), r8 = 8bit(relative address, signed)
2
3 or 4
If result of (Rx) - #imm16 is Z8 =1, then (PC)←(PC)+4±(r8)
If result of (Rx) - #imm16 is Z8 =0, then (PC)←(PC)+4
Z8, Z16, CY, HC, OV, P, S
CE000000H
[Description]
This instruction adds the value of the relative address designated by r8 + 4 to the program counter (PC) and
places the result in the PC if the 8-bit operation flag (Z8) is set to 1 as the result of subtracting immediate data
imm16 from the contents of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3)
of the PSW. If Z8 is set to 0 as the result of the subtraction, 4 is added to the PC.
The legitimate value range of imm16 is from 0 to FFFFh, and that of the relative address designated by r8 is
that of signed 8-bit data (-128 to 127).
[Example]
PC
R0
R1
9004h
9008h
-
-
MOV.W
MOV.W
R2, #0x1234
R3, #0xFFFF
MOV.W
BZ.B
MOV.W
BZ.B
BR
R1, #0x8000
900Ch
8000h
Rx, #0x1234, LA ;; NOT JUMP LA 9010h
8000h
R0, #0x5634
9014h 5634h 8000h
Rx, #0x1234, LB ;; JUMP LB
901Eh 5634h 8000h
loop
-
DEC
BR
R3
loop
INC
NOP
R3
R2
R3
PSW
1234h
2020h
1234h FFFFh 3040h
loop:
1234h
1234h
1234h
1234h
-
FFFFh
FFFFh
FFFFh
FFFFh
-
1061h
1038h
0038h
0001h
-
-
-
-
LA:
-
-
-
LB:
9020h 5634h 8000h 1234h
9022h 5634h 8000h 1234h
<Note>
This instruction takes 4 cycles to execute if the conditions are met.
5-92
0000h 3003h
0000h 3003h
LC88 Series Chapter 5
CALL
Rb, Rs
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][1 0 1 b0 s3s2s1s0]
Rb = 1bit(absolute address), Rs = 4bit(absolute address)
1
4
(SP)←(SP)+4: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h)
(PC)←(Rb<<16+Rs)
00A0H
Affected flags
[Description]
This instruction stores the address of the instruction following this CALL instruction (return address) in the
data memory location (RAM) designated by the stack pointer (SP) and increments the SP. Finally, the
instruction places the absolute address (of which the higher-order 16 bits are the contents of the
general-purpose register designated by the base register (Rb) and the lower-order 16 bits are the contents of
Rs) in the program counter (PC).
The legitimate values of Rb is R8 and R9, and the legitimate value range of Rs is from R0 to R15.
[Example] The value of label LA is 910AH.
MOV.W R15, #0x0000
MOV.W R3, #0x910A
RAM RAM RAM RAM
R3
(00h) (01h) (02h) (03h)
9004h
9004h
910Ah
MOV.W R8, #0x0000
9008h
PC
-
R8
-
PSW
SP
F003h 0000h
3060h 0000h
-
-
910Ah 0000h 8003h 0000h
;; CALL LA 910Ah
0Ah
90h
00h
00h 910Ah 0000h 8003h 0004h
9010h
0Ah
90h
00h
00h
910Ch 0000h 3060h 0000h
9012h
0Ah
90h
00h
00h
910Ch 0000h 3060h 0000h
910Ch
0Ah
90h
00h
00h
910Bh 0000h 3040h 0004h
900Eh
0Ah
90h
00h
00h
910Bh 0000h 3040h 0000h
loop:
CALL
R8, R3
INC
R3
NOP
.
.
.
LA:
INC
RET
R3
5-93
Instructions
CALLF
a24
[0 0 0 0 0 0 0 1][a7a6a5a4a3a2a1a0][a23 to a16][a15 to a8]
a24 = 24bit(absolute address)
2
4
(SP)←(SP)+4: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h)
(PC)←(a24)
Instruction code
Argument
Word count
Cycle count
Function
0100H
Affected flags
[Description]
This instruction stores the address of the instruction following this CALL instruction (return address) in the
data memory location (RAM) designated by the stack pointer (SP) and increments the SP. Finally, the
instruction places the absolute address (a24) in the program counter (PC).
The legitimate value range of a24 is from 0 to FF＿FFFFｈ.
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM
R3
PSW
SP
(00h) (01h) (02h) (03h)
9004h
F003h 0000h
9008h
FFFFh 3040h 0000h
PC
MOV.W R15, #0x0000
MOV.W R3, #0xFFFF
loop:
CALLF LA
INC
R3
NOP
.
.
.
;; CALL LA 910Ah 0Ch
900Eh 0Ch
9010h 0Ch
90h
90h
90h
00h
00h
00h
00h
00h
00h
FFFFh 3040h 0004h
0001h 3020h 0000h
0001h 3020h 0000h
910Ch 0Ch
900Ch 0Ch
90h
90h
00h
00h
00h
00h
0000h 3003h 0004h
0000h 3003h 0000h
LA:
INC
RET
R3
5-94
LC88 Series Chapter 5
CALLR r12
[0 0 0 1 r11r10r9r8][r7r6r5r4r3r2r1 1]
r12 = 12bit(relative address, signed)
1
4
(SP)←(SP)+4: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h)
(PC)←(PC)+2±(r12)
Instruction code
Argument
Word count
Cycle count
Function
1001H
Affected flags
[Description]
This instruction stores the address of the instruction following this CALL instruction (return address) in the
data memory location (RAM) designated by the stack pointer (SP) and increments the SP. Finally, the
instruction adds the value of the relative address (r12) + 2 to the program counter (PC) and places the result
in the PC.
The legitimate value range of the relative address designated by r12 is that of signed 12-bit data (-2048 to
2047).
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM
R3
PSW
SP
(00h) (01h) (02h) (03h)
9004h
F003h 0000h
9008h
FFFFh 3040h 0000h
PC
MOV.W R15, #0x0000
MOV.W R3, #0xFFFF
loop:
CALLR LA
INC
R3
NOP
.
.
.
;; CALL LA 910Ah 0Ah
900Ch 0Ah
900Eh 0Ah
90h
90h
90h
00h
00h
00h
00h
00h
00h
FFFFh 3040h 0004h
0001h 3020h 0000h
0001h 3020h 0000h
910Ch 0Ah
900Ah 0Ah
90h
90h
00h
00h
00h
00h
0000h 3003h 0004h
0000h 3003h 0000h
LA:
INC
RET
R3
<Note>
The value of the relative address (r) is valid if it is in the value range of signed 12-bit data (-2048 to +2047).
5-95
Instructions
CALLR Rs
[0 0 0 0 0 0 0 0][0 0 0 1 s3s2s1s0]
Rs = 4bit(relative address, signed)
1
4
(SP)←(SP)+4: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h)
(PC)←(PC)+2±(Rs)
Instruction code
Argument
Word count
Cycle count
Function
0010H
Affected flags
[Description]
This instruction stores the address of the instruction following this CALL instruction (return address) in the
data memory location (RAM) designated by the stack pointer (SP) and increments the SP. Finally the
instruction adds the value of the relative address (the contents of the general-purpose register Rs) + 2 to the
program counter (PC) and places the result in the PC.
The legitimate value range of Rs is from R0 to R15.
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM
R3
PSW
SP
(00h) (01h) (02h) (03h)
9004h
F003h 0000h
9008h
0100h 3021h 0000h
PC
MOV.W R15, #0x0000
MOV.W R3, #0x0100
loop:
CALLR R3
INC
R3
NOP
.
.
.
;; CALL LA 910Ah 0Ah
900Ch 0Ah
900Eh 0Ah
90h
90h
90h
00h
00h
00h
00h
00h
00h
0100h 3021h 0004h
0102h 3000h 0000h
0102h 3000h 0000h
910Ch 0Ah
900Ah 0Ah
90h
90h
00h
00h
00h
00h
0101h 3000h 0004h
0101h 3000h 0000h
LA:
INC
RET
R3
<Note>
The value of the relative address (Rs) is valid if it is in the value range of signed 16-biｔ data (-32768 to
+32767).
5-96
LC88 Series Chapter 5
CBW Rd
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 0 1 0 d3d2d1d0]
Rd = 4bit(R select)
1
1
if (Rd) of bit7 = 1, then Hibyte(Rd) = FFh
if (Rd) of bit7 = 0, then Hibyte(Rd) = 00h
Z8, Z16, P, S, N0 to N3
30A0H
[Description]
This instruction extends arithmetic 8-bit data into 16-bit data regarding bit 7 of the general-purpose register
Rd as the sign bit.
The legitimate value range of Rd is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CBW
CBW
CBW
CBW
R0,
R1,
R2,
R3,
R0
R1
R2
R3
#0x2345
#0xFEDC
#0x8888
#0x5500
R0
R1
R2
R3
2345h
2345h
2345h
2345h
0045h
0045h
0045h
0045h
FEDCh
FEDCh
FEDCh
FEDCh
FFDCh
FFDCh
FFDCh
8888h
8888h
8888h
8888h
FF88h
FF88h
5500h
5500h
5500h
5500h
0000h
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
<Note>
The higher-order 8 bits are set to FFH if bit 7 of Rd is 1 and to 00H if bit 7 is 0.
5-97
Instructions
CLR1
m16, #imm3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 1 X i2i1i0 0][m7m6m5m4m3m2m1m0]
E000H(RAM), F000H(SFR)
m16 = 16bit(Lower 8bit valid for operation code), imm3 = 3bit(bit select)
1
2
(m16) of bit #imm3 ← 0, (PC)←(PC)+2
Z8, Z16, P, S
[Description]
This instruction zero clears the bit designated by immediate data imm3 in the data memory location m16.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH.
The basic types of generated instruction code are E000H (RAM) and F000H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
The legitimate value range of imm3 is from 0 to 7ｈ.
[Example]
MOV.B
MOV.B
MOV.B
MOV.B
CLR1
CLR1
CLR1
CLR1
0x50,
0x51,
0x52,
0x53,
0x50,
0x51,
0x52,
0x53,
#0xFF
#0x33
#0x00
#0x54
#0x02
#0x00
#0x04
#0x04
RAM RAM RAM RAM
(50h) (51h) (52h) (53h)
FFh
FFh
33h
FFh
33h
00h
FFh
33h
00h
54h
FBh
33h
00h
54h
FBh
32h
00h
54h
FBh
32h
00h
54h
FBh
32h
00h
44h
5-98
Z8
Z16
P
S
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
LC88 Series Chapter 5
CLR1
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 0 0 0][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select), imm4 = 4bit(bit select)
1
1
(Rd) of bit #imm4 ← 0, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
0800H
[Description]
This instruction zero clears the bit designated by immediate data imm4 in the general-purpose register Rd.
The legitimate value range of Rd is from R0 to R15 and that of im4 from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
CLR1
CLR1
CLR1
R0,
R1,
R2,
R3,
R0,
R1,
R2,
R3,
#0xFFFF
#0x0001
#0x0000
#0x7654
#0x01
#0x00
#0x04
#0x0D
R0
R1
R2
R3
FFFFh
FFFFh
FFFFh
FFFFh
FFFDh
FFFDh
FFFDh
FFFDh
0001h
0001h
0001h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
7654h
7654h
7654h
7654h
5654h
5-99
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
Instructions
CLR1
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 0 1 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(bit select)
1
1
(Rd) of bit (Rs)&000Fh ← 0, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
0A00H
[Description]
This instruction zero clears the bit designated by the lower-order 4 bits of the general-purpose register Rs in
the general-purpose register Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rd from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
CLR1
CLR1
CLR1
R0,
R1,
R2,
R3,
R0,
R1,
R2,
R3,
#0xFFFF
#0x0001
#0x0000
#0x7654
R1
R2
R3
R0
R0
R1
R2
R3
FFFFh
FFFFh
FFFFh
FFFFh
FFFDh
FFFDh
FFFDh
FFFDh
0001h
0001h
0001h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
7654h
7654h
7654h
7654h
5654h
5-100
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
LC88 Series Chapter 5
DEC
Rd[, #imm2]
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][0 1 i1i0d3d2d1d0]
Rd = 4bit(R select), imm2 = 2bit(immediate data)
1
1
(Rd)←(Rd) - #imm2 – 1, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
3040H
[Description]
This instruction subtracts the value of immediate data imm2 + 1 from the contents of the general-purpose
register Rd and places the result in Rd.
The legitimate value range of Rd is from R0 to R15 and that of imm2 from 0 to 3.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
DEC
DEC
DEC
DEC
DEC
R0,
R1,
R2,
R3,
R0
R0,
R1,
R2,
R3,
#0x1234
#0x0000
#0x0003
#0x8765
#0
#1
#2
#3
R0
R1
R2
R3
1234h
1234h
1234h
1234h
1233h
1232h
1232h
1232h
1232h
0000h
0000h
0000h
0000h
0000h
FFFEh
FFFEh
FFFEh
0003h
0003h
0003h
0003h
0003h
0000h
0000h
8765h
8765h
8765h
8765h
8765h
8761h
N3 to
N0
0
1
2
3
0
0
1
2
3
<Note>
imm2 is assumed to be 0 if the immediate data (imm2) is omitted.
5-101
Z8
Z16
P
S
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
Instructions
DIV
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][1 1 0 0 0 0 0 0]
00C0H
1
18 cycles
(R0: quotient)…(R1: remainder)←(R0)÷(R2), (PC)←(PC)+2
Z8, Z16, P, S
CY, HC, OV, and N0 to N3 all cleared
[Description]
This instruction places the result of dividing the contents of the general-purpose register R0 by the contents
of R2 and places the quotient in R0 and the remainder in R1.
No valid result is guaranteed if the value of R2 is 0.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
DIV
R0,
R1,
R2,
R3,
89ABh
89ABh
89ABh
89ABh
0007h
#0x89AB
#0x5678
#0x1234
#0xDEF0
<Note>
The flags (Z8, Z16, P, and S) are affected by the contents of R0 (quotient).
5-102
R1
R2
R3
PSW
0040h
5678h
1000h
5678h 1234h
2020h
5678h 1234h DEF0h 3040h
0A3Fh 1234h DEF0h 0020h
LC88 Series Chapter 5
DIVLH
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][1 1 1 0 0 0 0 0]
00E0H
1
18 cycles
(R0: quotient)…(R1: remainder)←(R1<<16+R0)÷(R2), (PC)←(PC)+2
Z8, Z16, P, S
CY, HC, OV, and N0 to N3 all cleared
[Description]
This instruction places the result of dividing unsigned 32-bit data (R1<<16 + R0) by the contents of R2 in R0
and the remainder in R1.
No valid result is guaranteed if the value of R2 is 0 or R1≧R2.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
DIVLH
MOV.W
MOV.W
MOV.W
DIVLH
MOV.W
DIVLH
R0,
R1,
R2,
R3,
#0x89AB
#0x5678
#0x1234
#0xDEF0
R0, #0xFFFF
R1, #0x2FFF
R2, #0x0000
R0, #0x5555
R0
R1
R2
R3
PSW
89ABh
89ABh
89ABh
89ABh
4C01h
FFFFh
FFFFh
FFFFh
3333h
5555h
3332h
0567h
0567h
0567h
0777h
0777h
2FFFh
2FFFh
2FFFh
2FFFh
7555h
1234h
1234h
1234h
1234h
1234h
F000h
F000h
F000h
F000h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
0040h
1020h
2020h
3040h
0000h
0040h
1020h
2041h
0000h
0000h
0020h
<Note>
The flags (Z8, Z16, P, and S) are affected by the contents of R0 (quotient).
5-103
Instructions
HALT
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 1 0 0 0]
1
1
HALT mode, (PC)←(PC)+2
[Description]
The CPU enters the HALT mode after executing the HALT instruction.
5-104
0008H
LC88 Series Chapter 5
HOLD
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 1 0 1 0]
1
1
HOLD mode, (PC)←(PC)+2
[Description]
The CPU enters the HOLD mode after executing the HOLD instruction.
5-105
000AH
Instructions
HOLDX
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 1 0 1 1]
1
1
HOLDX mode, (PC)←(PC)+2
[Description]
The CPU enters the HOLDX mode after executing the HOLDX instruction.
5-106
000BH
LC88 Series Chapter 5
ICALL
Rb, Rs
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][0 1 1 b0 s3s2s1s0]
Rb = 1bit(absolute address), Rs = 4bit(absolute address)
1
4
(SP)←(SP)+6: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h), [SP+5, SP+4]←(PSW)
(PC)←(Rb<<16+Rs)
0060H
Affected flags
[Description]
This instruction stores the address of the instruction following this ICALL instruction (return address) and the
contents of the program status word (PSW) in the data memory locations (RAM) designated by the stack
pointer (SP) and increments the SP. Finally, the instruction places the absolute address (of which the
higher-order 16 bits are the contents of the general-purpose register designated by the base register (Rb) and
the lower-order 16 bits are the contents of Rs) in the program counter (PC).
The legitimate values of Rb is R8 and R9, and the legitimate value range of Rs is from R0 to R15.
[Example] The value of label LA is 910AH.
PC
MOV.W R15, #0x0000
9004h
MOV.W R3, #0x910A
9008h
MOV.W R8, #0x0000
900Ch
RAM RAM RAM RAM RAM RAM
(00h) (01h) (02h) (03h) (04h) (05h)
-
-
-
-
-
R3
-
-
-
-
-
-
PSW
SP
-
-
-
910Ah
-
R8
F003h 0000h
3060h 0000h
910Ah 0000h 8003h 0000h
loop:
ICALL
R8, R3;; CALL LA 910Ah 0Eh
90h
00h
00h
03h
80h 910Ah 0000h 8003h 0006h
INC
R3
NOP
900Ch
0Eh
90h
00h
00h
03h
80h
910Ch 0000h 3060h 0000h
900Eh
0Eh
90h
00h
00h
03h
80h
910Ch 0000h 3060h 0000h
910Ch
0Eh
90h
00h
00h
03h
80h
910Bh 0000h 3040h 0006h
900Ah 0Eh
90h
00h
00h
03h
80h
910Bh 0000h 8003h 0000h
.
.
.
LA:
INC
IRET
R3
5-107
Instructions
ICALLF a24
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 1 1][a7a6a5a4a3a2a1a0][a23 to a16][a15 to a8]
a24 = 24bit(absolute address)
2
4
(SP)←(SP)+6: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h), [SP+6, SP+5]←(PSW)
(PC)←(a24)
0300H
Affected flags
[Description]
This instruction stores the address of the instruction following this ICALL instruction (return address) and the
contents of the program status word (PSW) in the data memory locations (RAM) designated by the stack
pointer (SP) and increments the SP. Finally, the instruction places the absolute address (a24) in the program
counter (PC).
The legitimate value range of a24 is from 0 to FF＿FFFFｈ.
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM RAM RAM
R3
PSW
SP
(00h) (01h) (02h) (03h) (04h) (05h)
9004h
F003h 0000h
9008h
FFFFh 3040h 0000h
PC
MOV.W
MOV.W
loop:
ICALLF
INC
NOP
.
.
.
LA:
INC
IRET
R15, #0x0000
R3, #0xFFFF
LA;; CALL LA 910Ah 0Ch
R3
900Eh 0Ch
9010h 0Ch
90h
90h
90h
00h
00h
00h
00h
00h
00h
40h
40h
40h
30h
30h
30h
FFFFh 3040h 0006h
0001h 3020h 0000h
0001h 3020h 0000h
R3
90h
90h
00h
00h
00h
00h
40h
40h
30h
30h
0000h
0000h
910Ch 0Ch
900Ch 0Ch
5-108
3003h 0006h
3040h 0000h
LC88 Series Chapter 5
ICALLR
Rs
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][0 0 1 1 s3s2s1s0]
Rs = 4bit(relative address, signed)
1
4
(SP)←(SP)+6: [SP+1, SP]←(PC&0000FFFFh),
[SP+3, SP+2]←(PC&FFFF0000h), [SP+5, SP+4]←(PSW)
(PC)←(PC)+2±(Rs)
0030H
Affected flags
[Description]
This instruction stores the address of the instruction following this ICALL instruction (return address) and the
contents of the program status word (PSW) in the data memory locations (RAM) designated by the stack
pointer (SP) and increments the SP. Finally the instruction adds the value of the relative address (the contents
of the general-purpose register Rs) + 2 to the program counter (PC) and places the result in the PC.
The legitimate value range of Rs is from R0 to R15 and that of the relative address (the contents of the
general-purpose register Rs) is that of signed 16-biｔ data (-32768 to + 32767).
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM RAM RAM
R3
PSW
SP
(00h) (01h) (02h) (03h) (04h) (05h)
9004h
F003h 0000h
9008h
910Ah 3060h 0000h
PC
MOV.W
MOV.W
loop:
ICALLR
INC
NOP
.
.
.
LA:
INC
IRET
R15, #0x0000
R3, #0x910A
R3 ;; CALL LA 910Ah 0Ah
R3
900Ch 0Ah
900Eh 0Ah
90h
90h
90h
00h
00h
00h
00h
00h
00h
60h
60h
60h
30h 910Ah 3060h 0006h
30h 910Ch 3060h 0000h
30h 910Ch 3060h 0000h
R3
90h
90h
00h
00h
00h
00h
60h
60h
30h
30h
910Ch 0Ah
900Ah 0Ah
5-109
910Bh 3040h 0006h
910Bh 3060h 0000h
Instructions
INC Rd[, #imm2]
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][0 0 i1i0d3d2d1d0]
Rd = 4bit(R select), imm2 = 2bit(immediate data)
1
1
(Rd)←(Rd) + #imm2 + 1, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
3000H
[Description]
This instruction adds the value of immediate data imm2 + 1 to the contents of the general-purpose register Rd
and places the result in Rd.
The legitimate value range of Rd is from R0 to R15 and that of imm2 from 0 to 3.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
INC
INC
INC
INC
INC
R0,
R1,
R2,
R3,
R0
R0,
R1,
R2,
R3,
#0x1234
#0x0000
#0xFFFD
#0x8765
#0
#1
#2
#3
R0
R1
R2
R3
1234h
1234h
1234h
1234h
1235h
1236h
1236h
1236h
1236h
0000h
0000h
0000h
0000h
0000h
0002h
0002h
0002h
FFFDh
FFFDh
FFFDh
FFFDh
FFFDh
0000h
0000h
8765h
8765h
8765h
8765h
8765h
8769h
N3 to
N0
0
1
2
3
0
0
1
2
3
<Note>
imm2 is assumed to be 0 if the immediate data (imm2) is omitted.
5-110
Z8
Z16
P
S
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
LC88 Series Chapter 5
IRET
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][0 0 0 0 0 0 1 0]
0002H
1
3
(SP)←(SP)-6: (PC)←(PC-3<<24+SP-4<<16+SP-5<<8+SP-6)
(PSW)←(SP-1<<8, SP-2)
Affected flags
[Description]
This instruction decrements the value of the stack pointer (SP), places the contents of the data memory
locations (RAM) designated by SP in the program counter (PC) and program status word (PSW), then
resumes the execution of the interrupt acceptance function that has been disabled when the interrupt is
accepted.
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM RAM RAM
R3
(00h) (01h) (02h) (03h) (04h) (05h)
9004h
9008h
FFFFh
PC
MOV.W
MOV.W
loop:
ICALLF
INC
NOP
.
.
.
LA:
INC
IRET
R15, #0x0000
R3, #0xFFFF
PSW
SP
F003h 0000h
3040h 0000h
LA;; CALL LA 910Ah
R3
900Eh
9010h
0Ch
0Ch
0Ch
90h
90h
90h
00h
00h
00h
00h
00h
00h
40h
40h
40h
30h
30h
30h
FFFFh
0001h
0001h
3040h
3020h
3020h
0006h
0000h
0000h
R3
0Ch
0Ch
90h
90h
00h
00h
00h
00h
40h
40h
30h
30h
0000h
0000h
3003h
3040h
0006h
0000h
910Ch
900Ch
5-111
Instructions
JMP Rb, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 1 0 b0 s3s2s1s0]
Rb = 1bit(absolute address), Rs = 4bit(absolute address)
1
2
(PC)←(Rb<<16+Rs)
0040H
[Description]
This instruction places the absolute address (of which the higher-order 16 bits are the contents of the
general-purpose register designated by the base register (Rb) and the lower-order 16 bits are the contents of
Rs) in the program counter (PC).
The legitimate values of Rb is R8 and R9, and the legitimate value range of Rs is from R0 to R15.
[Example] The value of label LA is 9106H.
MOV.W R3, #0x9106
MOV.W R8, #0x0000
PC
R3
R8
PSW
9004h
9004h
9106h
9106h
0000h
3060h
8003h
9106h
-
9106h
-
0000h
-
8003h
-
9108h
910Ah
9107h
9107h
0000h
0000h
3060h
3060h
loop:
JMP
NOP
NOP
.
.
.
R8, R3
INC
NOP
R3
;; JUMP LA
LA:
5-112
LC88 Series Chapter 5
JMPF
a24
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 1 0][a7a6a5a4a3a2a1a0][a23 to a16][a15 to a8]
a24 = 24bit(absolute address)
2
3
(PC)←(a24)
0200H
[Description]
This instruction places the absolute address a24 in the program counter (PC).
The legitimate value range of a24 is from 0 to FF＿FFFFｈ.
[Example] The value of label LA is 9106H.
MOV.W
R3,
#0xFFFF
PC
R3
PSW
-
-
-
9004h
FFFFh
3040h
9106h
-
FFFFh
-
3040h
-
9108h
910Ah
0000h
0000h
3003h
3003h
loop:
JMPF
NOP
NOP
.
.
.
LA
INC
NOP
R3
;; JUMP LA
LA:
5-113
Instructions
MASK
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 1 1 0 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select), imm16 = 16bit(immediate data)
2
4
(Rd)←{(Rd) &~ #imm16} | { (Rx) & #imm16}, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
30E0H
[Description]
This instruction transfers (overwrites), to Rd, only such bits of the general-purpose register (Rx) designated
indirectly by bits 12 to 15 (N0 to N3) of the PSW that the value of the corresponding bits of immediate data
imm16 is 1.
The legitimate value range of Rd is from R0 to R15 and that of imm16 is from 0 to FFFF.
[Example]
MOV.W
MOV.W
MASK
MOV.W
MASK
SWPB
MASK
MOV.W
MASK
NOT
MASK
R3,
R0,
R3,
R1,
R3,
R1
R3,
R0,
R2,
R0
R2,
#0x0000
#0x5555
#0xFFFF
#0x1200
#0xFFFF
#0xFF00
#0x6789
#0x1234
#0xEDCB
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
6789h
6789h
9876h
9876h
1200h
1200h
0012h
0012h
0012h
0012h
0012h
0012h
0200h
0200h
8A42h
0000h
0000h
5555h
5555h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
5-114
N3 to
N0
3
0
3
1
3
1
3
0
2
0
2
Z8
Z16
P
S
1
0
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
LC88 Series Chapter 5
MASK
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 1 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
3
(Rd)←{(Rd) & ~(Rs)} | {(Rx) & (Rs)}, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
3300H
[Description]
This instruction transfers (overwrites), to Rd, only such bits of the general-purpose register (Rx) designated
indirectly by bits 12 to 15 (N0 to N3) of the PSW that the value of the corresponding bits of the
general-purpose register Rs is 1.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MASK
MOV.W
MASK
MOV.W
SWPB
MASK
MOV.W
MOV.W
MASK
NOT
NOT
MASK
R3,
R2,
R0,
R3,
R1,
R3,
R2,
R1
R3,
R2,
R0,
R3,
R2
R0
R3,
#0x0000
#0xFFFF
#0x5555
R2
#0x1200
R2
#0xFF00
R2
#0x1234
#0x6789
R2
R2
R0
R1
R2
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
6789h
6789h
6789h
9876h
9876h
1200h
1200h
1200h
0012h
0012h
0012h
0012h
0012h
0012h
0012h
0012h
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FF00h
FF00h
FF00h
1234h
1234h
1234h
EDCBh
EDCBh
EDCBh
5-115
N3 to
N0
0000h
3
0000h
2
0000h
0
5555h
3
5555h
1
1200h
3
1200h
2
1200h
1
0000h
3
0000h
2
0000h
0
0200h
3
0200h
2
0200h
0
8A42h
3
R3
Z8
Z16
P
S
1
0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
Instructions
MOV
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 1 1 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select), Rs = 4bit(R select)
1
1
(Rd)←(Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
4600H
[Description]
This instruction transfers the contents of the general-purpose register Rs to the general-purpose register Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R15.
[Example]
MOV.W
MOV
MOV.W
MOV
MOV.W
MOV
MOV.W
MOV
MOV.W
MOV
MOV.W
MOV
R0,
R3,
R1,
R3,
R2,
R3,
R0,
R3,
R1,
R3,
R2,
R3,
#0x5555
R0
#0x1200
R1
#0x0000
R2
#0x5634
R0
#0x8118
R1
#0x5555
R2
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
5555h
1200h
1200h
0000h
0000h
5634h
5634h
8118h
8118h
5555h
5-116
N3 to
N0
0
3
1
3
2
3
0
3
1
3
2
3
Z8
Z16
P
S
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
LC88 Series Chapter 5
MOV．B (Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
[Rd] ← Lobyte (Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7200H
[Description]
This instruction transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM)
location, special function register (SFR), or program memory (ROM) location designated by the contents of
Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
RAM RAM
(50h) (51h)
0x50,#0x6666 66h
66h
R3, #0x0050
66h
66h
R0, #0x5555
66h
66h
(R3), R0
55h
66h
R1, #0x1200
55h
66h
(R3), R1
00h
66h
R2, #0x0000
00h
66h
(R3), R2
00h
66h
R0, #0x5634
00h
66h
(R3), R0
34h
66h
R1, #0x1881
34h
66h
(R3), R1
34h
66h
R2, #0x5555
34h
66h
(R3), R2
81h
66h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
0055h
0055h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
N3 to
N0
3
0
0
1
1
2
2
0
0
1
1
2
2
Z8 Z16
0
0
0
0
1
1
1
1
0
0
0
0
0
0
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-117
0
0
0
0
0
1
1
1
0
0
0
0
0
0
P
S
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Instructions
MOV．B (--Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
(Rd)←(Rd)-1, [Rd] ← Lobyte (Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6A00H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register Rd. Subsequently, it
transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM) location,
special function register (SFR), or program memory (ROM) location designated by the contents of Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
0x50,
#0x6666
R3, #0x0051
R0, #0x5555
(--R3), R0
R3
R1, #0x1200
(--R3), R1
R3
R2, #0x0000
(--R3), R2
R3
R0, #0x5634
(--R3), R0
R3
R1, #0x1881
(--R3), R1
R3
R2, #0x5555
(--R3), R2
R3
RAM
(50h)
-
RAM
(51h)
-
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
81h
81h
81h
55h
55h
N3 to
Z8 Z16 P
N0
-
R0
R1
R2
R3
-
-
-
-
66h
-
-
-
-
-
0
0
0
0
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
3
0
0
3
1
1
3
2
2
3
0
0
3
1
1
3
2
2
3
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-118
S
-
LC88 Series Chapter 5
MOV．B (Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 1 0][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
[(Rd±n)&FFFFh]←Lobyte (Rs), (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
7208H
[Description]
This instruction transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM)
location, special function register (SFR), or program memory (ROM) location designated by the address
derived by the arithmetic operation＊1 performed on the contents of Rd and n.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R7, and that of n is that of
signed 12-bit data (-2048 to 2047).
＊1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
0x50,#0x6666
R3, #0x0000
R0, #0x5555
(R3,0x50), R0
R1, #0x1200
(R3,0x50), R1
R2, #0x0000
(R3,0x50), R2
R0, #0x5634
(R3,0x50), R0
R1, #0x1881
(R3,0x50), R1
R2, #0x5555
(R3,0x50), R2
RAM
(50h)
66h
66h
66h
55h
55h
00h
00h
00h
00h
34h
34h
81h
81h
55h
RAM
(51h)
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P
N0
0
0
0
3
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
2
1
1
0
2
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
2
0
0
0
2
0
0
0
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-119
S
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Instructions
MOV．B (--Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 1 0][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
(Rd)←(Rd)-1, [(Rd±n)&FFFFh] ← Lobyte(Rs), (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
6A08H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register Rd. Subsequently, it
transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM) location,
special function register (SFR), or program memory (ROM) location designated by the address derived by the
arithmetic operation＊1 performed on the contents of Rd and n.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R7, and that of n is that of 12-bit
data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
0x50, #0x6666
R3, #0x0001
R0, #0x5555
(--R3,0x50), R0
R3
R1, #0x1200
(--R3,0x50), R1
R3
R2, #0x0000
(--R3,0x50), R2
R3
R0, #0x5634
(--R3,0x50), R0
R3
R1, #0x1881
(--R3,0x50), R1
R3
R2, #0x5555
(--R3,
0x50),
MOV.B
R2
INC
R3
RAM
(50h)
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
81h
81h
81h
RAM
(51h)
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
N3 to
N0
3
0
0
3
1
1
3
2
2
3
0
0
3
1
1
3
2
55h
66h
5634h
1881h
5555h
0000h
55h
66h
5634h
1881h
5555h
0001h
Z8 Z16 P
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
2
0
0
0
0
3
0
0
1
0
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-120
S
LC88 Series Chapter 5
MOV．B (Rd+ +), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
[Rd] ← Lobyte(Rs), (Rd)←(Rd)+1, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6200H
[Description]
This instruction transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM)
location, special function register (SFR), or program memory (ROM) location designated by the
general-purpose register Rd. Subsequently, the instruction increments the contents of Rd by +1.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
RAM
(50h)
0x50,#0x6666 66h
R3, #0x0050
66h
R0, #0x5555
66h
(R3++), R0
55h
R3
55h
R1, #0x1200
55h
(R3++), R1
00h
R3
00h
R2, #0x0000
00h
(R3++), R2
00h
R3
00h
R0, #0x5634
00h
(R3++), R0
34h
R3
34h
R1, #0x1881
34h
(R3++), R1
81h
R3
81h
R2, #0x5555
81h
(R3++), R2
55h
R3
55h
RAM
(51h)
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
N3 to
Z8 Z16
N0
- 0 0
3
0 0
0
0 0
0
0 0
3
0 0
1
1 0
1
1 1
3
0 0
2
1 1
2
1 1
3
0 0
0
0 0
0
0 0
3
0 0
1
0 0
1
0 0
3
0 0
2
0 0
2
0 0
2
0 0
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-121
P
S
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Instructions
MOV．B (Rd + +, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 1 0][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
[(Rd±n)&FFFFh] ← Lobyte(Rs), (Rd)←(Rd)+1, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
6208H
[Description]
This instruction transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM)
location, special function register (SFR), or program memory (ROM) location designated by the address
derived by the arithmetic operation＊1 performed on the contents of Rd and n. Subsequently, the instruction
increments the contents of Rd by +1.
The legitimate value range of Rd is from R0 to R15, that of Rs is from R0 to R7, and that of n is that of
signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored..
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R3++, 0x50), R0
R3
R1, #0x1200
(R3++, 0x50), R1
R3
R2, #0x0000
(R3++, 0x50), R2
R3
R0, #0x5634
(R3++, 0x50), R0
R3
R1, #0x1881
(R3++, 0x50), R1
R3
R2, #0x5555
(R3++, 0x50), R2
R3
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 66h
66h
0 0
66h
66h
0000h
3
1 1
66h
66h 5555h
0000h
0
0 0
55h
66h 5555h
0001h
0
0 0
55h
66h 5555h
0000h
3
1 1
55h
66h 5555h 1200h
0000h
1
1 0
00h
66h 5555h 1200h
0001h
1
1 1
00h
66h 5555h 1200h
0000h
3
1 1
00h
66h 5555h 1200h 0000h 0000h
2
1 1
00h
66h 5555h 1200h 0000h 0001h
2
1 1
00h
66h 5555h 1200h 0000h 0000h
3
1 1
00h
66h 5634h 1200h 0000h 0000h
0
0 0
34h
66h 5634h 1200h 0000h 0001h
0
0 0
34h
66h 5634h 1200h 0000h 0000h
3
1 1
34h
66h 5634h 1881h 0000h 0000h
1
0 0
81h
66h 5634h 1881h 0000h 0001h
1
0 0
81h
66h 5634h 1881h 0000h 0000h
3
1 1
81h
66h 5634h 1881h 5555h 0000h
2
0 0
55h
66h 5634h 1881h 5555h 0001h
2
0 0
55h
66h 5634h 1881h 5555h 0000h
3
1 1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to the program memory (ROM).
However, no data can actually be transferred to ROM.
5-122
P
S
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOV．B m16, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 1 0 X 0][m7m6m5m4m3m2m1m0][i15 to i8][i7 to i0]
7800H(RAM), 7A00H(SFR)
m16 = 16bit (lower 8bit valid for operation code)
imm16 = 16bit (immediate data)
2
2
(m16)←Lobyte #imm16, (PC)←(PC)+4
Z8, Z16, P, S
[Description]
This instruction transfers the lower-order 8 bits of immediate data imm16 to the data memory (RAM)
location or SFR (one of the registers dedicated to control the internal peripheral devices) addressed by m16.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH.
The basic types of generated instruction code are 7800H (RAM) and 7A00H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
imm16 (second operand data) may be 16-bit data. Since this instruction is a byte transfer instruction, however,
the higher-order 8 bits of imm16 is irrelevant to the actual behavior of the instruction. The MOV. W
instruction should be used to handle 16-bit data.
[Example]
MOV.B
MOV.B
MOV.B
MOV.B
MOV.B
0x50,
0x50,
0x50,
0x50,
0x50,
RAM
(50h)
55h
00h
34h
81h
55h
#0x55
#0x00
#0x34
#0x81
#0x55
5-123
Z8
Z16
P
S
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
Instructions
MOV．B m16, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 0 X 1 s2s1s0 0][m7m6m5m4m3m2m1m0]
9000H(RAM), B000H(SFR)
m16 = 16bit(Lower 8bit valid for operation code), Rs = 3bit(R select)
1
1
(m16) ← Lobyte(Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the lower-order 8 bits of the general-purpose register Rs to the data memory (RAM)
location or SFR (one of the registers dedicated to control the internal peripheral devices) addressed by m16.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH.
The basic types of generated instruction code are 9000H (RAM) and B000H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
Rs (second operand data) may be 16-bit data. Since this instruction is a byte transfer instruction, however, the
higher-order 8 bits of Rs is irrelevant to the actual behavior of the instruction. The MOV. W instruction
should be used to handle 16-bit data.
[Example]
MOV.W
MOV.W
MOV.B
MOV.W
MOV.W
MOV.B
MOV.W
MOV.W
MOV.B
MOV.W
MOV.W
MOV.B
MOV.W
MOV.W
MOV.B
MOV.W
MOV.W
MOV.B
R0, #0x5555
R3, #0x5555
0x50, R0
R1, #0x1200
R3, #0x6666
0x50, R1
R2, #0x0000
R3, #0x3333
0x50, R2
R0, #0x5634
R3, #0x6655
0x50, R0
R1, #0x1881
R3, #0x3366
0x50, R1
R2, #0x5555
R3, #0x6355
0x50, R2
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 5555h
0
0 0
5555h
5555h
3
0 0
55h
5555h
5555h
0
0 0
55h
5555h 1200h
5555h
1
1 0
55h
5555h 1200h
6666h
3
0 0
00h
5555h 1200h
6666h
1
1 1
00h
5555h 1200h 0000h 6666h
2
1 1
00h
5555h 1200h 0000h 3333h
3
0 0
00h
5555h 1200h 0000h 3333h
2
1 1
00h
5634h 1200h 0000h 3333h
0
0 0
00h
5634h 1200h 0000h 6655h
3
0 0
34h
5634h 1200h 0000h 6655h
0
0 0
34h
5634h 1881h 0000h 6655h
1
0 0
34h
5634h 1881h 0000h 3366h
3
0 0
81h
5634h 1881h 0000h 3366h
1
0 0
81h
5634h 1881h 5555h 3366h
2
0 0
81h
5634h 1881h 5555h 6355h
3
0 0
55h
5634h 1881h 5555h 6355h
2
0 0
5-124
P
S
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
LC88 Series Chapter 5
MOV．B Rd, (Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rd) ← Lobyte [Rs], (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7000H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by Rs to the lower-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
R3, #0x0050
0x50, #0x5555
R0, (R3)
0x50, #0x1200
R1, (R3)
0x50, #0x0000
R2, (R3)
0x50, #0x5634
R0, (R3)
0x50, #0x1881
R1, (R3)
0x50, #0x5555
R2, (R3)
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0050h
3
0 0
55h
55h
0050h
3
0 0
55h
55h 0055h
0050h
0
0 0
00h
12h 0055h
0050h
0
1 0
00h
12h 0055h 0000h
0050h
1
1 1
00h
00h 0055h 0000h
0050h
1
1 1
00h
00h 0055h 0000h 0000h 0050h
2
1 1
34h
56h 0055h 0000h 0000h 0050h
2
0 0
34h
56h 0034h 0000h 0000h 0050h
0
0 0
81h
18h 0034h 0000h 0000h 0050h
0
0 0
81h
18h 0034h 0081h 0000h 0050h
1
0 0
55h
55h 0034h 0081h 0000h 0050h
1
0 0
55h
55h 0034h 0081h 0055h 0050h
2
0 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-125
P
S
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Instructions
MOV．B Rd, (--Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rs) ← (Rs) – 1, (Rd) ← Lobyte[Rs], (PC) ← (PC) + 2
Z8, Z16, P, S, N0 to N3
6800H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register Rs. Subsequently, the
instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by Rs to the lower-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R15 and that of Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
R3, #0x0051
0x50, #0x5555
R0, (--R3)
R3
0x50, #0x1200
R1, (--R3)
R3
0x50, #0x0000
R2, (--R3)
R3
0x50, #0x5634
R0, (--R3)
R3
0x50, #0x1881
R1, (--R3)
R3
0x50, #0x5555
R2, (--R3)
R3
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0051h
3
0 0
55h
55h
0051h
3
0 0
55h
55h 0055h
0050h
0
0 0
55h
55h 0055h
0051h
3
0 0
00h
12h 0055h
0051h
3
1 0
00h
12h 0055h 0000h
0050h
1
1 1
00h
12h 0055h 0000h
0051h
3
0 0
00h
00h 0055h 0000h
0051h
3
1 1
00h
00h 0055h 0000h 0000h 0050h
2
1 1
00h
00h 0055h 0000h 0000h 0051h
3
0 0
34h
56h 0055h 0000h 0000h 0051h
3
0 0
34h
56h 0034h 0000h 0000h 0050h
0
0 0
34h
56h 0034h 0000h 0000h 0051h
3
0 0
81h
18h 0034h 0000h 0000h 0051h
3
0 0
81h
18h 0034h 0081h 0000h 0050h
1
0 0
81h
18h 0034h 0081h 0000h 0051h
3
0 0
55h
55h 0034h 0081h 0000h 0051h
3
0 0
55h
55h 0034h 0081h 0055h 0050h
2
0 0
55h
55h 0034h 0081h 0055h 0051h
3
0 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-126
P
S
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOV．B Rd, (Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 0 0][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rd) ← Lobyte [(Rs±n)&FFFFh], (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
7008H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the address derived by the arithmetic operation＊1
performed on the contents of Rs and n to the lower-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R7, that of Rs is from 0 to R15, and that of n is that of signed
12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored..
[Example]
MOV.W
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
MOV.W
MOV.B
R3, #0x0000
0x50, #0x5555
R0, (R3, 0x50)
0x50, #0x1200
R1, (R3, 0x50)
0x50, #0x0000
R2, (R3, 0x50)
0x50, #0x5634
R0, (R3, 0x50)
0x50, #0x1881
R1, (R3, 0x50)
0x50, #0x5555
R2, (R3, 0x50)
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0000h
3
1 1
55h
55h
0000h
3
0 0
55h
55h 0055h
0000h
0
0 0
00h
12h 0055h
0000h
0
1 0
00h
12h 0055h 0000h
0000h
1
1 1
00h
00h 0055h 0000h
0000h
1
1 1
00h
00h 0055h 0000h 0000h 0000h
2
1 1
34h
56h 0055h 0000h 0000h 0000h
2
0 0
34h
56h 0034h 0000h 0000h 0000h
0
0 0
18h
81h 0034h 0000h 0000h 0000h
0
0 0
18h
81h 0034h 0081h 0000h 0000h
1
0 0
55h
55h 0034h 0081h 0000h 0000h
1
0 0
55h
55h 0034h 0081h 0055h 0000h
2
0 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-127
P
S
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Instructions
MOV．B Rd, (--Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 0 0][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rs)←(Rs)-1, (Rd)←Lobyte [(Rs±n)&FFFFh], (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
6808H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register Rs.
Subsequently, the instruction transfers the contents of the data memory (RAM) location, special function
register (SFR), or program memory (ROM) location designated by the address derived by the arithmetic
operation＊1 performed on the contents of Rs and n to the lower-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R7, that of Rs is from R0 to R15, and that of n is that of
signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored..
[Example]
MOV.W
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
MOV.W
MOV.B
INC
R3, #0x0001
0x50, #0x5555
R0,(--R3, 0x50)
R3
0x50, #0x1200
R1,(--R3, 0x50)
R3
0x50, #0x0000
R2,(--R3, 0x50)
R3
0x50, #0x5634
R0,(--R3, 0x50)
R3
0x50, #0x1881
R1,(--R3, 0x50)
R3
0x50, #0x5555
R2,(--R3, 0x50)
R3
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0001h
3
0 0
55h
55h
0001h
3
0 0
55h
55h 0055h
0000h
0
0 0
55h
55h 0055h
0001h
3
0 0
00h
12h 0055h
0001h
3
1 0
00h
12h 0055h 0000h
0000h
1
1 1
00h
12h 0055h 0000h
0001h
3
0 0
00h
00h 0055h 0000h
0001h
3
1 1
00h
00h 0055h 0000h 0000h 0000h
2
1 1
00h
00h 0055h 0000h 0000h 0001h
3
0 0
34h
56h 0055h 0000h 0000h 0001h
3
0 0
34h
56h 0034h 0000h 0000h 0000h
0
0 0
34h
56h 0034h 0000h 0000h 0001h
3
0 0
18h
81h 0034h 0000h 0000h 0001h
3
0 0
18h
81h 0034h 0081h 0000h 0000h
1
0 0
18h
81h 0034h 0081h 0000h 0001h
3
0 0
55h
55h 0034h 0081h 0000h 0001h
3
0 0
55h
55h 0034h 0081h 0055h 0000h
2
0 0
55h
55h 0034h 0081h 0055h 0001h
3
0 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-128
P
S
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOV．B Rd, (Rs + + )
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rd) ← Lobyte [Rs], (Rs) ← (Rs) + 1, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6000H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by Rs to the lower-order 8 bit positions of Rd. Subsequently,
the instruction increments the contents of Rs by 1.
The legitimate value range of Rd is from R0 to R7 and that of Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
R3, #0x0050
0x50, #0x5555
R0, (R3++)
R3
0x50, #0x1200
R1, (R3++)
R3
0x50, #0x0000
R2, (R3++)
R3
0x50, #0x5634
R0, (R3++)
R3
0x50, #0x1881
R1, (R3++)
R3
0x50, #0x5555
R2, (R3++)
R3
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0050h
3
0 0
55h
55h
0050h
3
0 0
55h
55h 0055h
0051h
0
0 0
55h
55h 0055h
0050h
3
0 0
00h
12h 0055h
0050h
3
1 0
00h
12h 0055h 0000h
0051h
1
1 1
00h
12h 0055h 0000h
0050h
3
0 0
00h
00h 0055h 0000h
0050h
3
1 1
00h
00h 0055h 0000h 0000h 0051h
2
1 1
00h
00h 0055h 0000h 0000h 0050h
3
0 0
34h
56h 0055h 0000h 0000h 0050h
3
0 0
34h
56h 0034h 0000h 0000h 0051h
0
0 0
34h
56h 0034h 0000h 0000h 0050h
3
0 0
81h
18h 0034h 0000h 0000h 0050h
3
0 0
81h
18h 0034h 0081h 0000h 0051h
1
0 0
81h
18h 0034h 0081h 0000h 0050h
3
0 0
55h
55h 0034h 0081h 0000h 0050h
3
0 0
55h
55h 0034h 0081h 0055h 0051h
2
0 0
55h
55h 0034h 0081h 0055h 0050h
3
0 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-129
P
S
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Instructions
MOV．B Rd, (Rs + +, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 0 0][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rd) ← Lobyte[(Rs±n)&FFFFh], (Rs) ← (Rs) + 1, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
6008H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the address derived by the arithmetic operation＊1
performed on the contents of Rs and n to the lower-order 8 bit positions of Rd. Subsequently, the instruction
increments the contents of Rs by 1.
The legitimate value range of Rd is from R0 to R7, that of Rs is from 0 to R15, and that of n is that of signed
12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored..
[Example]
MOV.W
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
MOV.W
MOV.B
DEC
R3, #0x0000
0x50, #0x5555
R0, (R3++, 0x50)
R3
0x50, #0x1200
R1, (R3++, 0x50)
R3
0x50, #0x0000
R2, (R3++, 0x50)
R3
0x50, #0x5634
R0, (R3++, 0x50)
R3
0x50, #0x1881
R1, (R3++, 0x50)
R3
0x50, #0x5555
R2, (R3++, 0x50)
R3
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 0000h
3
1 1
55h
55h
0000h
3
0 0
55h
55h 0055h
0001h
0
0 0
55h
55h 0055h
0000h
3
1 1
00h
12h 0055h
0000h
3
1 0
00h
12h 0055h 0000h
0001h
1
1 1
00h
12h 0055h 0000h
0000h
3
1 1
00h
00h 0055h 0000h
0000h
3
1 1
00h
00h 0055h 0000h 0000h 0001h
2
1 1
00h
00h 0055h 0000h 0000h 0000h
3
1 1
34h
56h 0055h 0000h 0000h 0000h
3
0 0
34h
56h 0034h 0000h 0000h 0001h
0
0 0
34h
56h 0034h 0000h 0000h 0000h
3
1 1
81h
18h 0034h 0000h 0000h 0000h
3
0 0
81h
18h 0034h 0081h 0000h 0001h
1
0 0
81h
18h 0034h 0081h 0000h 0000h
3
1 1
55h
55h 0034h 0081h 0000h 0000h
3
0 0
55h
55h 0034h 0081h 0055h 0001h
2
0 0
55h
55h 0034h 0081h 0055h 0000h
3
1 1
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-130
P
S
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOV．B Rd, m16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 0 X 0 d2d1d0 0][m7m6m5m4m3m2m1m0]
8000H(RAM), A000H(SFR)
Rd = 3bit(R select), m16 = 16bit(Lower 8bit valid for operation code)
1
1
(Rd) ← Lobyte (m16), (PC) ← (PC) + 2
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of data memory location designated by m16 to the lower-order 8 bit
positions of the general-purpose register Rd.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (second operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to ７FFFH.
The basic types of generated instruction code are 8000H (RAM) and A000H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
Rd (first operand data) may be 16-bit data. Since this instruction is a byte transfer instruction, however, the
higher-order 8 bits of Rd is irrelevant to the actual behavior of the instruction. The MOV. W instruction
should be used to handle 16-bit data.
The legitimate value range of Rd is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.B
MOV.B
MOV.W
MOV.B
MOV.B
MOV.W
MOV.B
MOV.B
MOV.W
MOV.B
MOV.B
MOV.W
MOV.B
0x50, #0x3C55
r3, #0x5555
r0, 0x50
0x50, #0x00
r3, #0x6666
r1, 0x50
0x50, #0x34
R3, #0x3333
R2, 0x50
0x50, #0x81
R3, #0x5555
R0, 0x50
0x50, #0x55
R3, #0x6355
R1, 0x50
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- 55h
3Ch
0 0
55h
3Ch
5555h
3
0 0
55h
3Ch 0055h
5555h
0
0 0
00h
3Ch 0055h
5555h
0
1 1
00h
3Ch 0055h
6666h
3
0 0
00h
3Ch 0055h 0000h
6666h
1
1 1
34h
3Ch 0055h 0000h
6666h
1
0 0
34h
3Ch 0055h 0000h
3333h
3
0 0
34h
3Ch 0055h 0000h 0034h 3333h
2
0 0
81h
3Ch 0055h 0000h 0034h 3333h
2
0 0
81h
3Ch 0055h 0000h 0034h 5555h
3
0 0
81h
3Ch 0081h 0000h 0034h 5555h
0
0 0
55h
3Ch 0081h 0000h 0034h 5555h
0
0 0
55h
3Ch 0081h 0000h 0034h 6355h
3
0 0
55h
3Ch 0081h 0055h 0034h 6355h
1
0 0
5-131
P
S
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
Instructions
MOV．B Rd, RxH
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 1 0 1 d3d2d1d0]
Rd = 4bit(R select)
1
1
(Rd) ← { Hibyte(Rx) | Lobyte(Rd) }, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
30D0H
[Description]
This instruction transfers the higher-order 8 bits (RxH) of the general-purpose register designated indirectly
by bits 12 to 15 (N0 to N3) of the PSW to the higher-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
SWPB
MOV.W
MOV.B
MOV.W
MOV.B
SWPB
MOV.W
MOV.B
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- R3, #0xFFFF
FFFFh
3
0 0
R0, #0x0000
0000h
FFFFh
0
1 1
0x50, #0x6666 66h
66h 0000h
FFFFh
0
0 0
R3, Rxh
66h
66h 0000h
00FFH
3
0 0
R3
66h
66h 0000h
FF00h
3
1 0
R1, #0x0012
66h
66h 0000h 0012h
FF00h
1
0 0
R3, Rxh
66h
66h 0000h 0012h
0000h
3
1 1
R2, #0x8967
66h
66h 0000h 0012h 8967h 0000h
2
0 0
R3, Rxh
66h
66h 0000h 0012h 8967h 8900h
3
0 0
R3
66h
66h 0000h 0012h 8967h 0089h
3
0 0
R0, #0x5634
66h
66h 5634h 0012h 8967h 0089h
0
0 0
R3, Rxh
66h
66h 5634h 0012h 8967h 5689h
3
0 0
5-132
P
S
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
LC88 Series Chapter 5
MOV．B Rd, RxL
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 1 0 0 d3d2d1d0]
Rd = 4bit(R select)
1
1
(Rd) ← { Lobyte(Rx) | Hibyte(Rd) }, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
30C0H
[Description]
This instruction transfers the lower-order 8 bits (RxL) of the general-purpose register designated indirectly by
bits 12 to 15 (N0 to N3) of the PSW to the lower-order 8 bit positions of Rd.
The legitimate value range of Rd is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.B
SWPB
MOV.W
MOV.B
MOV.W
MOV.B
SWPB
MOV.W
MOV.B
RAM RAM
N3 to
R0
R1
R2
R3
Z8 Z16
(50h) (51h)
N0
- R3, #0xFFFF
FFFFh
3
0 0
R0, #0x0000
0000h
FFFFh
0
1 1
0x50, #0x6666 66h
66h 0000h
FFFFh
0
0 0
R3, Rxl
66h
66h 0000h
FF00H
3
1 0
R3
66h
66h 0000h
00FFh
3
0 0
R1, #0x1200
66h
66h 0000h 1200h
00FFh
1
1 0
R3, Rxl
66h
66h 0000h 1200h
0000h
3
1 1
R2, #0x6789
66h
66h 0000h 1200h 6789h 0000h
2
0 0
R3, Rxl
66h
66h 0000h 1200h 6789h 0089h
3
0 0
R3
66h
66h 0000h 1200h 6789h 8900h
3
1 0
R0, #0x3456
66h
66h 3456h 1200h 6789h 8900h
0
0 0
R3, Rxl
66h
66h 3456h 1200h 6789h 8956h
3
0 0
5-133
P
S
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
Instructions
MOV[.W] (Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
if (Rd) = even data : [Rd] ← Lobyte (Rs), [Rd+1] ← Hibyte (Rs)
if (Rd) = odd data : [Rd] ← Hibyte (Rs), [Rd-1] ← Lobyte(Rs)
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7300H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
addressed by the contents of Rd is at an even address, the instruction transfers the contents of the lower-order
8 bits of the general-purpose register Rs to [Rd] and the contents of the higher-order 8 bits of Rs to [Rd + 1].
In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits of Rs to [Rd] and
the contents of the lower-order 8 bits of Rs to [Rd – 1].
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3), R0
R1, #0x1200
(R3), R1
R2, #0x0000
(R3), R2
R0, #0x5634
(R3), R0
R1, #0x8118
(R3), R1
R2, #0x5555
(R3), R2
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0050h
3
66h
66h 5555h
0050h
0
55h
55h 5555h
0050h
0
55h
55h 5555h 1200h
0050h
1
00h
12h 5555h 1200h
0050h
1
00h
12h 5555h 1200h 0000h 0050h
2
00h
00h 5555h 1200h 0000h 0050h
2
00h
00h 5634h 1200h 0000h 0050h
0
34h
56h 5634h 1200h 0000h 0050h
0
34h
56h 5634h 8118h 0000h 0050h
1
34h
56h 5555h 1200h 0000h 0050h
1
34h
56h 5634h 1200h 0000h 0050h
2
34h
56h 5634h 1200h 0000h 0050h
2
Z8 Z16 P S
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-134
LC88 Series Chapter 5
MOV[.W] (--Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
(Rd)←(Rd)-2
if (Rd) =even data : [Rd]←Lobyte(Rs), [Rd+1]←Hibyte(Rs)
if (Rd) =odd data : [Rd]←Hibyte(Rs), [Rd-1]←Lobyte(Rs)
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6B00H
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rd.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location addressed by the contents of Rd is at an even address, the instruction transfers the contents of
the lower-order 8 bits of the general-purpose register Rs to [Rd] and the contents of the higher-order 8 bits of
Rs to [Rd + 1]. In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits
of Rs to [Rd] and the contents of the lower-order 8 bits of Rs to [Rd – 1].
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0052
R0, #0x5555
(--R3), R0
R3, #1
R1, #0x1200
(--R3), R1
R3, #1
R2, #0x0000
(--R3), R2
R3, #1
R0, #0x5634
(--R3), R0
R3, #1
R1, #0x8118
(--R3), R1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0052h
3
66h
66h 5555h
0052h
0
55h
55h 5555h
0050h
0
55h
55h 5555h
0052h
3
55h
55h 5555h 1200h
0052h
1
00h
12h 5555h 1200h
0050h
1
00h
12h 5555h 1200h
0052h
3
00h
12h 5555h 1200h 0000h 0052h
2
00h
00h 5555h 1200h 0000h 0050h
2
00h
00h 5555h 1200h 0000h 0052h
3
00h
00h 5634h 1200h 0000h 0052h
0
34h
56h 5634h 1200h 0000h 0050h
0
34h
56h 5634h 1200h 0000h 0052h
3
34h
56h 5634h 8118h 0000h 0052h
1
18h
81h 5634h 8118h 0000h 0050h
1
Z8 Z16 P
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-135
Instructions
MOV[.W]
(Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 1 1][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
7308H
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
if (Rd±n) = even data :
[(Rd±n)&FFFFh]←Lobyte(Rs), [(Rd±n+1)&FFFFh]←Hibyte(Rs)
if (Rd±n) = odd data :
[(Rd±n)&FFFFh]←Hibyte(Rs), [(Rd±n-1)&FFFFh]←Lobyte(Rs)
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the address derived by the arithmetic operation*1 performed on the contents of the
general-purpose register designated by Rd and n is at an even address, the instruction transfers the contents of
the lower-order 8 bits of the general-purpose register Rs to [(Rd±n)&FFFFh] and the higher-order 8 bits of
Rs to [(Rd±n+1)&FFFFh]. In the case of an odd address, the instruction transfers the contents of the
higher-order 8 bits of Rs to [(Rd±n)&FFFFh] and the lower-order 8 bits of Rs to [(Rd±n-1)&FFFFh].
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R7, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R3, 0x50), R0
R1, #0x1200
(R3, 0x50), R1
R2, #0x0000
(R3, 0x50), R2
R0, #0x5634
(R3, 0x50), R0
R1, #0x8118
(R3, 0x50), R1
R2, #0x5555
(R3, 0x50), R2
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0000h
3
66h
66h 5555h
0000h
0
55h
55h 5555h
0000h
0
55h
55h 5555h 1200h
0000h
1
00h
12h 5555h 1200h
0000h
1
00h
12h 5555h 1200h 0000h 0000h
2
00h
00h 5555h 1200h 0000h 0000h
2
00h
00h 5634h 1200h 0000h 0000h
0
34h
56h 5634h 1200h 0000h 0000h
0
34h
56h 5634h 8118h 0000h 0000h
1
18h
81h 5634h 8118h 0000h 0000h
1
18h
81h 5634h 8118h 5555h 0000h
2
55h
55h 5634h 8118h 5555h 0000h
2
Z8 Z16 P S
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-136
LC88 Series Chapter 5
MOV[.W] (--Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 1 1][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
6B08H
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
(Rd)←(Rd)-2
if (Rd±n) = even data :
[(Rd±n)&FFFFh]←Lobyte(Rs), [(Rd±n+1)&FFFFh]←Hibyte(Rs)
if (Rd±n) = odd data :
[(Rd±n)&FFFFh]←Hibyte(Rs), [(Rd±n-1)&FFFFh]←Lobyte(Rs)
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rd.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by the address derived by the arithmetic operation*1 performed on the contents of
Rd and n is at an even address, the instruction transfers the contents of the lower-order 8 bits of the
general-purpose register Rs to [(Rd±n)&FFFFh] and the higher-order 8 bits of Rs to [(Rd±n+1)&FFFFh].
In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits of Rs to [(Rd±
n)&FFFFh] and the lower-order 8 bits of Rs to [(Rd±n-1)&FFFFh].
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R7, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0002
R0, #0x5555
(--R3, 0x50), R0
R3, #1
R1, #0x1200
(--R3, 0x50), R1
R3, #1
R2, #0x0000
(--R3, 0x50), R2
R3, #1
R0, #0x5634
(--R3, 0x50), R0
R3, #1
R1, #0x8118
(--R3, 0x50), R1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0002h
3
66h
66h 5555h
0002h
0
55h
55h 5555h
0000h
0
55h
55h 5555h
0002h
3
55h
55h 5555h 1200h
0002h
1
00h
12h 5555h 1200h
0000h
1
00h
12h 5555h 1200h
0002h
3
00h
12h 5555h 1200h 0000h 0002h
2
00h
00h 5555h 1200h 0000h 0000h
2
00h
00h 5555h 1200h 0000h 0002h
3
00h
00h 5634h 1200h 0000h 0002h
0
34h
56h 5634h 1200h 0000h 0000h
0
34h
56h 5634h 1200h 0000h 0002h
3
34h
56h 5634h 8118h 0000h 0002h
1
18h
81h 5634h 8118h 0000h 0000h
1
Z8 Z16 P
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-137
Instructions
MOV[.W] (Rd++), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
if (Rd) = even data : [Rd]←Lobyte(Rs), [Rd+1]←Hibyte (Rs)
if (Rd) = odd data : [Rd]←Hibyte(Rs), [Rd-1]←Lobyte(Rs)
(Rd)← (Rd)+2, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6300H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
addressed by the contents of the general-purpose register designated by Rd is at an even address, the
instruction transfers the contents of the lower-order 8 bits of the general-purpose register Rs to [Rd] and the
contents of the higher-order 8 bits of Rs to [Rd + 1]. In the case of an odd address, the instruction transfers
the contents of the higher-order 8 bits of Rs to [Rd] and the contents of the lower-order 8 bits of Rs to [Rd –
1]. Subsequently, the instruction increments the contents of Rd by 2.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3++), R0
R3, #1
R1, #0x1200
(R3++), R1
R3, #1
R2, #0x0000
(R3++), R2
R3, #1
R0, #0x5634
(R3++), R0
R3, #1
R1, #0x8118
(R3++), R1
R3, #1
R2, #0x5555
(R3++), R2
R3, #1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0050h
3
66h
66h 5555h
0050h
0
55h
55h 5555h
0052h
0
55h
55h 5555h
0050h
3
55h
55h 5555h 1200h
0050h
1
00h
12h 5555h 1200h
0052h
1
00h
12h 5555h 1200h
0050h
3
00h
12h 5555h 1200h 0000h 0050h
2
00h
00h 5555h 1200h 0000h 0052h
2
00h
00h 5555h 1200h 0000h 0050h
3
00h
00h 5634h 1200h 0000h 0050h
0
34h
56h 5634h 1200h 0000h 0052h
0
34h
56h 5634h 1200h 0000h 0050h
3
34h
56h 5634h 8118h 0000h 0050h
1
18h
81h 5634h 8118h 0000h 0052h
1
18h
81h 5634h 8118h 0000h 0050h
3
18h
81h 5634h 8118h 5555h 0050h
2
55h
55h 5634h 8118h 5555h 0052h
2
55h
55h 5634h 8118h 5555h 0050h
3
Z8 Z16 P
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
<Note>
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-138
LC88 Series Chapter 5
MOV[.W] (Rd++, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 1 1][d3d2d1d0 1 s2s1s0][0 0 0 0 n11 to n8][n7 to n0]
6308H
Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
if (Rd±n) =even data :
[(Rd±n)&FFFFh]←Lobyte(Rs), [(Rd±n+1)&FFFFh]←Hibyte(Rs)
if (Rd±n) =odd data :
[(Rd±n)&FFFFh]←Hibyte(Rs), [(Rd±n-1)&FFFFh]←Lobyte(Rs)
(Rd) ← (Rd)+2, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the address derived by the arithmetic operation*1 performed on the contents of the
general-purpose register designated by Rd and n is at an even address, the instruction transfers the contents of
the lower-order 8 bits of the general-purpose register Rs to [(Rd±n)&FFFFh] and the higher-order 8 bits of
Rs to [(Rd±n+1)&FFFFh]. In the case of an odd address, the instruction transfers the contents of the
higher-order 8 bits of Rs to [(Rd±n)&FFFFh] and the lower-order 8 bits of Rs to [(Rd±n-1)&FFFFh].
Subsequently, the instruction increments the contents of Rd by 2.
The legitimate value range designated by Rd is from R0 to R15, that by Rs is from R0 to R7, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R3++, 0x50), R0
R3, #1
R1, #0x1200
(R3++, 0x50), R1
R3, #1
R2, #0x0000
(R3++, 0x50), R2
R3, #1
R0, #0x5634
(R3++, 0x50), R0
R3, #1
R1, #0x
(R3++, 0x50), R1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0000h
3
66h
66h 5555h
0000h
0
55h
55h 5555h
0002h
0
55h
55h 5555h
0000h
3
55h
55h 5555h 1200h
0000h
1
00h
12h 5555h 1200h
0002h
1
00h
12h 5555h 1200h
0000h
3
00h
12h 5555h 1200h 0000h 0000h
2
00h
00h 5555h 1200h 0000h 0002h
2
00h
00h 5555h 1200h 0000h 0000h
3
00h
00h 5634h 1200h 0000h 0000h
0
34h
56h 5634h 1200h 0000h 0002h
0
34h
56h 5634h 1200h 0000h 0000h
3
34h
56h 5634h 8118h 0000h 0000h
1
18h
81h 5634h 8118h 0000h 0002h
1
Z8 Z16 P S
0
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-139
Instructions
MOV[.W] m16, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 1 0 X 1][m7m6m5m4m3m2m1m0][i15 to i8][i7 to i0]
7900H(RAM), 7B00H(SFR)
m16 = 16bit (lower 8bit valid for operation code)
imm16 = 16bit (immediate data)
2
2
if “m16” is even: (m16+1)←Hibyte(imm16), (m16)←Lobyte(imm16)
if “m16” is odd: (m16)←Hibyte(imm16), (m16-1)←Lobyte(imm16)
(PC)←(PC)+4
Z8, Z16, P, S
[Description]
This instruction transfers 16-bit immediate data imm16 to 2-byte data memory (RAM) location or SFR (one
of the registers dedicated to control the internal peripheral devices) addressed by m16.
The 2-byte destination address is determined according to the following rules:
・If m16 is an even number, the higher-order 8 bits of imm16 is transferred to the odd address (m16+1) and
the lower-order 8 bits to the even address (m16).
・If m16 is an odd number, the higher-order 8 bits of imm16 is transferred to the odd address (m16) and the
lower-order 8 bits to the even address (m16-1).
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to 7FFFH.
The basic types of generated instruction code are 7900H (RAM) and 7B00H (SFR), respectively. The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
RAM RAM
(50h) (51h)
55h
55h
00h
12h
00h
00h
56h
34h
18h
81h
55h
55h
0x50, #0x5555
0x50, #0x1200
0x50, #0x0000
0x50, #0x3456
0x50, #0x8118
0x50, #0x5555
5-140
Z8
Z16
P
S
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
LC88 Series Chapter 5
MOV[.W] m16, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 0 X 1 s2s1s0 1][m7m6m5m4m3m2m1m0]
9100H(RAM), B100H(SFR)
m16 = 16bit (lower 8bit valid for operation code)
Rs = 3bit (R select)
1
1
if m16 is even: (m16+1)←Hibyte(Rs), (m16)←Lobyte(Rs)
if m16 is odd: (m16)←Hibyte(Rs), (m16-1)←Lobyte(Rs)
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents (16 bits) of the general-purpose register designated by Rs to 2-byte data
memory (RAM) location or SFR (one of the registers dedicated to control the internal peripheral devices)
addressed by m16. The legitimate value range designated by Rs is from R0 to R7.
The 2-byte destination address is determined according to the following rules:
・If m16 is an even number, the higher-order 8 bits of Rs are transferred to the odd address (m16+1) and the
lower-order 8 bits to the even address (m16).
If m16 is an odd number, the higher-order 8 bits of Rs are transferred to the odd address (m16) and the
lower-order 8 bits to the even address (m16-1).
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to 7FFFH.
The basic types of generated instruction code are 9100H (RAM) and B100H (SFR), respectively. The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
R0, #0x5555
R3, #0x3333
0x50, R0
R1, #0x1200
R3, #0x7777
0x50, R1
R2, #0x0000
R3, #0x3333
0x50, R2
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
5555h
0
5555h
3333h
3
55h
55h 5555h
3333h
0
55h
55h 5555h 1200h
3333h
1
55h
55h 5555h 1200h
7777h
3
00h
12h 5555h 1200h
7777h
1
00h
12h 5555h 1200h 0000h 7777h
2
00h
12h 5555h 1200h 0000h 3333h
3
00h
00h 5555h 1200h 0000h 3333h
2
5-141
Z8 Z16 P
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
S
0
0
0
0
1
0
0
0
0
Instructions
MOV[.W] Rd, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 0 d2d1d0 1][i7i6i5i4i3i2i1i0]
Rd = 3bit(R select), imm8 = 8bit(immediate data)
1
1
(Rd) ←16bit data(Hibyte=00H, Lobyte=#imm8), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
2100H
[Description]
This instruction transfers immediate data designated by imm8 to the general-purpose register designated by
Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by imm8 is from 0 to FFh.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
R0,
R1,
#0x55
#0x00
#0x34
#0x8118
#0xFF
#0x33
0055h
0055h
0055h
0055h
00FFh
00FFh
N3 to
N0
0
0000h
1
0000h 0034h
2
0000h 0034h 8118h
3
0000h 0034h 8118h
0
0033h 0034h 8118h
1
R1
R2
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
5-142
R3
Z8
Z16
P
S
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
LC88 Series Chapter 5
MOV[.W] Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 0 1 1 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select), imm16 = 16bit(immediate data)
2
2
(Rd)←#imm16, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
3130H
[Description]
This instruction transfers immediate data designated by imm16 to the general-purpose register designated by
Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 is from 0 to FFFF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
R0,
R1,
R2,
R3,
R0,
R1,
R2,
#0x5555
#0x1200
#0x0000
#0x5634
#0x8118
#0x00FF
#0x5555
R0
R1
R2
R3
5555h
5555h
5555h
5555h
8118h
8118h
8118h
1200h
1200h
1200h
1200h
00FFh
00FFh
0000h
0000h
0000h
0000h
5555h
5634h
5634h
5634h
5634h
5-143
N3 to
N0
0
1
2
3
0
1
2
Z8
Z16
P
S
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
Instructions
MOV[.W] Rd, (Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 0 1][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
if (Rs) =even data : Hibyte(Rd)←[Rs+1], Lobyte(Rd)← [Rs]
if (Rs) =odd data : Hibyte(Rd)←[Rs], Lobyte [Rs-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7100H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
addressed by the contents of the general-purpose register designated by Rs is at an even address, the
instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and the
contents of [Rs + 1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction
transfers contents of [Rs] to the higher-order 8-bit positions of Rd and the contents of [Rs - 1] to the
lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
R3, #0x0050
0x50, #0x5555
R0, (R3)
0x50, #0x1200
R1, (R3)
0x50, #0x0000
R2, (R3)
0x50, #0x5634
R0, (R3)
0x50, #0x8118
R1, (R3)
0x50, #0x5555
R2, (R3)
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0050h
3
55h
55h
0050h
3
55h
55h 5555h
0050h
0
00h
12h 5555h
0050h
0
00h
12h 5555h 1200h
0050h
1
00h
00h 5555h 1200h
0050h
1
00h
00h 5555h 1200h 0000h 0050h
2
34h
56h 5555h 1200h 0000h 0050h
2
34h
56h 5634h 1200h 0000h 0050h
0
18h
81h 5634h 1200h 0000h 0050h
0
18h
81h 5634h 8118h 0000h 0050h
1
55h
55h 5634h 8118h 0000h 0050h
1
55h
55h 5634h 8118h 5555h 0050h
2
<Note>
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-144
Z8 Z16 P
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
S
0
0
0
0
0
0
0
0
0
1
1
0
0
LC88 Series Chapter 5
MOV[.W] Rd, (--Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 0 1][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rs)←(Rs)-2
if (Rs) = even data : Hibyte(Rd)←[Rs+1], Lobyte(Rd)← [Rs]
if (Rs) = odd data : Hibyte(Rd)←[Rs], Lobyte(Rd)← [Rs-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6900H
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rs.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location addressed by the contents of the general-purpose register Rs is at an even address, the
instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and the
contents of [Rs + 1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction
transfers contents of [Rs] to the higher-order 8-bit positions of Rd and the contents of [Rs - 1] to the
lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
R3, #0x0052
0x50, #0x5555
R0, (--R3)
R3, #1
0x50, #0x1200
R1, (--R3)
R3, #1
0x50, #0x0000
R2, (--R3)
R3, #1
0x50, #0x5634
R0, (--R3)
R3, #1
0x50, #0x8118
R1, (--R3)
R3, #1
0x50, #0x5555
R2, (--R3)
R3, #1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0052h
3
55h
55h
0052h
3
55h
55h 5555h
0050h
0
55h
55h 5555h
0052h
3
00h
12h 5555h
0052h
3
00h
12h 5555h 1200h
0050h
1
00h
12h 5555h 1200h
0052h
3
00h
00h 5555h 1200h
0052h
3
00h
00h 5555h 1200h 0000h 0050h
2
00h
00h 5555h 1200h 0000h 0052h
3
34h
56h 5555h 1200h 0000h 0052h
3
34h
56h 5634h 1200h 0000h 0050h
0
34h
56h 5634h 1200h 0000h 0052h
3
18h
81h 5634h 1200h 0000h 0052h
3
18h
81h 5634h 8118h 0000h 0050h
1
18h
81h 5634h 8118h 0000h 0052h
3
55h
55h 5634h 8118h 0000h 0052h
3
55h
55h 5634h 8118h 5555h 0050h
2
55h
55h 5634h 8118h 5555h 0052h
3
<Note>
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-145
Z8 Z16 P
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
S
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Instructions
MOV[.W] Rd, Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 0 0 1][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
if (Rs±n) =even data :
Hibyte(Rd)←[(Rs±n+1)&FFFFh], Lobyte(Rd)← [(Rs±n)&FFFFh]
if (Rs±n) =odd data :
Hibyte(Rd)←[(Rs±n)&FFFFh], Lobyte(Rd)←[(Rs±n-1)&FFFFh]
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
7108H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the address derived by the arithmetic operation ＊ 1 performed on the contents of the
general-purpose register designated by Rs and n is at an even address, the instruction transfers the contents to
the lower-order 8-bit positions of the general-purpose register Rd and the contents of [(Rs±n+1)&FFFFh] to
the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction transfers contents of [(Rs
±n)&FFFFh] to the higher-order 8-bit positions of Rd and the contents of [(Rs±n-1)&FFFFh] to the
lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rs is from R0 to R15, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
R3, #0x0000
0x50, #0x5555
R0, (R3, 0x50)
0x50, #0x1200
R1, (R3, 0x50)
0x50, #0x0000
R2, (R3, 0x50)
0x50, #0x5634
R0, (R3, 0x50)
0x50, #0x8118
R1, (R3, 0x50)
0x50, #0x5555
R2, (R3, 0x50)
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0000h
3
55h
55h
0000h
3
55h
55h 5555h
0000h
0
00h
12h 5555h
0000h
0
00h
12h 5555h 1200h
0000h
1
00h
00h 5555h 1200h
0000h
1
00h
00h 5555h 1200h 0000h 0000h
2
34h
56h 5555h 1200h 0000h 0000h
2
34h
56h 5634h 1200h 0000h 0000h
0
18h
81h 5634h 1200h 0000h 0000h
0
18h
81h 5634h 8118h 0000h 0000h
1
55h
55h 5634h 8118h 0000h 0000h
1
55h
55h 5634h 8118h 5555h 0000h
2
<Note>
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-146
Z8 Z16 P
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
S
0
0
0
0
0
0
0
0
0
1
1
0
0
LC88 Series Chapter 5
MOV[.W] Rd, (--Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 0 0 1][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rs)←(Rs)-2
if (Rs±n) =even data :
Hibyte(Rd)←[(Rs±n+1)&FFFFh], Lobyte(Rd)← [(Rs±n)&FFFFh]
if (Rs±n) =odd data :
Hibyte(Rd)←[(Rs±n)&FFFFh], Lobyte(Rd) ← [(Rs±n-1)&FFFFh]
((PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
6908H
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rs.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by the address derived by the arithmetic operation＊1 performed on the contents of
the general-purpose register Rs and n is at an even address, the instruction transfers the contents to the
lower-order 8-bit positions of the general-purpose register Rd and the contents of [(Rs±n+1)&FFFFh] to the
higher-order 8-bit positions of Rd. In the case of an odd address, the instruction transfers contents of [(Rs±
n)&FFFFh] to the higher-order 8-bit positions of Rd and the contents of [(Rs±n-1)&FFFFh] to the
lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rs is from R0 to R15, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
INC
MOV.W
MOV.W
R3, #0x0002
0x50, #0x5555
R0, (--R3, 0x50)
R3, #1
0x50, #0x1200
R1, (--R3, 0x50)
R3, #1
0x50, #0x0000
R2, (--R3, 0x50)
R3, #1
0x50, #0x5634
R0, (--R3, 0x50)
R3, #1
0x50, #0x8118
R1, (--R3, 0x50)
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0002h
3
55h
55h
0002h
3
55h
55h 5555h
0000h
0
55h
55h 5555h
0002h
3
00h
12h 5555h
0002h
3
00h
12h 5555h 1200h
0000h
1
00h
12h 5555h 1200h
0002h
3
00h
00h 5555h 1200h
0002h
3
00h
00h 5555h 1200h 0000h 0000h
2
00h
00h 5555h 1200h 0000h 0002h
3
34h
56h 5555h 1200h 0000h 0002h
3
34h
56h 5634h 1200h 0000h 0000h
0
34h
56h 5634h 1200h 0000h 0002h
3
18h
81h 5634h 1200h 0000h 0002h
3
18h
81h 5634h 8118h 0000h 0000h
1
<Note>
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-147
Z8 Z16 P
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Instructions
MOV[.W] Rd, (Rs ++)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 0 1][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
If (Rs) = even data : Hibyte(Rd)←[Rs+1], Lobyte(Rd)← [Rs]
If (Rs) = odd data : Hibyte(Rd)←[Rs], Lobyte(Rd)←[Rs-1]
(Rs)←(Rs)+2, (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6100H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
addressed by the contents of the general-purpose register designated by Rs is an even address, the instruction
transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and the contents of
[Rs + 1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction transfers
contents of [Rs] to the higher-order 8-bit positions of Rd and the contents of [Rs - 1] to the lower-order 8-bit
positions of Rd. Subsequently, the instruction increments the contents of Rs by 2.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
R3, #0x0050
0x50, #0x5555
R0, (R3++)
R3, #1
0x50, #0x1200
R1, (R3++)
R3, #1
0x50, #0x0000
R2, (R3++)
R3, #1
0x50, #0x5634
R0, (R3++)
R3, #1
0x50, #0x8118
R1, (R3++)
R3, #1
0x50, #0x5555
R2, (R3++)
R3, #1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0050h
3
55h
55h
0050h
3
55h
55h 5555h
0052h
0
55h
55h 5555h
0050h
3
00h
12h 5555h
0050h
3
00h
12h 5555h 1200h
0052h
1
00h
12h 5555h 1200h
0050h
3
00h
00h 5555h 1200h
0050h
3
00h
00h 5555h 1200h 0000h 0052h
2
00h
00h 5555h 1200h 0000h 0050h
3
34h
56h 5555h 1200h 0000h 0050h
3
34h
56h 5634h 1200h 0000h 0052h
0
34h
56h 5634h 1200h 0000h 0050h
3
18h
81h 5634h 1200h 0000h 0050h
3
18h
81h 5634h 8118h 0000h 0052h
1
18h
81h 5634h 8118h 0000h 0050h
3
55h
55h 5634h 8118h 0000h 0050h
3
55h
55h 5634h 8118h 5555h 0052h
2
55h
55h 5634h 8118h 5555h 0050h
3
<Note>
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-148
Z8 Z16 P
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
LC88 Series Chapter 5
MOV[.W] Rd, (Rs++, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 0 0 1][s3s2s1s0 1 d2d1d0][0 0 0 0 n11 to n8][n7 to n0]
6108H
Rd = 3bit(R select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
if (Rs±n) =even data :
Hibyte(Rd)←[(Rs±n+1)&FFFFh], Lobyte(Rd)←[(Rs±n)&FFFFh]
if (Rs±n) =odd data :
Hibyte(Rd)←[(Rs±n)&FFFFh], Lobyte(Rd)←[(Rs±n-1)&FFFFh]
(Rs)←(Rs)+2, (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the address derived by the arithmetic operation ＊ 1 performed on the contents of the
general-purpose register designated by Rs and n is at an even address, the instruction transfers the contents to
the lower-order 8-bit positions of the general-purpose register Rd and the contents of [(Rs±n+1)&FFFFh] to
the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction transfers contents of [(Rs
±n)&FFFFh] to the higher-order 8-bit positions of Rd and the contents of [(Rs±n-1)&FFFFh] to the
lower-order 8-bit positions of Rd. Subsequently, the instruction increments the contents of Rs by 2.
The legitimate value range designated by Rd is from R0 to R7, that by Rs is from R0 to R15, and that by n is
that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from a 16-bit arithmetic operation is ignored.
[Example]
MOV.W
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
MOV.W
MOV.W
DEC
R3, #0x0000
0x50, #0x5555
R0, (R3++, 0x50)
R3, #1
0x50, #0x1200
R1, (R3++, 0x50)
R3, #1
0x50, #0x0000
R2, (R3++, 0x50)
R3, #1
0x50, #0x5634
R0, (R3++, 0x50)
R3, #1
0x50, #0x8118
R1, (R3++, 0x50)
R3, #1
0x50, #0x5555
R2, (R3++, 0x50)
R3, #1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
0000h
3
55h
55h
0000h
3
55h
55h 5555h
0002h
0
55h
55h 5555h
0000h
3
00h
12h 5555h
0000h
3
00h
12h 5555h 1200h
0002h
1
00h
12h 5555h 1200h
0000h
3
00h
00h 5555h 1200h
0000h
3
00h
00h 5555h 1200h 0000h 0002h
2
00h
00h 5555h 1200h 0000h 0000h
3
34h
56h 5555h 1200h 0000h 0000h
3
34h
56h 5634h 1200h 0000h 0002h
0
34h
56h 5634h 1200h 0000h 0000h
3
18h
81h 5634h 1200h 0000h 0000h
3
18h
81h 5634h 8118h 0000h 0002h
1
18h
81h 5634h 8118h 0000h 0000h
3
55h
55h 5634h 8118h 0000h 0000h
3
55h
55h 5634h 8118h 5555h 0002h
2
55h
55h 5634h 8118h 5555h 0000h
3
<Note>
This instruction takes 4 cycles to transfer the contents to program memory (ROM) to Rd.
5-149
Z8 Z16 P
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Instructions
MOV[.W] Rd, m16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 0 X 0 d2d1d0 1][m7m6m5m4m3m2m1m0]
8100H(RAM), A100H(SFR)
Rd = 3bit(R select), m16 = 16bit(Lower 8bit valid for operation code)
1
1
if “m16” is even
: Hibyte(Rd)←(m16+1), Lobyte(Rd)←(m16)
if “m16” is odd
: Hibyte(Rd)←(m16), Lobyte(Rd)←(m16-1)
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of 2-byte data memory (RAM) location or SFR (one of the registers
dedicated to control the internal peripheral devices) designated by m16 to the lower-order 8-bit positions of
the general-purpose register designated by Rd. The legitimate value range designated by Rd is from R0 to R7.
The 2-byte destination address is determined according to the following rules:
・If m16 is an even number, the contents of the odd address (m16+1) are transferred to the higher-order 8-bit
positions of Rd and those of the even address (m16) to the lower-order 8-bit positions of Rd.
・If m16 is an odd number, the contents of the odd address (m16) are transferred to the higher-order 8-bit
positions of Rd and those of the even address (m16–1) to the lower-order 8-bit positions of Rd.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (second operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to 7FFFH.
The basic types of generated instruction code are 8100H (RAM) and A100H (SFR), respectively. The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
0x50, #0x05555
R3, #05555
R0, 0x50
0x50, #0x1200
R3, #06666
R1, 0x50
0x50, #0x0000
R3, #0x3333
R2, 0x50
0x50, #0x3456
R3, #0x6655
R0, 0x50
0x50, #0x8118
R3, #0x3366
R1, 0x50
0x50, #0x5555
R3, #0x6355
R2, 0x50
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
55h
55h
55h
55h
5555h
3
55h
55h 5555h
5555h
0
00h
12h 5555h
5555h
0
00h
12h 5555h
6666h
3
00h
12h 5555h 1200h
6666h
1
00h
00h 5555h 1200h
6666h
1
00h
00h 5555h 1200h
3333h
3
00h
00h 5555h 1200h 0000h 3333h
2
56h
34h 5555h 1200h 0000h 3333h
2
56h
34h 5555h 1200h 0000h 6655h
3
56h
34h 3456h 1200h 0000h 6655h
0
18h
81h 3456h 1200h 0000h 6655h
0
18h
81h 3456h 1200h 0000h 3366h
3
18h
81h 3456h 8118h 0000h 3366h
1
55h
55h 3456h 8118h 0000h 3366h
1
55h
55h 3456h 8118h 0000h 6355h
3
55h
55h 3456h 8118h 5555h 6355h
2
5-150
Z8 Z16 P
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
LC88 Series Chapter 5
MOV[.W] Rｘ, #ｉmm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 1 1 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx)←16bit data(Hibyte=00H, Lobyte=#imm8),
Z8, Z16, P, S
4700H
(PC)←(PC)+2
[Description]
This instruction transfers immediate data designated by imm8 to the general-purpose register Rx designated
indirectly by the value of bits 12 to 15 (N0 to N3) of the PSW.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
MOV.W
DEC
MOV.W
INC
MOV.W
SWPB
MOV.W
MOV.W
MOV.W
R3, #0x3456
R2, #0x2222
R1, #0x1111
R0, #0x0000
0x50, #0x6666
Rx, #0x55
R1
Rx, #0x00
R2
Rx, #0x34
R3
Rx, #0x81
0x50, #0x8118
Rx, #0xFF
NOT
R0
MOV.W
Rx, #0x55
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
3456h
3
2222h 3456h
2
1111h 2222h 3456h
1
0000h 1111h 2222h 3456h
0
66h
66h 0000h 1111h 2222h 3456h
0
66h
66h 0055h 1111h 2222h 3456h
0
66h
66h 0055h 1110h 2222h 3456h
1
66h
66h 0055h 0000h 2222h 3456h
1
66h
66h 0055h 0000h 2223h 3456h
2
66h
66h 0055h 0000h 0034h 3456h
2
66h
66h 0055h 0000h 0034h 5634h
3
66h
66h 0055h 0000h 0034h 0081h
3
18h
81h 0055h 0000h 0034h 0081h
3
18h
81h 0055h 0000h 0034h 00FFh
3
FFAA
18h
81h
0000h 0034h 00FFh
0
h
18h
81h 0055h 0000h 0034h 00FFh
0
<Note>
The higher-order 8-bit positions of Rx are loaded with 00H.
5-151
Z8 Z16 P
S
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Instructions
MOVF.B
(Rb, Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 1 0][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
7608H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
[Rb<<16+Rd±n]←Lobyte (Rs), (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of the lower-order 8 bits of the general-purpose register designated by
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of the base register (Rb)
and the lower-order 16 bits are the result of the arithmetic operation＊1 performed on the contents of Rd and n.
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits is
reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
R0
R1
R2
R3
R8
N3 to
Z8 Z16 P S
N0
-
-
-
-
-
-
-
-
-
-
- -
MOV.W
MOV.W
MOV.W
0x50, #0x6666
R3, #0x0000
R0, #0x5555
66h
66h
66h
66h
66h
66h
5555h
-
-
0000h
0000h
-
3
0
0
1
0
0
1
0
0 0
0 0
0 0
MOV.W
MOVF.B
MOV.W
MOVF.B
R8, #0x0000
66h
(R8, R3, 0x50), R0 55h
R1, #0x1200
55h
(R8, R3, 0x50), R1 00h
66h
66h
66h
66h
5555h
5555h
5555h 1200h
5555h 1200h
-
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
MOV.W
MOVF.B
MOV.W
R2, #0x0000
00h
(R8, R3, 0x50), R2 00h
R0, #0x5634
00h
66h
66h
66h
5555h 1200h 0000h 0000h 0000h
5555h 1200h 0000h 0000h 0000h
5634h 1200h 0000h 0000h 0000h
2
2
0
1
1
0
1
1
0
0 0
0 0
1 0
MOVF.B
MOV.W
MOVF.B
MOV.W
(R8, R3, 0x50), R0 34h
R1, #0x1881
34h
(R8, R3, 0x50), R1 81h
R2, #0x5555
81h
66h
66h
66h
66h
5634h
5634h
5634h
5634h
0000h
0000h
0000h
0000h
0
1
1
2
0
0
0
0
0
0
0
0
1
0
0
0
MOVF.B
(R8, R3, 0x50), R2 55h
66h
5634h 1881h 5555h 0000h 0000h
2
0
0
0 0
1200h
1881h
1881h
1881h
0000h
0000h
0000h
5555h
0000h
0000h
0000h
0000h
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-152
0
0
0
0
0
0
1
0
LC88 Series Chapter 5
MOVF.B
(Rb, --Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 1 0][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
6E08H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
(Rd)←(Rd)-1, if Borrow : (Rb)←(Rb)-1
[Rb<<16+Rd±n]←Lobyte(Rs)
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register Rd. Rd is decremented if
a borrow occurs as the result of the subtraction performed on Rd.
Subsequently, the instruction transfers the contents of the lower-order 8 bits of the general-purpose register
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of the base register (Rb)
and the lower-order 16 bits are the result of the arithmetic operation＊1 performed on the contents of Rd and n.
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
0x50, #0x6666
R3, #0x0001
R0, #0x5555
R8, #0x0000
(R8, --R3, 0x50),
R3
R1, #0x1200
(R8, --R3, 0x50),
R3
R2, #0x0000
(R8, --R3, 0x50),
R3
R0, #0x5634
(R8, --R3, 0x50),
R3
R1, #0x1881
(R8, --R3, 0x50),
R3
R2, #0x5555
(R8, --R3, 0x50),
R3
RAM
(50h)
66h
66h
66h
66h
R0 55h
55h
55h
R1 00h
00h
00h
R2 00h
00h
00h
R0 34h
34h
34h
R1 81h
81h
81h
R2 55h
55h
RAM
(51h)
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
-
-
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0001h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
N0
3
0
8
0
3
1
1
3
2
2
3
0
0
3
1
1
3
2
2
3
Z8 Z16 P S
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Instructions
MOVF.B
(Rb, Rd++, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 1 0][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
6608H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
[Rb<<16+Rd±n] ← Lobyte (Rs)
(Rd)←(Rd)+1, if Carry : (Rb)←(Rb)+1
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of the lower-order 8 bits of the general-purpose register designated by
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of the base register (Rb)
and the lower-order 16 bits are the result of the arithmetic operation＊1 performed on the contents of Rd and n.
Subsequently, the contents of Rd are incremented by 1. Rb is incremented if a carry occurs as the result of the
addition performed on Rd.
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits is
reflected in the higher-order 16 bits.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R8, R3++, 0x50),
R3
R1, #0x1200
(R8, R3++, 0x50),
R3
R2, #0x0000
(R8, R3++, 0x50),
R3
R0, #0x5634
(R8, R3++, 0x50),
R3
R1, #0x1881
(R8, R3++, 0x50),
R3
R2, #0x5555
(R8, R3++, 0x50),
R3
R0
R1
R2
R0
R1
R2
RAM RAM
(50h) (51h)
66h 66h
66h 66h
66h 66h
55h 66h
55h 66h
55h 66h
00h 66h
00h 66h
00h 66h
00h 66h
00h 66h
00h 66h
34h 66h
34h 66h
34h 66h
81h 66h
81h 66h
81h 66h
55h 66h
55h 66h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
N0
3
0
0
3
1
1
3
2
2
3
0
0
3
1
1
3
2
2
3
Z8 Z16 P S
0
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
0
0
1
0
0
1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-154
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOVF.B
(Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
[R8<<16+Rd]←Lobyte(Rs), (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7600H
[Description]
This instruction transfers the contents of the lower-order 8 bits of the general-purpose register designated by
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3), R0
R1, #0x1200
(R3), R1
R2, #0x0000
(R3), R2
R0, #0x5634
(R3), R0
R1, #0x1881
(R3), R1
R2, #0x5555
(R3), R2
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0050h
3
66h
66h 5555h
0050h
0
55h
66h 5555h
0050h
0
55h
66h 5555h 1200h
0050h
1
00h
66h 5555h 1200h
0050h
1
00h
66h 0055h 1200h 0000h 0050h
2
00h
66h 0055h 1200h 0000h 0050h
2
00h
66h 5634h 1200h 0000h 0050h
0
34h
66h 5634h 1200h 0000h 0050h
0
34h
66h 5634h 1881h 0000h 0050h
1
34h
66h 5634h 1881h 0000h 0050h
1
34h
66h 5634h 1881h 5555h 0050h
2
81h
66h 5634h 1881h 5555h 0050h
2
Z8 Z16 P
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
S
0
0
0
0
0
0
0
0
0
0
0
1
0
0
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-155
Instructions
MOVF.B
(--Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
(Rd)←(Rd)-1, if Borrow : (R8)←(R8)-1
[R8<<16+Rd]←Lobyte(Rs)
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6E00H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register designated by Rd. R8 is
decremented if a borrow occurs as the result of the subtraction performed on Rd.
Subsequently, the instruction transfers the contents of the lower-order 8 bits of the general-purpose register
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7
.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
0x50, #0x6666
R3, #0x0051
R0, #0x5555
(--R3), R0
R3
R1, #0x1200
(--R3), R1
R3
R2, #0x0000
(--R3), R2
R3
R0, #0x5634
(--R3), R0
R3
R1, #0x1881
(--R3), R1
RAM RAM
N3 to
R0
R1
R2
R3
N0
(50h) (51h)
66h
66h
66h
66h
0051h
3
66h
66h 5555h
0051h
0
55h
66h 5555h
0050h
0
55h
66h 5555h
0051h
3
55h
66h 5555h 1200h
0051h
1
00h
66h 5555h 1200h
0050h
1
00h
66h 5555h 1200h
0051h
3
00h
66h 5555h 1200h 0000h 0051h
2
00h
66h 5555h 1200h 0000h 0050h
2
00h
66h 5555h 1200h 0000h 0051h
3
00h
66h 5634h 1200h 0000h 0051h
0
34h
66h 5634h 1200h 0000h 0050h
0
34h
66h 5634h 1200h 0000h 0051h
3
34h
66h 5634h 1881h 0000h 0051h
1
81h
66h 5634h 1881h 0000h 0050h
1
Z8 Z16 P
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-156
LC88 Series Chapter 5
MOVF.B
(Rd++), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 1 0][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
[R8<<16+Rd]←Lobyte(Rs)
(Rd)←(Rd)+1, if Carry : (R8)←(R8)+1
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6600H
[Description]
This instruction transfers the contents of the lower-order 8 bits of the general-purpose register designated by
Rs to the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of Rd. Subsequently, the instruction adds 1 to the contents of Rd. R8 is
incremented if a carry occurs as the result of the addition performed on Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3++), R0
R3
R1, #0x1200
(R3++), R1
R3
R2, #0x0000
(R3++), R2
R3
R0, #0x5634
(R3++), R0
R3
R1, #0x1881
(R3++), R1
R3
R2, #0x5555
(R3++), R2
R3
RAM
(50h)
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
81h
81h
81h
55h
55h
RAM
(51h)
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
66h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1881h
1881h
1881h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
N3 to
N0
3
0
0
3
1
1
3
2
2
3
0
0
3
1
1
3
2
2
3
Z8 Z16 P S
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-157
Instructions
MOVF.B
Rd, (Rb, Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 0 0][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0]
7408H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
Lobyte (Rd)← [Rb<<16+Rs±n], (PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the 32-bit address of which the higher-order 16 bits are the
contents of the general-purpose register designated by the base register (Rb) and the lower-order 16 bits are
the result of the arithmetic operation＊1 performed on the contents of Rs and n, to the lower-order 8-bit
positions of the general-purpose register Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
R3, #0x0000
0x50, #0x5555
R0, (R8, R3, 0x50)
0x50, #0x1200
R1, (R8, R3, 0x50)
0x50, #0x0000
R2, (R8, R3, 0x50)
0x50, #0x5634
R0, (R8, R3, 0x50)
0x50, #0x1881
R1, (R8, R3, 0x50)
0x50, #0x5555
R2, (R8, R3, 0x50)
55h
55h
00h
00h
00h
00h
34h
34h
81h
81h
55h
55h
55h
55h
12h
12h
00h
00h
56h
56h
18h
18h
55h
55h
R0
R1
R2
R3
R8
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0081h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0055h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-158
3
3
0
0
1
1
2
2
0
0
1
1
2
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
LC88 Series Chapter 5
MOVF.B
Rd, (Rb, --Rs,±n )
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 0 0][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0]
6C08H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rs)←(Rs)-1, if Borrow : (Rb)←(Rb)-1
Lobyte (Rd)← [Rb<<16+Rs±n]
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register designated by Rs. Rb is
decremented if a borrow occurs as the result of the subtraction performed on Rs.
Subsequently, the instruction transfers the contents of the data memory (RAM) location, special function
register (SFR), or program memory (ROM) location designated by the 32-bit address, of which the
higher-order 16 bits are the contents of the base register (Rb) and the lower-order 16 bits are the result of the
arithmetic operation＊1 performed on the contents of Rs and n, to the lower-order 8-bit positions of the
general-purpose register Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
MOV.W
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
RAM
(50h)
R3, #0x0001
0x50, #0x5555
55h
R0, (R8, --R3, 0x50) 55h
R3
55h
0x50, #0x1200
00h
R1, (R8, --R3, 0x50) 00h
R3
00h
0x50, #0x0000
00h
R2, (R8, --R3, 0x50) 00h
R3
00h
0x50, #0x5634
34h
R0, (R8, --R3, 0x50) 34h
R3
34h
0x50, #0x1881
81h
R1, (R8, --R3, 0x50) 81h
R3
81h
0x50, #0x5555
55h
R2, (R8, --R3, 0x50) 55h
R3
55h
RAM
(51h)
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
18h
18h
18h
55h
55h
55h
R0
R1
R2
R3
R8
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0081h
0081h
0081h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0055h
0055h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0001h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
- - 3
0 0 1 0
3
0 0 0 0
0
0 0 0 0
3
0 0 1 0
3
1 0 0 0
1
1 1 0 0
3
0 0 1 0
3
1 1 0 0
2
1 1 0 0
3
0 0 1 0
3
0 0 1 0
0
0 0 1 0
3
0 0 1 0
3
0 0 0 0
1
0 0 0 1
3
0 0 1 0
3
0 0 0 0
2
0 0 0 0
3
0 0 1 0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-159
Instructions
MOVF.B
Rd, (Rb, Rs++, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 0 0][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0]
6408H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
Lobyte (Rd)← [Rb<<16+Rs±n]
(Rs)←(Rs)+1, if Carry : (Rb)←(Rb)+1
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the
contents of the general-purpose register designated by the base register (Rb) and the lower-order 16 bits are
the result of the arithmetic operation＊1 performed on the contents of Rs and n, to the lower-order 8-bit
positions of the general-purpose register Rd. Subsequently, the instruction adds 1 to the contents of Rs. Rb is
incremented if a carry occurs as the result of the addition performed on Rs.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
R3, #0x0000
0x50, #0x5555
R0, (R8, R3++,
R3
0x50, #0x1200
R1, (R8, R3++,
R3
0x50, #0x0000
R2, (R8, R3++,
R3
0x50, #0x5634
R0, (R8, R3++,
R3
0x50, #0x1881
R1, (R8, R3++,
R3
0x50, #0x5555
R2, (R8, R3++,
R3
0x50)
0x50)
0x50)
0x50)
0x50)
0x50)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
81h
81h
81h
55h
55h
55h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
18h
18h
18h
55h
55h
55h
R0
R1
R2
R3
R8
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0081h
0081h
0081h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0055h
0055h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
<Note>
The higher-order 8 bits of Rd are loaded with 00H.
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-160
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
3
3
2
3
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
LC88 Series Chapter 5
MOVF.B
Rd, (Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
Lobyte (Rd)← [R8<<16+Rs], (PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7400H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the
contents of R8 (Rb0) and the lower-order 16 bits are the contents of the general-purpose register designated
by Rs, to the lower-order 8-bit positions of the general-purpose register Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
MOV.W
MOVF.B
R3, #0x0050
0x50, #0x5555
R0, (R3)
0x50, #0x1200
R1, (R3)
0x50, #0x0000
R2, (R3)
0x50, #0x5634
R0, (R3)
0x50, #0x1881
R1, (R3)
0x50, #0x5555
R2, (R3)
RAM
(50h)
55h
55h
00h
00h
00h
00h
34h
34h
81h
81h
55h
55h
RAM
(51h)
55h
55h
12h
12h
00h
00h
56h
56h
18h
18h
55h
55h
R0
R1
R2
R3
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0081h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0055h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
N3 to
N0
3
3
0
0
1
1
2
2
0
0
1
1
2
<Note>
In this case, Rb0 refers to R8.
The higher-order 8 bits of Rd are loaded with 00H.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-161
Z8 Z16 P S
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Instructions
MOVF.B
Rd, (--Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rs)←(Rs)-1, if Borrow : (R8)←(R8)-1
Lobyte (Rd)← [R8<<16+Rs]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6C00H
[Description]
This instruction firstly subtracts 1 from the contents of the general-purpose register designated by Rs. R8 is
decremented if a borrow occurs as the result of the subtraction performed on Rs.
Subsequently, the instruction transfers the contents of the data memory (RAM) location, special function
register (SFR), or program memory (ROM) location designated by the 32-bit address, of which the
higher-order 16 bits are the contents of R8 (Rb0) and the lower-order 16 bits are the contents of Rs, to the
lower-order 8-bit positions of the general-purpose register Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
INC
MOV.W
MOVF.B
R3, #0x0051
0x50, #0x5555
R0, (--R3)
R3
0x50, #0x1200
R1, (--R3)
R3
0x50, #0x0000
R2, (--R3)
R3
0x50, #0x5634
R0, (--R3)
R3
0x50, #0x1881
R1, (--R3)
RAM
(50h)
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
81h
81h
RAM
(51h)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
18h
18h
R0
R1
R2
R3
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
0051h
0051h
0050h
N3 to
N0
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
<Note>
In this case, Rb0 refers to R8.
The higher-order 8 bits of Rd are loaded with 00H.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-162
Z8 Z16 P
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
LC88 Series Chapter 5
MOVF.B
Rd, (Rs++)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 0 0][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
Lobyte (Rd) ← [R8<<16+Rs]
(Rs)←(Rs)+1, if Carry : (R8)←(R8)+1
(PC) ← (PC)+2
Z8, Z16, P, S, N0 to N3
6400H
[Description]
This instruction transfers the contents of the data memory (RAM) location, special function register (SFR), or
program memory (ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the
contents of R8 (Rb0) and the lower-order 16 bits are the contents of the general-purpose register designated
by Rs, to the lower-order 8-bit positions of the general-purpose register Rd. Subsequently, the instruction
adds 1 to the contents of Rs. R8 is incremented if a carry occurs as the result of the addition performed on Rs.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
DEC
MOV.W
MOVF.B
R3, #0x0050
0x50, #0x5555
R0, (R3++)
R3
0x50, #0x1200
R1, (R3++)
R3
0x50, #0x0000
R2, (R3++)
R3
0x50, #0x5634
R0, (R3++)
R3
0x50, #0x1881
R1, (R3++)
RAM
(50h)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
81h
81h
RAM
(51h)
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
18h
18h
R0
R1
R2
R3
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0055h
0034h
0034h
0034h
0034h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0081h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
0050h
0050h
0051h
N3 to
N0
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
<Note>
In this case, Rb0 refers to R8.
The higher-order 8 bits of Rd are loaded with 00H.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-163
Z8 Z16 P S
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Instructions
MOVF[.W] (Rb, Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 1 1][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
7708H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
if (Rd±n) = even data : [Rb<<16+Rd±n+1]
←Hibyte(Rs),
[Rb<<16+Rd±n]
←Lobyte (Rs)
if (Rd±n) =odd data
: [Rb<<16+Rd±n]
←Hibyte(Rs),
[Rb<<16+Rd±n-1]
←Lobyte (Rs)
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of the general-purpose
register designated by the base register (Rb) and the lower-order 16 bits are the result of the arithmetic
operation＊1 performed on the contents of Rd and n, is at an even address, the instruction transfers the
contents of the lower-order 8 bits of Rs to [Rb<<16+Rd±n] and the higher-order 8 bits of Rs to
[Rb<<16+Rd±n+1].
In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits of Rs to
[Rb<<16+Rd±n] and the lower-order 8 bits of Rs to [Rb<<16+Rd±n-1].
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R8, R3, 0x50),
R1, #0x1200
(R8, R3, 0x50),
R2, #0x0000
(R8, R3, 0x50),
R0, #0x5634
(R8, R3, 0x50),
R1, #0x8118
(R8, R3, 0x50),
R2, #0x5555
(R8, R3, 0x50),
R0
R1
R2
R0
R1
R2
66h
66h
66h
55h
55h
00h
00h
00h
00h
34h
34h
18h
18h
55h
66h
66h
66h
55h
55h
12h
12h
00h
00h
56h
56h
81h
81h
55h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
3
0
0
1
1
2
2
0
0
1
1
2
2
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-164
LC88 Series Chapter 5
MOVF[.W] (Rb, --Rd, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 1 1][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
6F08H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
(Rd)←(Rd)-2, if Borrow : (Rb)←(Rb)-1
if ( Rd±n) = even data : [Rb<<16+Rd±n+1]
←Hibyte(Rs),
[Rb<<16+Rd±n]
←Lobyte(Rs)
if ( Rd±n) = odd data : [Rb<<16+Rd±n]
←Hibyte(Rs),
[Rb<<16+Rd±n-1]
←Lobyte(Rs)
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rd. Rb is
decremented if a borrow occurs as the result of the subtraction performed on Rd.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the contents of the
base register (Rb) and the lower-order 16 bits are the result of the arithmetic operation＊1 performed on the
contents of Rd and n, is at an even address, the instruction transfers the contents of the lower-order 8 bits of
Rs to [Rb<<16+Rd±n] and the higher-order 8 bits of Rs to [Rb<<16+Rd±n+1].
In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits of Rs to
[Rb<<16+Rd±n] and the lower-order 8 bits of Rs to [Rb<<16+Rd±n-1].
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16
bits is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0002
R0, #0x5555
(R8, --R3, 0x50),
R3, #1
R1, #0x1200
(R8, --R3, 0x50),
R3, #1
R2, #0x0000
(R8, --R3, 0x50),
R3, #1
R0, #0x5634
(R8, --R3, 0x50),
R0
R1
R2
R0
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
66h
66h
66h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
3
0
0
3
1
1
3
2
2
3
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-165
Instructions
MOVF[.W] (Rb, Rd++, ±n), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 1 1][d3d2d1d0 1 s2s1s0][0 b2b1b0 n11 to n8][n7 to n0]
6708H
Rb = 3bit(Rb select), Rd = 4bit(R select), n = 12bit(signed), Rs = 3bit(R select)
2
3 or 4
if (Rd±n) = even data : [Rb<<16+Rd±n+1]
←Hibyte (Rs),
[Rb<<16+Rd±n]
←Lobyte(Rs)
if (Rd±n) =
odd data : [Rb<<16+Rd±n]
←Hibyte(Rs),
[Rb<<16+Rd±n-1]
←Lobyte(Rs)
(Rd)←(Rd)+2, if Carry : (Rb)←(Rb)+1
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of the general-purpose
register designated by the base register (Rb) and the lower-order 16 bits are the result of the arithmetic
operation＊1 performed on the contents of Rd and n, is at an even address, the instruction transfers the
contents of the lower-order 8 bits of Rs to [Rb<<16+Rd±n] and the higher-order 8 bits of Rs to
[Rb<<16+Rd±n+1].
In the case of an odd address, the instruction transfers the contents of the higher-order 8 bits of Rs to
[Rb<<16+Rd±n] and the lower-order 8 bits of Rs to [Rb<<16+Rd±n-1]. Subsequently, the instruction adds
2 to the contents of Rd. Rb is incremented if a carry occurs as the result of the addition performed on Rd.
The legitimate value range designated by Rd is from R0 to R15, that by Rb is from R8 to R13, that by Rs is
from R0 to R7, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits is
reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0000
R0, #0x5555
(R8, R3++, 0x50),
R3, #1
R1, #0x1200
(R8, R3++, 0x50),
R3, #1
R2, #0x0000
(R8, R3++, 0x50),
R3, #1
R0, #0x5634
(R8, R3++, 0x50),
R0
R1
R2
R0
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
66h
66h
66h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
3
0
0
3
1
1
3
2
2
3
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
<Note>
This instruction takes 4 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-166
0
0
0
0
0
0
0
0
0
0
0
0
0
LC88 Series Chapter 5
MOVF[.W] (Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
if (Rd) = even data : [R8<<16+Rd+1]
[R8<<16+Rd]
if (Rd) = odd data : [R8<<16+Rd]
[R8<<16+Rd-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7700H
←Hibyte(Rs),
←Lobyte(Rs),
←Hibyte(Rs),
←Lobyte(Rs)
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of the general-purpose register designated by Rd, is at an even address,
the instruction transfers the contents of the lower-order 8 bits of the general-purpose register Rs to
[R8<<16+Rd] and the contents of the higher-order 8 bits of Rs to [R8<<16+Rd+1]. In the case of an odd
address, the instruction transfers the contents of the higher-order 8 bits to [R8<<16+Rd] and the contents of
the lower-order 8 bits of Rs to [R8<<16+Rd-1].
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3), R0
R1, #0x1200
(R3), R1
R2, #0x0000
(R3), R2
R0, #0x5634
(R3), R0
R1, #0x8118
(R3), R1
R2, #0x5555
(R3), R2
RAM
(50h)
66h
66h
66h
55h
55h
00h
00h
00h
00h
34h
34h
34h
34h
34h
RAM
(51h)
66h
66h
66h
55h
55h
12h
12h
00h
00h
56h
56h
56h
56h
56h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5555h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
1200h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
N3 to
N0
3
0
0
1
1
2
2
0
0
1
1
2
2
Z8 Z16 P S
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-167
Instructions
MOVF[.W] (--Rd), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
(Rd)←(Rd)-2, if Borrow : (R8)←(R8)-1
if (Rd) =
even data : [R8<<16+Rd+1]
[R8<<16+Rd]
if (Rd) =
odd data : [R8<<16+Rd]
[R8<<16+Rd-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6F00H
←Hibyte(Rs),
←Lobyte(Rs)
←Hibyte(Rs),
←Lobyte(Rs)
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rd. R8 is
decremented if a borrow occurs as the result of the subtraction performed on Rd.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by designated by the 32-bit address, of which the higher-order 16 bits are the
contents of R8 (Rb0) and the lower-order 16 bits are the contents of the general-purpose register Rd, is at an
even address, the instruction transfers the contents of the lower-order 8 bits of the general-purpose register Rs
to [R8<<16+Rd] and the contents of the higher-order 8 bits of Rs to [R8<<16+Rd+1]. In the case of an odd
address, the instruction transfers the contents of the higher-order 8 bits to [R8<<16+Rd] and the contents of
the lower-order 8 bits of Rs to [R8<<16+Rd-1].
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0052
R0, #0x5555
(--R3), R0
R3, #1
R1, #0x1200
(--R3), R1
R3, #1
R2, #0x0000
(--R3), R2
R3, #1
R0, #0x5634
(--R3), R0
RAM
(50h)
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
RAM
(51h)
66h
66h
66h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
0052h
0052h
0050h
0052h
0052h
0050h
0052h
0052h
0050h
0052h
0052h
0050h
N3 to
N0
3
0
0
3
1
1
3
2
2
3
0
0
Z8 Z16 P S
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-168
LC88 Series Chapter 5
MOVF[.W] (Rd++), Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 1 1][d3d2d1d0 0 s2s1s0]
Rd = 4bit(R select), Rs = 3bit(R select)
1
2 or 3
if (Rd) = even data : [R8<<16+Rd+1]
[R8<<16+Rd]
if (Rd) =
odd data : [R8<<16+Rd]
[R8<<16+Rd-1]
(Rd)←(Rd)+2, if Carry : (R8)←(R8)+1
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6700H
←Hibyte(Rs),
←Lobyte(Rs)
←Hibyte(Rs),
←Lobyte(Rs)
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of the general-purpose register designated by Rd, is at an even address,
the instruction transfers the contents of the lower-order 8 bits of the general-purpose register Rs to
[R8<<16+Rd] and the contents of the higher-order 8 bits of Rs to [R8<<16+Rd+1]. In the case of an odd
address, the instruction transfers the contents of the higher-order 8 bits of Rs to [R8<<16+Rd] and the
contents of the lower-order 8 bits of Rs to [R8<<16+Rd-1]. Subsequently, the instruction adds 2 to the
contents of Rd. R8 is incremented if a carry occurs as the result of the addition performed on Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R7.
[Example]
MOV.W
MOV.W
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
0x50, #0x6666
R3, #0x0050
R0, #0x5555
(R3++), R0
R3, #1
R1, #0x1200
(R3++), R1
R3, #1
R2, #0x0000
(R3++), R2
R3, #1
R0, #0x5634
(R3++), R0
RAM
(50h)
66h
66h
66h
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
RAM
(51h)
66h
66h
66h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
0000h
0000h
0000h
0000h
0000h
0050h
0050h
0052h
0050h
0050h
0052h
0050h
0050h
0052h
0050h
0050h
0052h
N3 to
N0
3
0
0
3
1
1
3
2
2
3
0
0
Z8 Z16 P S
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
<Note>
In this case, Rb0 refers to R8.
This instruction takes 3 cycles to transfer the contents of Rs to program memory (ROM). However, no data
can actually be transferred to ROM.
5-169
Instructions
MOVF[.W] Rd, (Rb, Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 0 1][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0]
7508H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
if (Rs±n)=even data:
Hibyte(Rd)←[Rb<<16+Rs±n+1], Lobyte(Rd)←[Rb<<16+Rs±n]
if (Rs±n)=odd data:
Hibyte(Rd)←[Rb<<16+Rs±n], Lobyte(Rd)←[Rb<<16+Rs±n-1]
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of the general-purpose
register designated by the base register (Rb) and the lower-order 16 bits are the result of the arithmetic
operation＊1 performed on the contents of Rs and n, is at an even address, the instruction transfers the contents
to the lower-order 8-bit positions of the general-purpose register Rd and the contents of [Rb<<16+Rs±n+1]
to the higher-order 8-bit positions of Rd. In the case of an odd address, the instruction transfers the contents
of [Rb<<16+Rs±n] to the higher-order 8-bit positions of Rd and the contents of [Rb<<16+Rs±n-1] to the
lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
R3, #0x0000
0x50, #0x5555
R0, (R8, R3, 0x50)
0x50, #0x1200
R1, (R8, R3, 0x50)
0x50, #0x0000
R2, (R8, R3, 0x50)
0x50, #0x5634
R0, (R8, R3, 0x50)
0x50, #0x8118
R1, (R8, R3, 0x50)
0x50, #0x5555
R2, (R8, R3, 0x50)
55h
55h
00h
00h
00h
00h
34h
34h
18h
18h
55h
55h
55h
55h
12h
12h
00h
00h
56h
56h
81h
81h
55h
55h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
<Note>
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-170
3
3
0
0
1
1
2
2
0
0
1
1
2
1
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
LC88 Series Chapter 5
MOVF[.W] Rd, (Rb, --Rs, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 0 1][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0] 6D08H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
(Rs)←(Rs)-2, if Borrow : (Rb)←(Rb)-1
If (Rs±n) =even data:
Hibyte(Rd)←[Rb<<16+Rs±n+1], Lobyte(Rd)←[Rb<<16+Rs±n]
If (Rs±n) =odd data:
Hibyte(Rd)←[Rb<<16+Rs±n], Lobyte(Rd)←[Rb<<16+Rs±n-1]
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rs. Rb is
decremented if a borrow occurs as the result of the subtraction performed on Rs.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the contents of the
base register (Rb) and the lower-order 16 bits are the result of the arithmetic operation＊1 performed on the
contents of Rs and n, is at an even address, the instruction transfers the contents to the lower-order 8-bit
positions of the general-purpose register Rd and the contents of [Rb<<16+Rs±n+1] to the higher-order 8-bit
positions of Rd. In the case of an odd address, the instruction transfers the contents of [Rb<<16+Rs±n] to
the higher-order 8-bit positions of Rd and the contents of [Rb<<16+Rs±n-1] to the lower-order 8-bit
positions of Rd.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
R3, #0x0002
0x50, #0x5555
R0,(R8,--R3,0x50)
R3, #1
0x50, #0x1200
R1,(R8,--R3,0x50)
R3, #1
0x50, #0x0000
R2,(R8,--R3,0x50)
R3, #1
0x50, #0x5634
R0,(R8,--R3,0x50)
R3, #1
0x50, #0x8118
R1,(R8,--R3,0x50)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
18h
18h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
81h
81h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0002h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N3 to
Z8 Z16 P S
N0
<Note>
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-171
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Instructions
MOVF[.W] Rd, (Rb, Rs++, ±n)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 0 1][s3s2s1s0 1 d2d1d0][0 b2b1b0 n11 to n8][n7 to n0]
6508H
Rd = 3bit(R select), Rb = 3bit(Rb select), Rs = 4bit(R select), n = 12bit(signed)
2
3 or 4
if (Rs±n) =even data:
Hibyte(Rd)←[Rb<<16+Rs±n+1], Lobyte(Rd)←[Rb<<16+Rs±n]
if (Rs±n) =odd data:
Hibyte(Rd)←[Rb<<16+Rs±n], Lobyte(Rd)←[Rb<<16+Rs±n-1]
(Rs)←(Rs)+1, if Carry : (Rb)←(Rb)+1
(PC)←(PC)+4
Z8, Z16, P, S, N0 to N3
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of the general-purpose
register designated by the base register (Rb) and the lower-order 16 bits are the result of the arithmetic
operation＊1 performed on the contents of the general-purpose register Rs and n, is at an even address, the
instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and the
contents of [Rb<<16+Rs±n+1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the
instruction transfers the contents of [Rb<<16+Rs ± n] to the higher-order 8-bit positions of the
general-purpose register Rd and the contents of [Rb<<16+Rs±n-1] to the lower-order 8-bit positions of Rd.
Subsequently, the instruction adds 2 to the contents of Rs. Rb is incremented if a carry occurs as the result of
the addition performed on Rs.
The legitimate value range designated by Rd is from R0 to R7, that by Rb is from R8 to R13, that by Rs is
from R0 to R15, and that by n is that of signed 12-bit data (-2048 to 2047).
*1: Any carry or borrow resulting from the arithmetic operation performed on the lower-order 16 bits
is reflected in the higher-order 16 bits.
[Example]
RAM RAM
(50h) (51h)
MOV.W
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
R3, #0x0000
0x50, #0x5555
R0,(R8,R3++, 0x50)
R3, #1
0x50, #0x1200
R1,(R8,R3++, 0x50)
R3, #1
0x50, #0x0000
R2,(R8,R3++, 0x50)
R3, #1
0x50, #0x5634
R0,(R8,R3++, 0x50)
R3, #1
0x50, #0x8118
R1,(R8,R3++, 0x50)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
18h
18h
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
81h
81h
R0
R1
R2
R3
R8
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
<Note>
This instruction takes 4 cycles to transfer the contents of program memory (ROM) to Rd.
5-172
N3 to
Z8 Z16 P S
N0
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
LC88 Series Chapter 5
MOVF[.W] Rd, (Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 1 0 1 0 1][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
if (Rs) = even data :
Hibyte(Rd)←[R8<<16+Rs+1], Lobyte(Rd)←[R8<<16+Rs]
if (Rs) = odd data :
Hibyte(Rd)←[R8<<16+Rs], Lobyte(Rd)←[R8<<16+Rs-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
7500H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of the general-purpose register designated by Rs, is at an even address,
the instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and
the contents of [R8<<16+Rs+1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the
instruction transfers the contents of [R8<<16+Rs] to the higher-order 8-bit positions of Rd and the contents
of [R8<<16+Rs-1] to the lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
MOV.W
MOVF.W
R3, #0x0050
0x50, #0x5555
R0, (R3)
0x50, #0x1200
R1, (R3)
0x50, #0x0000
R2, (R3)
0x50, #0x5634
R0, (R3)
0x50, #0x8118
R1, (R3)
0x50, #0x5555
R2, (R3)
RAM
(50h)
55h
55h
12h
12h
00h
00h
56h
56h
81h
81h
55h
55h
RAM
(51h)
55h
55h
00h
00h
00h
00h
34h
34h
18h
18h
55h
55h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
0050h
N3 to
N0
3
3
0
0
1
1
2
2
0
0
1
1
2
<Note>
In this case, Rb0 refers to R8.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-173
Z8 Z16 P S
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Instructions
MOVF[.W] Rd, (--Rs)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 1 1 0 1][s3s2s1s0 0 d2d1d0]
6D00H
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
(Rs)←(Rs)-2, if Borrow : (R8)←(R8)-1
if (Rs) = even data :
Hibyte(Rd)←[R8<<16+Rs+1], Lobyte(Rd)←[R8<<16+Rs]
if (Rs) = odd data :
Hibyte(Rd)←[R8<<16+Rs], Lobyte(Rd)←[R8<<16+Rs-1]
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
[Description]
This instruction firstly subtracts 2 from the contents of the general-purpose register designated by Rs. R8 is
decremented if a borrow occurs as the result of the subtraction performed on Rs.
Subsequently, if the data memory (RAM) location, special function register (SFR), or program memory
(ROM) location designated by the 32-bit address, of which the higher-order 16 bits are the contents of R8
(Rb0) and the lower-order 16 bits are the contents of the general-purpose register Rs, is at an even address,
the instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and
the contents of [R8<<16+Rs+1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the
instruction transfers the contents of [R8<<16+Rs] to the higher-order 8-bit positions of Rd and the contents
of [R8<<16+Rs-1] to the lower-order 8-bit positions of Rd.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
INC
MOV.W
MOVF.W
R3, #0x0052
0x50, #0x5555
R0, (--R3)
R3, #1
0x50, #0x1200
R1, (--R3)
R3, #1
0x50, #0x0000
R2, (--R3)
R3, #1
0x50, #0x5634
R0, (--R3)
R3, #1
0x50, #0x8118
R1, (--R3)
RAM
(50h)
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
81h
81h
RAM
(51h)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
18h
18h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0052h
0052h
0050h
0052h
0052h
0050h
0052h
0052h
0050h
0052h
0052h
0050h
0052h
0052h
0050h
N3 to
N0
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
<Note>
In this case, Rb0 refers to R8.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-174
Z8 Z16 P S
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
LC88 Series Chapter 5
MOVF[.W] Rd, (Rs++)
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 1 0 0 1 0 1][s3s2s1s0 0 d2d1d0]
Rd = 3bit(R select), Rs = 4bit(R select)
1
2 or 3
if (Rs) = even data :
Hibyte(Rd)←[R8<<16+Rs+1], Lobyte(Rd)←[R8<<16+Rs]
if (Rs) = odd data :
Hibyte (Rd)←[R8<<16+Rs], Lobyte(Rd)←[R8<<16+Rs-1]
(Rs)←(Rs)+2, if Carry : (R8)←(R8)+1
(PC)←(PC)+2
Z8, Z16, P, S, N0 to N3
6500H
[Description]
If the data memory (RAM) location, special function register (SFR), or program memory (ROM) location
designated by the 32-bit address, of which the higher-order 16 bits are the contents of R8 (Rb0) and the
lower-order 16 bits are the contents of the general-purpose register designated by Rs, is at an even address,
the instruction transfers the contents to the lower-order 8-bit positions of the general-purpose register Rd and
the contents of [R8<<16+Rs+1] to the higher-order 8-bit positions of Rd. In the case of an odd address, the
instruction transfers the contents of [R8<<16+Rs] to the higher-order 8-bit positions of Rd and the contents
of [R8<<16+Rs-1] to the lower-order 8-bit positions of Rd.
Subsequently, the instruction adds 2 to the contents of the general-purpose register Rs. R8 is incremented if a
carry occurs as the result of the addition performed on Rs.
The legitimate value range designated by Rd is from R0 to R7 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
DEC
MOV.W
MOVF.W
R3, #0x0050
0x50, #0x5555
R0, (R3++)
R3, #1
0x50, #0x1200
R1, (R3++)
R3, #1
0x50, #0x0000
R2, (R3++)
R3, #1
0x50, #0x5634
R0, (R3++)
R3, #1
0x50, #0x8118
R1, (R3++)
RAM
(50h)
55h
55h
55h
12h
12h
12h
00h
00h
00h
56h
56h
56h
81h
81h
RAM
(51h)
55h
55h
55h
00h
00h
00h
00h
00h
00h
34h
34h
34h
18h
18h
R0
R1
R2
R3
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5634h
5634h
5634h
5634h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0050h
0050h
0052h
0050h
0050h
0052h
0050h
0050h
0052h
0050h
0050h
0052h
0050h
0050h
0052h
N3 to
N0
3
3
0
3
3
1
3
3
2
3
3
0
3
3
1
<Note>
In this case, Rb0 refers to R8.
The instruction takes 3 cycles to transfer the contents of program memory (ROM) to Rd.
5-175
Z8 Z16 P S
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Instructions
MUL
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][1 1 0 1 0 0 0 0]
00D0H
1
4 or 18 cycles
(R0)× (R2)=Result(32bit), R1= Result >>16, R0= Result &FFFFh,
(PC)←(PC) +2
Z8, Z16, P, S
CY, HC, OV, and N3-N0 all cleared.
[Description]
This instruction places the higher-order 16 bits of the result of multiplications performed on the contents of
the general-purpose registers R0 and R2 in R1 and the lower-order 16 bits of the result in R0.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
MUL
R0,#0X48D0
R1,#0X5678
R2,#0X4000
R3,#0XDEF0
R0
R1
R2
R3
PSW
48D0h
48D0h
48D0h
48D0h
0000h
5678h
5678h
5678h
1234h
4000h
4000h
4000h
DEF0h
DEF0h
0020h
1000h
2021h
3040h
0003h
<Note>
The flags (Z8, Z16, P, and S) are affected by R0 (lower-order 16-bit result).
Please refer to the datasheet of each product for the cycle count.
5-176
LC88 Series Chapter 5
NOP
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 0 0 0 0]
1
1
(PC)←(PC)+2
[Description]
This instruction consumes one system clock and does nothing.
5-177
0000H
Instructions
NOT Rd
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 0 1 1 d3d2d1d0]
Rd = 4bit(R select)
1
1
(Rd)← ~(Rd), (PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
30B0H
[Description]
This instruction inverts the contents of the general-purpose register designated by Rd.
The legitimate value range designated by Rd is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
NOT
NOT
NOT
NOT
R0,#0X5678
R1,#0X0000
R2,#0XFFFF
R3,#0X3456
R0
R1
R2
R3
R0
R1
R2
5678h
5678h
5678h
5678h
A987h
A987h
A987h
A987h
0000h
0000h
0000h
0000h
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
0000h
0000h
5-178
N3 to
N0
0
1
2
3456h
3
3456h
0
3456h
1
3456h
2
CBA9h
3
R3
Z8
Z16
P
S
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
LC88 Series Chapter 5
OR
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 0 1 0][s3s2s1s 0 d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) | (Rs), (PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
4200H
[Description]
This instruction takes the OR of the contents of the general-purpose registers designated by Rd and
designated by Rs and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
R0
MOV.W
MOV.W
MOV.W
MOV.W
OR
OR
OR
OR
R0,#0X5678
R1,#0X0000
R2,#0XFEDC
R3,#0X3456
R0,R1
R1,R2
R2,R3
R3,R0
R1
R2
R3
5678h
5678h 0000h
5678h 0000h FEDCh
5678h 0000h FEDCh 3456h
5678h 0000h FEDCh 3456h
5678h FEDCh FEDCh 3456h
5678h FEDCh FEDEh 3456h
5678h FEDCh FEDEh 767Eh
5-179
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
Instructions
OR
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 0 0 1 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select),imm16 = 16bit(immediate data)
2
2
(Rd)← (Rd) | #imm16, (PC)←(PC)+4
Z8,Z16,P,S,N0 to N3
3110H
[Description]
This instruction takes the OR of the contents of the general-purpose register designated by Rd and immediate
data designated by imm16 and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
OR
OR
OR
OR
R0,#0X5678
R1,#0X0000
R2,#0XFEDC
R3,#0X3456
R0,#0X3456
R1,#0X0066
R2,#0X0123
R3,#0X7F00
R0
R1
R2
R3
5678h
5678h
5678h
5678h
767Eh
767Eh
767Eh
767Eh
0000h
0000h
0000h
0000h
0066h
0066h
0066h
FEDCh
FEDCh
FEDCh
FEDCh
FFFFh
FFFFh
3456h
3456h
3456h
3456h
7F56h
5-180
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
LC88 Series Chapter 5
OR
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 0 1 1][i7i6i5i4i3i2i1i0]
4300H
imm8 = 8bit(immediate data)
1
1
(Rx)← (Rx) | 16bit data(Hibyte = 00H, Lobyte = #imm8), (PC)←(PC)+2
Z8,Z16,P,S
[Description]
This instruction takes the OR of the contents of the general-purpose register Rx designated indirectly by the
value of bits 12 to 15 (N0 to N3) of the PSW and the 16-bit data, of which the higher-order 8 bits are 00h and
the lower-order 8 bits are immediate data designated by imm8, and places the result in Rx.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
OR
INC
OR
SWPB
OR
DEC
OR
R3,#0X3456
R2,#0XFEDC
R1,#0X0000
R0,#0X5678
Rx,#0X78
R1
Rx,#0X66
R2
Rx,#0X01
R3
Rx,#0XAA
R0
R1
R2
R3
5678h
5678h
5678h
5678h
5678h
5678h
5678h
5678h
0000h
0000h
0000h
0001h
0067h
0067h
0067h
0067h
0067h
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
DCFEh
DCFFh
DCFFh
DCFFh
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3455h
34FFh
5-181
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8
Z16
P
S
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
1
1
0
0
Instructions
POP
PSW
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][1 0 0 1 1 1 1 0]
009EH
1
1
(SP)←(SP)-2
Hibyte(PSW)←[SP+1], Lobyte(PSW)← [SP], (PC)←(PC)+2
Affected flags
[Description]
This instruction decrements the stack pointer (SP) by 2 and transfers the contents of the data memory (RAM)
location designated by SP to the program status word (PSW).
[Example]
RAM RAM RAM RAM
(50h) (51h) (52h) (53h)
MOV.W R15,#0X0050
MOV.W R0,#0X5555
PUSH
R0
55h
55h
MOV.W R1,#0X0000
55h
55h
PUSH
R1
55h
55h 00h 00h
POP
PSW
55h
55h 00h 00h
POP
PSW
55h
55h 00h 00h
MOV.W R2,#0X1200
55h
55h 00h 00h
PUSH
R2
00h
12h 00h 00h
MOV.W R3,#0X3456
00h
12h 00h 00h
PUSH
R3
00h
12h 56h 34h
POP
PSW
00h
12h 56h 34h
POP
PSW
00h
12h 56h 34h
MOV.W R0,#0X8118
00h
12h 56h 34h
PUSH
R0
18h
81h 56h 34h
MOV.W R1,#0X5555
18h
81h 56h 34h
PUSH
R1
18h
81h 55h 55h
POP
PSW
18h
81h 55h 55h
POP
PSW
18h
81h 55h 55h
5-182
R0
R1
R2
R3
PSW
SP
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
8118h
8118h
8118h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
5555h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
F000h
0000h
0000h
1003h
1003h
0000h
5555h
2515h
2515h
3534h
3534h
3456h
1200h
0240h
0240h
1200h
1200h
1000h
1200h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
LC88 Series Chapter 5
POP Rs
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][1 0 0 1 s3s2s1s0]
Rs = 4bit(R select)
1
1
(SP)←(SP)-2,
Hibyte(Rs)←[SP+1], Lobyte(Rs)← [SP], (PC)←(PC)+2
0090H
Affected flags
[Description]
This instruction decrements the stack pointer (SP) by 2 and transfers the contents of the data memory (RAM)
location designated by SP to the general-purpose register designated by Rs.
The legitimate value range designated by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
PUSH
MOV.W
PUSH
POP
POP
MOV.W
PUSH
MOV.W
PUSH
POP
POP
MOV.W
PUSH
MOV.W
PUSH
POP
POP
R15,#0X0050
R0,#0X5555
R0
R1,#0X0000
R1
R2
R3
R3,#0X1200
R3
R2,#0X3456
R2
R1
R0
R0,#0X8118
R0
R1,#0X5555
R1
R2
R3
RAM
(50h)
55h
55h
55h
55h
55h
55h
00h
00h
00h
00h
00h
00h
18h
18h
18h
18h
18h
RAM
(51h)
55h
55h
55h
55h
55h
55h
12h
12h
12h
12h
12h
12h
81h
81h
81h
81h
81h
RAM RAM
R0
(52h) (53h)
5555h
5555h
5555h
00h
00h 5555h
00h
00h 5555h
00h
00h 5555h
00h
00h 5555h
00h
00h 5555h
00h
00h 5555h
56h
34h 5555h
56h
34h 5555h
56h
34h 1200h
56h
34h 8118h
56h
34h 8118h
56h
34h 8118h
55h
55h 8118h
55h
55h 8118h
55h
55h 8118h
5-183
R1
R2
R3
SP
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
3456h
3456h
3456h
3456h
5555h
5555h
5555h
5555h
0000h
0000h
0000h
0000h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5555h
5555h
5555h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
Instructions
PUSH PSW
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][1 0 0 0 1 1 1 0]
008EH
1
1
[SP+1]←Hibyte(PSW), [SP]←Lobyte(PSW),
(SP)←(SP)+2,(PC)←(PC)+2
Affected flags
[Description]
This instruction transfers the contents of the program status word (PSW) to the data memory (RAM) location
designated by the stack pointer (SP), then increments the SP by 2.
[Example]
RAM
(50h)
MOV.W R15,#0X0050
MOV.W R0,#0X5555
PUSH
PSW
00h
MOV.W R1,#0X0000
00h
PUSH
PSW
00h
POP
R0
00h
POP
R1
00h
MOV.W R2,#0X1200
00h
PUSH
PSW
01h
MOV.W R3,#0X3456
01h
PUSH
PSW
01h
POP
R2
01h
POP
R3
01h
MOV.W R0,#0X8118
01h
PUSH
PSW
40h
MOV.W R1,#0X5555
40h
PUSH
PSW
40h
POP
R0
40h
POP
R1
40h
RAM
(51h)
00h
00h
00h
00h
00h
00h
20h
20h
20h
20h
20h
20h
00h
00h
00h
00h
00h
RAM RAM
R0
(52h) (53h)
5555h
5555h
5555h
03h 10h 5555h
03h 10h 1003h
03h 10h 1003h
03h 10h 1003h
03h 10h 1003h
03h 10h 1003h
20h 30h 1003h
20h 30h 1003h
20h 30h 1003h
20h 30h 8118h
20h 30h 8118h
20h 30h 8118h
00h 10h 8118h
00h 10h 1000h
00h 10h 1000h
5-184
R1
R2
R3
PSW
SP
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5555h
5555h
5555h
0040h
1200h
1200h
1200h
1200h
3020h
3020h
3020h
3020h
3020h
3020h
3020h
3020h
3456h
3456h
3456h
2001h
2001h
2001h
2001h
2001h
2001h
2001h
F000h
0000h
0000h
1003h
1003h
1003h
1003h
2001h
2001h
3020h
3020h
3020h
3020h
0040h
0040h
1000h
1000h
1000h
1000h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
LC88 Series Chapter 5
PUSH Rs
Instruction code
Argument
Word count
Cycle count
Function
[0 0 0 0 0 0 0 0][1 0 0 0 s3s2s1s0]
Rs = 4bit(R select)
1
1
[SP+1]←Hibyte(Rs), [SP]←Lobyte(Rs),
(SP)←(SP)+2,(PC)←(PC)+2
0080H
Affected flags
[Description]
This instruction transfers the contents of the general-purpose register designated by Rs to the data memory
(RAM) location designated by the stack pointer (SP), then increments the SP by 2.
The legitimate value range designated by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
PUSH
MOV.W
PUSH
POP
POP
MOV.W
PUSH
MOV.W
PUSH
POP
POP
MOV.W
PUSH
MOV.W
PUSH
POP
POP
R15,#0X0050
R0,#0X5555
R0
R1,#0X0000
R1
R2
R3
R3,#0X1200
R3
R2,#0X3456
R2
R1
R0
R0,#0X8118
R0
R1,#0X5555
R1
R2
R3
RAM RAM RAM RAM
(50h) (51h) (52h) (53h)
55h
55h
55h
55h
55h
55h
00h
00h
55h
55h
00h
00h
55h
55h
00h
00h
55h
55h
00h
00h
00h
12h
00h
00h
00h
12h
00h
00h
00h
12h
56h
34h
00h
12h
56h
34h
00h
12h
56h
34h
00h
12h
56h
34h
18h
81h
56h
34h
18h
81h
56h
34h
18h
81h
55h
55h
18h
81h
55h
55h
18h
81h
55h
55h
5-185
R0
R1
R2
R3
SP
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
5555h
1200h
8118h
8118h
8118h
8118h
8118h
8118h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
3456h
3456h
3456h
3456h
5555h
5555h
5555h
5555h
0000h
0000h
0000h
0000h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5555h
5555h
5555h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
8118h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
0050h
0052h
0052h
0054h
0052h
0050h
Instructions
RESET
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 1 1 1 1]
1
1
Initialize
[Description]
The CPU is initialized as the result of executing the RESET instruction.
5-186
000FH
LC88 Series Chapter 5
RET
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][0 0 0 0 0 0 1 1]
0003H
1
3
(PC)←(SP-1<<24+SP-2<<16+SP-3<<8+SP-4), (SP)←(SP)-4
[Description]
This instruction decrements the stack pointer (SP) and places the contents of the data memory (RAM)
location designated by SP to the program counter (PC).
[Example] The value of label LA is 910AH.
RAM RAM RAM RAM
R3
(00h) (01h) (02h) (03h)
9004h
9008h
FFFFh
PC
MOV.W R15,#0X0000
MOV.W R3,#0XFFFF
PSW
SP
F003h
3040h
0000h
0000h
loop:
CALLF LA
INC
NOP
.
.
.
R3
INC
RET
R3
;; CALL LA
910A
h
900Eh
9010h
0Ch
90h
00h
00h
FFFFh
3040h
0004h
0Ch
0Ch
90h
90h
00h
00h
00h
00h
0001h
0001h
3020h
3020h
0000h
0000h
910Ch
900Ch
0Ch
0Ch
90h
90h
00h
00h
00h
00h
0000h
0000h
3003h
3003h
0004h
0000h
LA:
5-187
Instructions
REV
Rd
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 1 1 1 d3d2d1d0]
Rd = 4bit(R select)
1
1
(Rd)←mirror(Rd), (PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
30F0H
[Description]
This instruction swaps the contents (exchanges the MSB and LSB sides) of the general-purpose register
designated by Rd.
The legitimate value range designated by Rd is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
REV
REV
REV
REV
R0,#0XCDEF
R1,#0X0000
R2,#0X8888
R3,#0X5500
R0
R1
R2
R3
R0
R1
R2
CDEFh
CDEFh
CDEFh
CDEFh
F7B3h
F7B3h
F7B3h
F7B3h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8888h
8888h
8888h
8888h
1111h
1111h
5-188
N3 to
N0
0
1
2
5500h
3
5500h
0
5500h
1
5500h
2
00AAh
3
R3
Z8
Z16
P
S
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
LC88 Series Chapter 5
RLC
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 0 1 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) rotate left #imm4 bit through carry
(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3B00H
[Description]
This instruction rotates the contents of the general-purpose register Rd through the carry flag (CY) (17-bit
space) to the left by the amount (rotate amount) designated by immediate data imm4.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
RLC
RLC
RLC
RLC
R0,#0XBA98
R1,#0XF123
R2,#0X0000
R3,#0X8761
R14,#2
R0,#0X03
R1,#0X00
R2,#0X01
R3,#0X02
R0
R1
R2
R3
BA98h
BA98h
BA98h
BA98h
BA98h
D4C2h
D4C2h
D4C2h
D4C2h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
0000h
0000h
0000h
0000h
0000h
0001h
0001h
8761h
8761h
8761h
8761h
8761h
1D85h
5-189
N3 to
Z8
N0
0
0
1
0
2
1
3
0
E
0
0
0
1
0
2
0
3
0
Z16
CY
P
S
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
1
0
0
Instructions
RLC
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 0 1 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) rotate left (Rs)&000Fh bit through carry
(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3A00H
[Description]
This instruction rotates the contents of the general-purpose register Rd through the carry flag (CY) (17-bit
space) to the left by the amount (rotate amount) of the lower-order 4 bits of the general-purpose register
designated by Rs.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
RLC
RLC
RLC
RLC
R0,#0XBA98
R1,#0XF123
R2,#0X0000
R3,#0X8761
R14,#2
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
R3
BA98h
BA98h
BA98h
BA98h
BA98h
D4C2h
D4C2h
D4C2h
D4C2h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
0000h
0000h
0000h
0000h
0000h
0001h
0001h
8761h
8761h
8761h
8761h
8761h
1D85h
5-190
N3 to
Z8
N0
0
0
1
0
2
1
3
0
E
0
0
0
1
0
2
0
3
0
Z16
CY
P
S
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
1
0
0
LC88 Series Chapter 5
RRC
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 0 0 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) rotate right #imm4 bit through carry
(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3900H
[Description]
This instruction rotates the contents of the general-purpose register Rd through the carry flag (CY) (17-bit
space) to the right by the amount (rotate amount) designated by immediate data imm4.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
RRC
RRC
RRC
RRC
R0,#0X1234
R1,#0XF123
R2,#0X0000
R3,#0X8761
R14,#2
R0,#0X03
R1,#0X00
R2,#0X01
R3,#0X06
R0
R1
R2
1234h
1234h
1234h
1234h
1234h
0246h
0246h
0246h
0246h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
0000h
0000h
0000h
0000h
0000h
8000h
8000h
5-191
N3 to
N0
0
1
2
8761h
3
8761h
E
8761h
0
8761h
1
8761h
2
0A1Dh
3
R3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
Instructions
RRC
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 0 0 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) rotate right (Rs)&000Fh bit through carry
(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3800H
[Description]
This instruction rotates the contents of the general-purpose register Rd through the carry flag (CY) (17-bit
space) to the right by the amount (rotate amount) of the lower-order 4 bits of the general-purpose register
designated by Rs.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
RRC
RRC
RRC
RRC
R0,#0X1234
R1,#0XF123
R2,#0X0000
R3,#0X8761
R14,#2
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
1234h
1234h
1234h
1234h
1234h
0246h
0246h
0246h
0246h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
F123h
0000h
0000h
0000h
0000h
0000h
8000h
8000h
5-192
N3 to
N0
0
1
2
8761h
3
8761h
E
8761h
0
8761h
1
8761h
2
0A1Dh
3
R3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
LC88 Series Chapter 5
SBC
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 0 1 1 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) - #imm4 – CY, (PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S,N0 to N3
5700H
[Description]
This instruction subtracts immediate data designated by imm4 and the value of the carry flag (CY) from the
contents of the general-purpose register designated by Rd and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SBC
SBC
SBC
SBC
R0,#0X0034
R1,#0X0001
R2,#0XBA98
R3,#0X3456
R0,#0X4
R1,#0XF
R2,#0X8
R3,#0X1
R0
R1
R2
R3
0034h
0034h
0034h
0034h
0030h
0030h
0030h
0030h
0001h
0001h
0001h
0001h
FFF2h
FFF2h
FFF2h
BA98h
BA98h
BA98h
BA98h
BA8Fh
BA8Fh
3456h
3456h
3456h
3456h
3455h
5-193
N3 to
Z8 Z16 CY HC OV
N0
0
0
0
1
0
0
2
0
0
3
0
0
0
0
0
0
0
0
1
0
0
1
1
0
2
0
0
0
1
0
3
0
0
0
0
0
P
S
1
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
Instructions
SBC
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 1 1 1 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select),imm16 = 16bit(immediate data)
2
2
(Rd)←(Rd) - #imm16 – CY, (PC)←(PC)+4
Z8,Z16,CY,HC,OV,P,S,N0 to N3
3170H
[Description]
This instruction subtracts immediate data designated by imm16 and the value of the carry flag (CY) from the
contents of the general-purpose register designated by Rd and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 is from 0 to FFFF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SBC
SBC
SBC
SBC
R0,#0X1234
R1,#0X0001
R2,#0XBA98
R3,#0X8765
R0,#0X1234
R1,#0XFFFF
R2,#0X9898
R3,#0X5678
R0
R1
R2
R3
1234h
1234h
1234h
1234h
0000h
0000h
0000h
0000h
0001h
0001h
0001h
0001h
0002h
0002h
0002h
BA98h
BA98h
BA98h
BA98h
21FFh
21FFh
8765h
8765h
8765h
8765h
30EDh
5-194
N3 to
Z8 Z16 CY HC OV
N0
0
0
0
1
0
0
2
0
0
3
0
0
0
1
1
0
0
0
1
0
0
1
1
0
2
0
0
0
1
0
3
0
0
0
1
1
P
S
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
LC88 Series Chapter 5
SBC
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 1 1 1 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx)←(Rx) - #imm8 - CY,(PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S
5F00H
[Description]
This instruction subtracts immediate data designated by imm8 and the value of the carry flag (CY) from the
contents of the general-purpose register Rx designated indirectly by bits 12 to 15 (N0 to N3) of the PSW and
places the result in Rx.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SBC
INC
SBC
NOT
SBC
SWPB
SBC
R3,#0X3456
R2,#0XFFFF
R1,#0X7654
R0,#0X8000
Rx,#0XF6
R1
Rx,#0X99
R2
Rx,#0X01
R3
Rx,#0X55
R0
R1
R2
R3
8000h
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7654h
7654h
7654h
7655h
75BCh
75BCh
75BCh
75BCh
75BCh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
0000h
FFFFh
FFFFh
FFFFh
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5634h
55DEh
5-195
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8 Z16 CY HC OV
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
P
S
1
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
0
Instructions
SBC
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 1 1 1 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) - (Rs) – CY, (PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S,N0 to N3
4F00H
[Description]
This instruction subtracts the contents of the general-purpose register designated by Rs and the value of the
carry flag (CY) from the contents of the general-purpose register designated by Rd and places the result in
Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SBC
SBC
SBC
SBC
SBC
SBC
R0,#0X1234
R1,#0X1234
R2,#0X89AB
R3,#0X3456
R0,R1
R1,R2
R2,R3
R3,R0
R3,R2
R3,R2
R0
R1
R2
1234h
1234h
1234h
1234h
0000h
0000h
0000h
0000h
0000h
0000h
1234h
1234h
1234h
1234h
8889h
8889h
8889h
8889h
8889h
89ABh
89ABh
89ABh
89ABh
5554h
5554h
5554h
5554h
5-196
N3 to
Z8 Z16 CY HC OV
N0
0
0
0
1
0
0
2
0
0
3456h
3
0
0
3456h
0
1
1
0
0
0
3456h
1
0
0
1
1
1
3456h
2
0
0
0
0
1
3456h
3
0
0
0
0
0
DF02h
3
0
0
1
0
0
89ADh
3
0
0
0
1
0
R3
P
S
1
1
0
1
0
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
LC88 Series Chapter 5
SDIV
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][1 1 0 0 1 0 0 0]
00C8H
1
18 to 19 cycles
(R0 : quotient)…(R1 : remainder)←(R0)÷(R2)(signed division), (PC)←(PC)+2
Z8,Z16,P,S,CY(equal to S)
HC, OV, and N3 to N0 all cleared.
[Description]
This instruction places the result of dividing the contents (signed 16-bit data) of the general-purpose register
R0 by the contents (signed 16-bit data) of the general-purpose register R2 in R0 and the remainder of the
division in R1.
No valid result is guaranteed if the value of R2 is 0.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SDIV
MOV.W
MOV.W
SDIV
MOV.W
SDIV
R0,#0X89AB
R1,#0X5678
R2,#0X1234
R3,#0XDEF0
R0,#0X8000
R2,#0X0002
R0,#0XFFFF
<Note>
The cycle count of this instruction is variable.
The sign of the remainder is identical to that of the dividend.
The flags (Z8, Z16, P, and S) are affected by R0 (quotient).
5-197
R0
R1
R2
R3
PSW
89ABh
89ABh
89ABh
89ABh
FFFAh
8000h
8000h
C000h
FFFFh
0000h
5678h
5678h
5678h
E6E3h
E6E3h
E6E3h
0000h
0000h
FFFFh
1234h
1234h
1234h
1234h
0002h
0002h
0002h
0002h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
0040h
1000h
2020h
3040h
0044h
0065h
2024h
0045h
0044h
0003h
Instructions
SDIVLH
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 0 0 0 0][1 1 1 0 1 0 0 0]
00E8H
1
18 to 19 cycles
(R0 : quotient)…(R1 : remainder)←(R1<<16+R0)÷(R2)(signed division),
(PC)←(PC)+2
Z8,Z16,P,S,CY(equal to S)
HC, OV, and N3 to N0 all cleared.
[Description]
This instruction places the result of dividing signed 32-bit data (R1<<16+R0) by R2 (signed 16-bit data) in
R0 and the remainder of the division in R1.
No valid result is guaranteed if the value of R2 is 0 or the quotient (R0) exceeds the value range of 8000h
(-32768) to 7FFFh (32767).
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SDIVLH
MOV.W
MOV.W
MOV.W
SDIVLH
MOV.W
MOV.W
MOV.W
SDIVLH
R0,#0X0A9F
R1,#0X3AB0
R2,#0X8001
R3,#0XDEF0
R0,#0X0AA0
R1,#0X3AB0
R2,#0X8001
R0,#0XF560
R1,#0XC54F
R2,#0X7FFF
<Note>
The cycle count of this instruction is variable.
The sign of the remainder is identical to that of the dividend.
The flags (Z8, Z16, P, and S) are affected by R0 (quotient).
5-198
R0
R1
R2
R3
PSW
0A9Fh
0A9Fh
0A9Fh
0A9Fh
8A9Fh
0AA0h
0AA0h
0AA0h
8A9Fh
F560h
F560h
F560h
8A9Fh
3AB0h
3AB0h
3AB0h
0000h
0777h
3AB0h
3AB0h
0001h
0001h
C54Fh
C54Fh
FFFFh
8001h
8001h
8001h
8001h
8001h
8001h
8001h
8001h
8001h
7FFFh
7FFFh
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
DEF0h
0000h
1020h
2040h
3040h
0064h
0004h
1024h
2044h
0064h
0044h
1064h
2024h
0064h
LC88 Series Chapter 5
SET1
m16, #imm3
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[1 1 1 X i2i1i0 1][m7m6m5m4m3m2m1m0]
E100H(RAM),F100H(SFR)
m16 = 16bit(Lower 8bit valid for operation code),imm3 = 3bit(bit select)
1
2
(m16)←(m16) of bit #imm3 ←1,(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
[Description]
This instruction sets the bit, in the 2-byte RAM (data memory) location or SFR (one of the registers dedicated
to control the internal peripheral devices) addressed by m16, that is designated by immediate data designated
by imm3, to 1.
The legitimate value range designated by imm3 is from 0 to 8.
The compiler generates the instruction code while regarding RAM or SFR as the destination of transfer
according to the value of m16 (first operand data).
・ When specifying a RAM location, specify m16 with a value from 00H to FFH (0000H to 00FFH). It is
disallowed to specify a RAM address not lower than 100H.
・ When specifying a SFR, specify m16 with a value from 7F00H to 7FFFH.
The basic types of generated instruction code are E100H (RAM) and F100H (SFR), respectively, The
lower-order 8 bits of m16 are reflected in the behavior of the instruction code.
[Example]
MOV.B
MOV.B
MOV.B
MOV.B
SET1
SET1
SET1
SET1
0X50,#0XFF
0X51,#0X32
0X52,#0X00
0X53,#0X54
0X50,#0X02
0X51,#0X00
0X52,#0X04
0X53,#0X07
RAM RAM RAM RAM
(50h) (51h) (52h) (53h)
FFh
FFh
32h
FFh
32h
00h
FFh
32h
00h
54h
FFh
32h
00h
54h
FFh
33h
00h
54h
FFh
33h
10h
54h
FFh
33h
10h
D4h
5-199
Z8
Z16
P
S
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
0
1
Instructions
SET1
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 0 0 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(bit select)
1
1
(Rd)←(Rd) of bit #imm4←1,(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
0900H
[Description]
This instruction sets the bit of the general-purpose register designated by Rd that is designated by immediate
data designated by imm4 to 1.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SET1
SET1
SET1
SET1
R0,#0X7FFF
R1,#0X5432
R2,#0X0000
R3,#0X7654
R0,#0X02
R1,#0X00
R2,#0X04
R3,#0X0F
R0
R1
R2
R3
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
5432h
5432h
5432h
5432h
5433h
5433h
5433h
0000h
0000h
0000h
0000h
0010h
0010h
7654h
7654h
7654h
7654h
F654h
5-200
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
LC88 Series Chapter 5
SET1
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 0 0 1 0 1 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(bit select)
1
1
(Rd)←(Rd) of bit (Rs)&000Fh ←1,(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
0B00H
[Description]
This instruction sets the bit, in the general-purpose register designated by Rd, that is designated by the
lower-order 4 bits of the general-purpose register designated by Rs, to 1.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SET1
SET1
SET1
SET1
R0,#0X7FFF
R1,#0X5432
R2,#0X0000
R3,#0X7654
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
R3
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
7FFFh
5432h
5432h
5432h
5432h
5433h
5433h
5433h
0000h
0000h
0000h
0000h
0010h
0010h
7654h
7654h
7654h
7654h
F654h
5-201
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
Instructions
SHL
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 1 1 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) logical shift left #imm4 bit
(CY)←last shift bit, (PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3F00H
[Description]
This instruction shifts the contents of the general-purpose register designated by Rd to the left by the amount
(shift amount) of immediate data designated by imm4. Finally, the instruction places the overflow bit out of
the MSB in the carry flag (CY).
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
SHL
SHL
SHL
SHL
R0,#0XCDEF
R1,#0X5432
R2,#0X0000
R3,#0X8761
R14,#2
R0,#0X02
R1,#0X00
R2,#0X01
R3,#0X0C
R0
R1
R2
R3
CDEFh
CDEFh
CDEFh
CDEFh
CDEFh
37BCh
37BCh
37BCh
37BCh
5432h
5432h
5432h
5432h
5432h
5432h
5432h
5432h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8761h
8761h
8761h
8761h
8761h
1000h
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
<Note>
The contents of Rd are shifted to the left and are padded with 0s from the LSB side.
5-202
LC88 Series Chapter 5
SHL
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 1 1 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) logical shift left (Rs)&000Fh bit
(CY)←last shift bit,(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3E00H
[Description]
This instruction shifts the contents of the general-purpose register designated by Rd to the left by the amount
(shift amount) of the lower-order 4 bits of the general-purpose register designated by Rs. Finally, the
instruction places the overflow bit out of the MSB in the carry flag (CY).
The legitimate value range designated by Rd is from R0 to R15 and that of Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
SHL
SHL
SHL
SHL
R0,#0XCDEF
R1,#0X5432
R2,#0X0000
R3,#0X8761
R14,#2
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
R3
CDEFh
CDEFh
CDEFh
CDEFh
CDEFh
37BCh
37BCh
37BCh
37BCh
5432h
5432h
5432h
5432h
5432h
5432h
5432h
5432h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8761h
8761h
8761h
8761h
8761h
1000h
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
<Note>
The contents of Rd are shifted to the left and are padded with 0s from the LSB side.
5-203
Instructions
SHR
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 1 0 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) logical shift right #imm4 bit
(CY)←last shift bit,(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3D00H
[Description]
This instruction shifts the contents of the general-purpose register designated by Rd to the right by the
amount (shift amount) of immediate data designated by imm4. Finally, the instruction places the overflow bit
out of the LSB in the carry flag (CY).
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
SHR
SHR
SHR
SHR
R0,#0XFEDC
R1,#0X9BDF
R2,#0X0000
R3,#0X8761
R14,#2
R0,#0X0F
R1,#0X00
R2,#0X01
R3,#0X01
R0
R1
R2
R3
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
0001h
0001h
0001h
0001h
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8761h
8761h
8761h
8761h
8761h
43B0h
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
0
<Note>
The contents of Rd are shifted to the right and are padded with 0s from the MSB side.
5-204
LC88 Series Chapter 5
SHR
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 1 1 0 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) logical shift right (Rs)&000Fh bit
(CY)←last shift bit,(PC)←(PC)+2
Z8,Z16,CY,P,S,N0 to N3
3C00H
[Description]
This instruction shifts the contents of the general-purpose register designated by Rd to the right by the
amount (shift amount) of the lower-order 4 bits of the general-purpose register designated by Rs. Finally, the
instruction places the overflow bit out of the LSB in the carry flag (CY).
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
CLR1
SHR
SHR
SHR
SHR
R0,#0XFEDC
R1,#0X9BDF
R2,#0X0000
R3,#0X8761
R14,#2
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
R3
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
0001h
0001h
0001h
0001h
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
9BDFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8761h
8761h
8761h
8761h
8761h
43B0h
N3 to
N0
0
1
2
3
E
0
1
2
3
Z8
Z16
CY
P
S
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
0
<Note>
The contents of Rd are shifted to the right and are padded with 0s from the MSB side.
5-205
Instructions
SUB
Rd, #imm4
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 0 1 0 1][i3i2i1i0d3d2d1d0]
Rd = 4bit(R select),imm4 = 4bit(immediate data)
1
1
(Rd)←(Rd) - #imm4,(PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S,N0 to N3
5500H
[Description]
This instruction subtracts immediate data designated by imm4 from the contents of the general-purpose
register designated by Rd and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm4 is from 0 to F.
[Example]
R0
MOV.W R0,#0X0034 0034h
MOV.W R1,#0X0001 0034h
MOV.W R2,#0XBA98 0034h
MOV.W R3,#0X3456 0034h
SUB
R0,#0X4
0030h
SUB
R1,#0XF
0030h
SUB
R2,#0X8
0030h
SUB
R3,#0X1
0030h
R1
R2
R3
0001h
0001h
0001h
0001h
FFF2h
FFF2h
FFF2h
BA98h
BA98h
BA98h
BA98h
BA90h
BA90h
3456h
3456h
3456h
3456h
3455h
5-206
N3 to
Z8 Z16 CY
N0
0
0
0
1
0
0
2
0
0
3
0
0
0
0
0
0
1
0
0
1
2
0
0
0
3
0
0
0
HC OV
0
1
0
0
0
0
0
0
P
S
1
1
0
1
0
1
1
1
0
0
1
0
0
1
1
0
LC88 Series Chapter 5
SUB
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 1 1 0 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select),imm16 = 16bit(immediate data)
2
2
(Rd)←(Rd) - #imm16,(PC)←(PC)+4
Z8,Z16,CY,HC,OV,P,S,N0 to N3
3160H
[Description]
This instruction subtracts immediate data designated by imm16 from the contents of the general-purpose
register designated by Rd and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 is from 0 to FFFF.
[Example]
MOV.W R0,#0X1234
MOV.W R1,#0X0001
MOV.W R2,#0XBA98
MOV.W R3,#0X8765
SUB
R0,#0X1234
SUB
R1,#0XFFFF
SUB
R2,#0X9898
SUB
R3,#0X5678
R0
R1
R2
R3
1234h
1234h
1234h
1234h
0000h
0000h
0000h
0000h
0001h
0001h
0001h
0001h
0002h
0002h
0002h
BA98h
BA98h
BA98h
BA98h
2200h
2200h
8765h
8765h
8765h
8765h
30EDh
5-207
N3 to
Z8 Z16 CY
N0
0
0
0
1
0
0
2
0
0
3
0
0
0
1
1
0
1
0
0
1
2
1
0
0
3
0
0
0
HC OV
0
1
0
1
0
0
0
1
P
S
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
Instructions
SUB
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 1 1 1 0 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx)←(Rx) - #imm8,(PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S
5D00H
[Description]
This instruction subtracts immediate data designated by imm8 from the contents of the general-purpose
register Rx designated indirectly by the value of bits 12 to 15 (N0 to N3) of the PSW and places the result in
Rx.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SUB
INC
SUB
NOT
SUB
SWPB
SUB
R3,#0X3456
R2,#0XFFFF
R1,#0X7654
R0,#0X8000
Rx,#0XF6
R1
Rx,#0X99
R2
Rx,#0X01
R3
Rx,#0X55
R0
R1
R2
R3
8000h
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7F0Ah
7654h
7654h
7654h
7655h
75BCh
75BCh
75BCh
75BCh
75BCh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
0000h
FFFFh
FFFFh
FFFFh
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5634h
55DFh
5-208
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8
0
0
0
1
0
0
0
1
0
0
0
Z16 CY HC OV
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
P
S
1
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
1
0
0
LC88 Series Chapter 5
SUB
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 1 1 0 1][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)← (Rd) - (Rs),(PC)←(PC)+2
Z8,Z16,CY,HC,OV,P,S,N0 to N3
4D00H
[Description]
This instruction subtracts the contents of the general-purpose register designated by Rs from the contents of
the general-purpose register designated by Rd and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SUB
SUB
SUB
SUB
SUB
SUB
R0,#0X1234
R1,#0X1234
R2,#0X89AB
R3,#0X3456
R0,R1
R1,R2
R2,R3
R3,R0
R3,R2
R3,R2
R0
R1
R2
R3
1234h
1234h
1234h
1234h
0000h
0000h
0000h
0000h
0000h
0000h
1234h
1234h
1234h
1234h
8889h
8889h
8889h
8889h
8889h
89ABh
89ABh
89ABh
89ABh
5555h
5555h
5555h
5555h
3456h
3456h
3456h
3456h
3456h
DF01h
89ACh
5-209
N3 to
N0
0
1
2
3
0
1
2
3
3
3
Z8
0
0
0
0
1
0
0
0
0
0
Z16 CY HC OV
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
P
S
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
1
Instructions
SWPB
Rd
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 0 0 0 d3d2d1d0]
Rd = 4bit(R select)
1
1
Hibyte(Rd) ⇔ Lobyte(Rd)
(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
3080H
[Description]
This instruction swaps the higher-order 8 bits of the general-purpose register designated by Rd with its
lower-order 8 bits.
The legitimate value range designated by Rd is from R0 to R15.
[Example]
MOV.W
SWPB
MOV.W
SWPB
MOV.W
SWPB
MOV.W
SWPB
MOV.W
SWPB
MOV.W
SWPB
R0,#0X5678
R0
R1,#0X0000
R1
R2,#0X1200
R2
R3,#0X3456
R3
R0,#0X8118
R0
R1,#0X5678
R1
R0
R1
R2
R3
5678h
7856h
7856h
7856h
7856h
7856h
7856h
7856h
8118h
1881h
1881h
1881h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5678h
7856h
1200h
0012h
0012h
0012h
0012h
0012h
0012h
0012h
3456h
5634h
5634h
5634h
5634h
5634h
5-210
N3 to
N0
0
0
1
1
2
2
3
3
0
0
1
1
Z8
Z16
P
S
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
LC88 Series Chapter 5
SWPN
Rd
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 0][1 0 0 1 d3d2d1d0]
3090H
Rd = 4bit(R select)
1
1
Hibyte(Rd)←Hibyte(Rd), Lobyte(Rd)←(Rd)&000Fh<<4+(Rd)&00F0h>>4
(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
[Description]
This instruction swaps between the higher- and lower-order 4 bits of the lower-order 8 bits of the
general-purpose register designated by Rd.
The legitimate value range designated by Rd is from R0 to R15.
[Example]
MOV.W
SWPN
MOV.W
SWPN
MOV.W
SWPN
MOV.W
SWPN
MOV.W
SWPN
MOV.W
SWPN
R0,#0X5678
R0
R1,#0X0000
R1
R2,#0X1200
R2
R3,#0X3456
R3
R0,#0X8118
R0
R1,#0X5678
R1
R0
R1
R2
R3
5678h
5687h
5687h
5687h
5687h
5687h
5687h
5687h
8118h
8181h
8181h
8181h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
5678h
5687h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
1200h
3456h
3465h
3465h
3465h
3465h
3465h
<Note>
The value of the higher-order 8 bits of Rd remains unchanged.
5-211
N3 to
N0
0
0
1
1
2
2
3
3
0
0
1
1
Z8
Z16
P
S
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Instructions
SWPW
Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 1 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
2
(Rd)⇔(Rs) exchange,(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
3200H
[Description]
This instruction swaps the contents of the general-purpose register designated by Rd with the contents of the
general-purpose register designated by Rs.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
SWPW
SWPW
SWPW
MOV.W
MOV.W
SWPW
SWPW
R0,#0X5678
R1,#0X0000
R2,#0X1200
R3,#0X3456
R0,R1
R1,R2
R2,R3
R0,#0X8118
R1,#0X5678
R3,R0
R0,R1
R0
R1
R2
R3
5678h
5678h
5678h
5678h
0000h
0000h
0000h
8118h
8118h
5678h
5678h
0000h
0000h
0000h
5678h
1200h
1200h
1200h
5678h
5678h
5678h
1200h
1200h
1200h
5678h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
5678h
5678h
5678h
8118h
8118h
5-212
N3 to
N0
0
1
2
3
0
1
2
0
1
3
0
Z8
Z16
P
S
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
LC88 Series Chapter 5
XOR Rd, Rs
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 1 0 0][s3s2s1s0d3d2d1d0]
Rd = 4bit(R select),Rs = 4bit(R select)
1
1
(Rd)←(Rd) ^ (Rs),(PC)←(PC)+2
Z8,Z16,P,S,N0 to N3
4400H
[Description]
This instruction takes the exclusive OR of the contents of the general-purpose register designated by Rd and
the contents of the general-purpose register designated by Rs and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by Rs is from R0 to R15.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
XOR
XOR
XOR
XOR
R0,#0X5678
R1,#0X0000
R2,#0XFEDC
R3,#0X3456
R0,R1
R1,R2
R2,R3
R3,R0
R0
R1
R2
R3
5678h
5678h
5678h
5678h
5678h
5678h
5678h
5678h
0000h
0000h
0000h
0000h
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
CA8Ah
CA8Ah
3456h
3456h
3456h
3456h
622Eh
5-213
N3 to
N0
0
1
2
3
0
1
2
3
Z8
Z16
P
S
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
Instructions
XOR
Rd, #imm16
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 0 1 1 0 0 0 1][0 0 1 0 d3d2d1d0][i15 to i8][i7 to i0]
Rd = 4bit(R select),imm16 = 16bit(immediate data)
2
2
(Rd)←(Rd) ^ #imm16,(PC)←(PC)+4
Z8,Z16,P,S,N0 to N3
3120H
[Description]
This instruction takes the exclusive OR of the contents of the general-purpose register designated by Rd and
immediate data designated by imm16 and places the result in Rd.
The legitimate value range designated by Rd is from R0 to R15 and that by imm16 is from 0 to FFFF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
XOR
XOR
XOR
XOR
R0,#0X5678
R1,#0X0000
R2,#0XFEDC
R3,#0X3456
R0,#0X0078
R1,#0X0000
R2,#0X0012
R3,#0XFFFF
R0
R1
R2
5678h
5678h
5678h
5678h
5600h
5600h
5600h
5600h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
FEDCh
FEDCh
FEDCh
FEDCh
FECEh
FECEh
5-214
N3 to
N0
0
1
2
3456h
3
3456h
0
3456h
1
3456h
2
CBA9h
3
R3
Z8
Z16
P
S
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
LC88 Series Chapter 5
XOR
Rx, #imm8
Instruction code
Argument
Word count
Cycle count
Function
Affected flags
[0 1 0 0 0 1 0 1][i7i6i5i4i3i2i1i0]
imm8 = 8bit(immediate data)
1
1
(Rx)← (Rx) ^ 16bit data(Hibyte=00H, Lobyte=#imm8),(PC)←(PC)+2
Z8,Z16,P,S
4500H
[Description]
This instruction takes the exclusive OR of the contents of the general-purpose register Rx designated
indirectly by the value of bits 12 to 15 (N0 to N3) of the PSW and the 16-bit data of which the higher-order 8
bits are 00h and the lower-order 8 bits are immediate data designated by imm8 and places the result in Rx.
The legitimate value range designated by imm8 is from 0 to FF.
[Example]
MOV.W
MOV.W
MOV.W
MOV.W
XOR
DEC
XOR
SWPB
XOR
DEC
XOR
R3,#0X3456
R2,#0XFEDC
R1,#0X0001
R0,#0X5678
Rx,#0X78
R1
Rx,#0X00
R2
Rx,#0X01
R3
Rx,#0XFF
R0
R1
R2
R3
5678h
5600h
5600h
5600h
5600h
5600h
5600h
5600h
0001h
0001h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
FEDCh
DCFEh
DCFFh
DCFFh
DCFFh
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3456h
3455h
34AAh
5-215
N3 to
N0
3
2
1
0
0
1
1
2
2
3
3
Z8
Z16
P
S
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
1
1
0
0
Instructions
5-216
Important Note
This document is designed to provide the reader with accurate information in easily
understandable form regarding the device features and the correct device implementation
procedures.
The sample configurations included in the various descriptions are intended for reference
only and should not be directly incorporated in user product configurations.
ON Semiconductor shall bear no responsibility for obligations concerning patent
infringements, safety or other legal disputes arising from prototypes or actual products
created using the information contained herein.
LC88 SERIES CHAPTER 5 INSTRUCTIONS
USER’S MANUAL
Rev. 0
December 18, 2015
Microcontroller Business Unit
ON Semiconductor