E2E1031-27-Y4 Pr el im This version: Jan. 1998 MSM66589/66P589/66Q589 ina ry Previous version: Nov. 1996 ¡ Semiconductor MSM66589/66P589/66Q589 ¡ Semiconductor OLMS-66K Series CMOS 16-Bit Microcontroller GENERAL DESCRIPTION The MSM66589/66P589/66Q589 is a high-speed, high-performance 16-bit microcontroller that employs OKI original nX-8/500S CPU core. The MSM66589/66P589/66Q589 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, pulse-width modulator (PWM), and I/O ports. The MSM66Q589 is a Flash EEPROM version. FEATURES • Program memory space Internal ROM : : : : : 128K bytes 96K bytes (MSM66589/66P589) 128K bytes (MSM66Q589) 64K bytes 4K bytes • Data memory space Internal RAM • High-speed execution Minimum instruction execution time : 100 nsec (@ 20 MHz) • Built-in multiplier • Powerful instruction set : Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instructions ROM table reference instructions • Abundant addressing modes : Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate addressing • I/O port Analog input only ports : 16 channels Input-output ports : 11 ports ¥ 8 bits, 1 port ¥ 6 bits (Each bit can be configured to be an input or output) • Flexible timers Free run counters : 19 bits ¥ 1, 16 bits ¥ 1 19-bit CAP with a divider : 4 16-bit double buffer RTO : 6 16-bit RTO/PWM : 2 16-bit CAP/RTO : 6 • 8-bit general timer : 1 8-bit event counter : 1 • 16-bit PWM : 8 Input clock divider : 1 • 8-bit serial ports 1/27 ¡ Semiconductor MSM66589/66P589/66Q589 UART mode with BRG : 1 Synchronous/UART switchable mode with BRG : 1 • 10-bit A/D converter : 16 channels • Transition detector : 6 • Watchdog timer : 1 • Interrupts Non-maskable : 1 Maskable : Internal 47/external 2 (4-level priority can be set) • ROM window function • Standby modes HALT mode STOP mode • Package: 128-pin plastic QFP (QFP128-P-2828-BK) (Product name: MSM66589-¥¥¥GS-BK) (Product name: MSM66P589-¥¥¥GS-BK) (Product name: MSM66Q589GS-BK) ¥¥¥ indicates the code number. 2/27 * Peripheral P7_3/CLKOUT O S C 0 O S C 1 R E S System Control Instruction Decoder Memory Control Pointing R. Local R. P P P P P P P PPPPP 012345678911 01 Port Control ROM * 96K bytes RAM 4K bytes MSM66Q589 (Flash EEPROM version) contains 128K bytes Flash EEPROM. ALU Control ACC ALU PC LRB TSR CSR PSW CPU Core SSP Control Registers BUS PORT CONTROL WDT Interrupt Transition Detector Event Timer A/ D Converter PWM Serial Port Flexible Timer P6_0/INT0 P6_1/INT1 NMI P4_7/TRNS5 P4_2/TRNS0 P4_0/ETMCK P4_1/ECTCK AI15 AVDD VREF AGND AI0 P8_3/PWM7 P7_4/PWM0 P10_5/FTM17 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0 P3_7/CAP3 P10_0/RTO12 P10_1/RTO13 P10_2/FTM14 P3_3/FTM11D P3_4/CAP0 P2_5/RTO9 P2_6/FTM10 P3_0/FTM11A P3_1/FTM11B P2_0/RTO4 O E A15/P1_7 A16/P9_0 A8/P1_0 AD7/P0_7 AD0/P0_0 EA ALE/P5_5 PSEN/P5_4 RD/P7_1 WR/P7_0 WAIT/P7_2 ¡ Semiconductor MSM66589/66P589/66Q589 BLOCK DIAGRAM 3/27 TRNS2/P4_4 TRNS1/P4_3 TRNS0/P4_2 ECTCK/P4_1 ETMCK/P4_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 VDD CAP3/P3_7 CAP2/P3_6 CAP1/P3_5 CAP0/P3_4 FTM11D/P3_3 FTM11C/P3_2 FTM11B/P3_1 FTM11A/P3_0 GND P10_7 P10_6 FTM17/P10_5 FTM16/P10_4 FTM15/P10_3 FTM14/P10_2 RTO13/P10_1 RTO12/P10_0 P2_7 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P2_6/FTM10 P2_5/RTO9 P2_4/RTO8 P2_3/RTO7 P2_2/RTO6 P2_1/RTO5 P2_0/RTO4 VDD P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0/A16 P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 GND P0_7/AD7 P0_6/AD6 P0_5/AD5 P0_4/AD4 P0_3/AD3 P0_2/AD2 P0_1/AD1 4/27 MSM66589/66P589/66Q589 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 ¡ Semiconductor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PIN CONFIGURATION (TOP VIEW) TRNS3/P4_5 TRNS4/P4_6 TRNS5/P4_7 P5_0 P5_1 P5_2 P5_3 NMI RES EA VDD AVDD VREF AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 AI9 AI10 AI11 AI12 AI13 AI14 AI15 AGND GND INT0/P6_0 128-Pin Plastic QFP (FLAT) P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0 GND OSC0 OSC1 P5_5/ALE P5_4/PSEN P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4/PWM0 P7_5/PWM1 P7_6/PWM2 P7_7/PWM3 VDD P8_0/PWM4 P8_1/PWM5 P8_2/PWM6 P8_3/PWM7 P8_4 P8_5 P8_6 P8_7 GND OE P0_0/AD0 ¡ Semiconductor MSM66589/66P589/66Q589 PIN DESCRIPTION Symbol Type P0_0-P0_7/ AD0-AD7 I/O P0: 8-bit input-output port. Each bit can be assigned to be an input or an output. AD: When an external memory is used, these pins output the lower 8 bits of the address. These pins also input or output the data. P1_0-P1_7/ A8-A15 I/O P1: 8-bit input-output port. Each bit can be assigned to input or output. A: When an external memory is used, these pins output the upper 8 bits of the address. P2_0-P2_5/ RTO4-RTO9 P2_6/FTM10 P2_7 I/O P2: 8-bit input-output port. Each bit can be assigned to input or output. RTO: Output pin for real time output FTM10: Capture input pin or real-time output pin I/O P3: 8-bit input-output port. Each bit can be assigned to input or output. FTM11A: Capture input pin or real-time output pin FTM11B-D: 4-port real-time output pin CAP : Capture input pin I/O P4: 8-bit input-output port. Each bit can be assigned to input or output. ETMCK: External clock input pin of 8-bit general timer ECTCK: External clock input pin of 8-bit event counter TRNS: Transition detector input pin I/O P5: 6-bit input-output port. Each bit can be assigned to input or output. PSEN: Strobe pulse output pin to fetch to external program memory ALE: Timing pulse output pin to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory I/O P6: 8-bit input-output port. Each bit can be assigned to input or output. INT0, 1: External interrupt request input pin RXD1 : SCI1 Receiver data input pin TXD1 : SCI1 Transmitter data output pin RXC1 : SCI1 Receiver circuit clock pin TXC1 : SCI1 Transmitter circuit clock pin RXD0 : SCI0 Receiver data input pin TXD0 : SCI0 Transmitter data output pin P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4-P7_7/ PWM0-PWM3 I/O P7: 8-bit input-output port. Each bit can be assigned to input or output. WR: Write strobe output pin for external data memory RD: Read strobe output pin for external data memory WAIT: CPU wait request input pin when accessing external data memory CLKOUT: Output pin to output clock pulse specified by PRPHF PWM: PWM output pin P8_0-P8_3/ PWM4-PWM7 P8_4-P8_7 I/O P3_0-P3_3/ FTM11A-FTM11D P3_4-P3_7/ CAP0-CAP3 P4_0/ETMCK P4_1/ECTCK P4_2-P4_7/ TRNS0-TRNS5 P5_0-P5_3 P5_4/PSEN P5_5/ALE P6_0/INT0 P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0 P9_0/A16 P9_1-P9_7 I/O Description P8: 8-bit input-output port. Each bit can be assigned to input or output. PWM: PWM output pin P9: 8-bit input-output port. Each bit can be assigned to input or output. A16: When an external program memory is used, this pin outputs the MSB of the address. P10_0-P10_1/ RTO12-RTO13 P10_2-P10_5/ FTM14-FTM17 P10_6-P10_7 I/O P10: 8-bit input-output port. Each bit can be assigned to input or output. RTO: Output pin for real time output. FTM: Capture input pin or real-time output pin P11_0-P11_7 I/O P11: 8-bit input-output port. Each bit can be assigned to input or output. 5/27 ¡ Semiconductor MSM66589/66P589/66Q589 PIN DESCRIPTION (Continued) Symbol Type Description AI0-AI15 I Analog signal input pin for A/D converter AVDD I Power supply input pin for A/D converter VREF I Reference voltage input pin for A/D converter AGND I GND input pin for A/D converter OSC0 I OSC1 O Basic clock oscillation pin When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "H" level, P0, P1, P2, P7_4-P7_7, and P8-P11 go to a high-impedance state. When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "L" level, P0, P1, P2, P7_4-P7_7, and P8-P11 output "H" or "L" level. However, when P0, P1, P2, P7_4-P7_7, and P8-P11 are in an input state, these ports are not under the influence of OE pin. OE I NMI I Nonmaskable interrupt request input pin RES I Low-active RESET input pin EA I Normally set to "H" level. If set to "L" level, the program memory goes into external access mode and accesses external program memory VDD I Power supply pin GND I Ground pin 6/27 ¡ Semiconductor MSM66589/66P589/66Q589 REGISTERS Accumulator Control Register (CR) Program Status Word 15 0 ACC 15 0 PSW Bit 15 : Carry flag (CY) Bit 14 : Zero flag (ZF) Bit 13 : Half carry flag (HC) Bit 12 : Data descriptor (DD) Bit 11 : Sign flag (S) Bit 10 : Master interrupt priority flag (MIP) Bit 9 : Overflow flag (OV) Bit 8 : Master interrupt enable flag (MIE) Bit 7 : Multiply and accumulate operation bank flag (MAB)* Bit 6 : User flag (F1) Bit 5 : Bank common base (BCB1)* Bit 4 : Bank common base (BCB0)* Bit 3 : User flag (F0) Bit 2-0 : System control base 2-0 (SCB2-0) * Bit 7 (MAB), Bit 5 (BCB1), and Bit 4 (BCB0) can be used as the User flag. 15 0 Program Counter PC Local Register Base LRB System Stack Pointer SSP Segment Register Code Segment Register 7 0 CSR Table Segment Register TSR Pointing Register (PR) 15 Index Register 1 Index Register 2 Data pointer User Stack Pointer 0 X1 X2 DP USP 7/27 ¡ Semiconductor MSM66589/66P589/66Q589 7 Local Register 0 7 0 ER0 ER1 R1 R0 R3 R2 ER2 R5 R4 ER3 R7 R6 8/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR Address [H] 0000 0001 0002 0003 0004 0005 0006 0007 0008✩ Name System Stack Pointer Local Register Base Program Status Word Accumulator Table Segment Register Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation — LRBL LRBH PSWL PSWH ACCL ACCH SSP 16 R/W 8/16 — 00 00 00 ACC TSR FFFF Undefined LRB PSW Reset Status 00 8 00 0009 000A 000B ROM Window Register ROMWIN — 000C✩ ROM Ready Control Register ROMRDY — 000D✩ RAM Ready Control Register RAMRDY — 000E Stop Code Acceptor STPACP — 000F✩ Standby Control Register SBYCON — 0010 Port 0 Data Register P0 0011 Port 1 Data Register P1 0012 Port 2 Data Register P2 0013 Port 3 Data Register P3 0014 Port 4 Data Register P4 0015✩ Port 5 Data Register P5 0016 Port 6 Data Register P6 0017 Port 7 Data Register P7 0018 Port 0 Mode Register P0IO 0019 Port 1 Mode Register P1IO 001A Port 2 Mode Register P2IO 001B Port 3 Mode Register P3IO 001C Port 4 Mode Register P4IO 001D✩ Port 5 Mode Register P5IO 001E Port 6 Mode Register P6IO 001F Port 7 Mode Register P7IO 0020 Port 8 Data Register P8 0021 Port 9 Data Register P9 0022 Port 10 Data Register P10 0023 Port 11 Data Register P11 0024 0025✩ TRNS Control Register 0026✩ Transition Detector 0027 Watchdog Timer — — 00 FF R/W 8 "0" W C8 00 P0P1 00 00 P2P3 00 00 P4P5 C0 00 P6P7 00 00 P0P1IO 8/16 P2P3IO R/W C0 00 00 00 P8P9 00 00 P10P11 00 16 TRNSCON — — 00 00 P6P7IO WDT 00 00 P4P5IO TRNSIT FF W 8 F000 C0 Stop ✩ mark in the address column indicates that there is a nonexistent bit in its register. 9/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation 0028 Port 8 Mode Register P8IO 0029 Port 9 Mode Register P9IO 002A Port 10 Mode Register P10IO 002B Port 11 Mode Register P11IO 002C✩ A/D Interrupt Control Register ADINTCON — 002D✩ A/D Hardware Select Enable Register ADHENCON — 002E 002F A/D Hardware Select Register — — Reset Status 00 P8P9IO 8/16 P10P11IO 00 00 R/W 8 ADHSEL 00 16 C0 F0 0000 0030 0031 Port 1 Secondary Function Control Register P1SF — 00 0032✩ Port 2 Secondary Function Control Register P2SF — 80 0033 Port 3 Secondary Function Control Register P3SF — 00 0034 Port 4 Secondary Function Control Register P4SF — 00 0035✩ Port 5 Secondary Function Control Register P5SF — 0036 Port 6 Secondary Function Control Register P6SF — 00 0037 Port 7 Secondary Function Control Register P7SF — 00 0038✩ Port 8 Secondary Function Control Register P8SF — F0 0039✩ Port 9 Secondary Function Control Register P9SF — 00 Port 10 Secondary Function Control Register P10SF -— 00 003A✩ R/W 8 CF 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F IRQD0L Interrupt Request Flag Disable Register 0 IRQD0H Interrupt Request Flag Disable Register1 IRQD1H Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Control Register 00 Interrupt Priority Control Register 01 Interrupt Priority Control Register 10 Interrupt Priority Control Register 11 IRQD1L IRQ0L IRQ0H IRQ1L IRQ1H IE0L IE0H IE1L IE1H IP00L IP00H IP01L IP01H IP10L IP10H IP11L IP11H 00 IRQD0 00 00 IRQD1 00 00 IRQ0 00 00 IRQ1 IE0 IE1 IP00 IP01 IP10 IP11 ✩ mark in the address column indicates that there is a nonexistent bit in its register. 00 R/W 8/16 00 00 00 00 00 00 00 00 00 00 00 00 10/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 Name Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation Reset Status PWM Counter 0 — PWC0 FFFF PWM Counter 1 — PWC1 FFFF PWM Counter 2 — PWC2 FFFF PWM Counter 3 — PWC3 PWM Counter 4 — PWC4 FFFF PWM Counter 5 — PWC5 FFFF PWM Counter 6 — PWC6 FFFF PWM Counter 7 — PWC7 FFFF PWC0 Buffer Register — PWC0BF FFFF PWC1 Buffer Register — PWC1BF FFFF PWC2 Buffer Register — PWC2BF FFFF PWC3 Buffer Register — PWC3BF FFFF PWC4 Buffer Register — PWC4BF FFFF PWC5 Buffer Register — PWC5BF FFFF PWC6 Buffer Register — PWC6BF PWC7 Buffer Register — PWC7BF FFFF PWR0 Buffer Register — PW0BF 0000 PWR1 Buffer Register — PW1BF 0000 PWR2 Buffer Register — PW2BF 0000 PWR3 Buffer Register — PW3BF 0000 FFFF R 16 ✩ mark in the address column indicates that there is a nonexistent bit in its register. R/W FFFF 11/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] 0078 0079 007A 007B 007C 007D 007E 007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F Name Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation PWR4 Buffer Register — PW4BF PWR5 Buffer Register — PW5BF Reset Status 0000 0000 R/W PWR6 Buffer Register — PW6BF 0000 PWR7 Buffer Register — PW7BF 0000 Timer Register 0 — TMR0 Undefined Timer Register 1 — TMR1 Undefined Timer Register 2 — TMR2 Undefined Timer Register 3 — TMR3 Undefined Timer Register 4 — TMR4 0000 Timer Register 5 — TMR5 R 0000 16 Timer Register 6 — TMR6 0000 Timer Register 7 — TMR7 0000 Timer Register 8 — TMR8 0000 Timer Register 9 — TMR9 0000 Timer Register 10 — TMR10 0000 Timer Register 11 — TMR11 0000 Timer Register 12 — TMR12 0000 Timer Register 13 — TMR13 0000 Timer Register 14 — TMR14 0000 Timer Register 15 — TMR15 0000 R/W ✩ mark in the address column indicates that there is a nonexistent bit in its register. 12/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation Reset Status Timer Register 16 — TMR16 0000 Timer Register 17 — TMR17 0000 TMR4 Buffer Register — TMR4BF 0000 TMR5 Buffer Register — TMR5BF 0000 16 TMR6 Buffer Register — TMR6BF 0000 TMR7 Buffer Register — TMR7BF 0000 TMR12 Buffer Register — TMR12BF 0000 TMR13 Buffer Register — TMR13BF 0000 00B0✩ RTO Control Register 0 RTOCON0 — F8 00B1✩ RTO Control Register 1 RTOCON1 — 00B2✩ RTO Control Register 2 RTOCON2 — 00B3✩ RTO Control Register 3 RTOCON3 — F8 00B4✩ RTO Control Register 4 RTOCON4 — FC 00B5✩ RTO Control Register 5 RTOCON5 — FC 00B6✩ RTO Control Register 6 RTOCON6 — 00B7✩ RTO Control Register 7 RTOCON7 — 00B8 RTO Control Register 8 RTOCON8 — 00 00B9✩ RTO Control Register 9 RTOCON9 — F8 00BA✩ RTO Control Register 10 RTOCON10 — F8 00BB✩ RTO Control Register 11 RTOCON11 — F8 00BC✩ RTO Control Register 12 RTOCON12 — F8 00BD✩ RTO Control Register 13 RTOCON13 — F8 00BE✩ RTO Control Register 14 RTOCON14 — F8 00BF✩ Timer Counter 0 Low-order 3 bits TM0L — 1F — TM0 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00C0 00C1 00C2 00C3 00C4✩ Timer Counter 0 F8 R/W F8 F8 8 F8 0000 16 Timer Counter 1 TMR0 Low-order 3 Bits — TM1 0000 TMR0L — Undefined 00C5✩ TMR1 Low-order 3 Bits TMR1L — 00C6✩ TMR2 Low-order 3 Bits TMR2L — 00C7✩ TMR3 Low-order 3 Bits TMR3L — ✩ mark in the address column indicates that there is a nonexistent bit in its register. R 8 Undefined Undefined Undefined 13/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation Reset Status 00C8✩ Event Dividing Counter 0 EVDV0 — C0 00C9✩ Event Dividing Counter 1 EVDV1 — C0 00CA✩ Event Dividing Counter 2 EVDV2 — 00CB✩ Event Dividing Counter 3 EVDV3 — 00CC✩ EVDV0 Buffer Register EVDV0BF — C0 00CD✩ EVDV1 Buffer Register EVDV1BF — C0 00CE✩ EVDV2 Buffer Register EVDV2BF — C0 00CF✩ EVDV3 Buffer Register EVDV3BF — C0 00D0 A/D Result Register 0 ADCR0 ADCR0W 00D1 A/D Result Register 1 ADCR1 ADCR1W 00D2 A/D Result Register 2 ADCR2 ADCR2W 00D3 A/D Result Register 3 ADCR3 ADCR3W 00D4 A/D Result Register 4 ADCR4 ADCR4W 00D5 A/D Result Register 5 ADCR5 ADCR5W 00D6 A/D Result Register 6 ADCR6 ADCR6W 00D7 A/D Result Register 7 ADCR7 ADCR7W 00D8 A/D Result Register 8 ADCR8 ADCR8W 00D9 A/D Result Register 9 ADCR9 ADCR9W 00DA A/D Result Register 10 ADCR10 ADCR10W 00DB A/D Result Register 11 ADCR11 ADCR11W 00DC A/D Result Register 12 ADCR12 ADCR12W 00DD A/D Result Register 13 ADCR13 ADCR13W 00DE A/D Result Register 14 ADCR14 ADCR14W 00DF A/D Result Register 15 ADCR15 ADCR15W 00E0✩ A/D Control Register L ADCONL — 80 00E1✩ A/D Control Register H ADCONH — 80 00E2 Timer Control Register TMCON — 00E3✩ TM Setting Register 2 TMSEL2 — — TMSEL TMR Mode Register TMRMODE — TMR Mode Register 2 TMRMODE2 — — CAPCON CAPCON2 — 00 00 00E4 00E5✩ 00E6 00E7✩ 00E8 00E9✩ TM Setting Register Capture Control Register 00EA Capture Control Register 2 00EB PWM RUN Register PWRUN — 00EC PWM Control Register 0 PWCON0 — C0 R/W R/W (*1) 8 8/16 (*1) 8 C0 Undefined 00 C0 16 8 R/W 16 8 0000 00 C0 0000 00 00ED PWM Control Register 1 PWCON1 — 00EE PWM Control Register 2 PWCON2 — 00 00EF PWM Control Register 3 PWCON3 — 00 ✩ mark in the address column indicates that there is a nonexistent bit in its register. 00 14/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation Reset Status 00F0 PWM Interrupt Register 0 PWINTQ0 00F1 PWM Interrupt Register 1 PWINTQ1 00F2 PWM Interrupt Enable Register 0 PWINTE0 00F3 PWM Interrupt Enable Register 1 PWINTE1 00F4 SCI0 Transmit/Receive Buffer Register S0BUF — Undefined 00F5 SCI0 Status Register S0STAT — 00 00F6 SCI1 Transmit/Receive Buffer Register S1BUF — 00F7 SCI1 Status Register S1STAT — 00F8✩ General-purpose 8-bit Timer Control Register GTMCON — 00F9 8-bit Event Counter GEVC — 00FA General-purpose 8-bit Timer Counter GTMC — 00 00FB General-purpose 8-bit Timer Register GTMR — 00 EVNTCONL — 88 EVNTCONH — 88 00FC✩ 00FD✩ Event Control Register 00FE Emulator Use Area 00 PWINTQ 8/16 PWINTE 00 00 00 R/W Undefined 00 8 00FF * Note 3 0100 Memory Size Acceptor MEMSACP — W 0101✩ Memory Size Control Register MEMSCON — R/W PRPHF — 8 30 00 "0" FC 0102 0103 0104 0105 0106 0107✩ Peripheral Control Register 0108✩ NMI Control Register NMICON — 0109✩ External Interrupt Control Register EXICON — — S0TM S0CON — (*3) R/W 8 FC or 7C 00 010A 010B 010C 010D 010E 010F 0110 0111 SCI0 Timer 0112✩ SCI0 Timer Control Register 0113✩ SCI0 Transmit Control Register ST0CON — 0114✩ SCI0 Receive Control Register SR0CON — 16 R/W 0000 02 8 8A 1A 0115 0116 0117 15/27 ¡ Semiconductor MSM66589/66P589/66Q589 SFR (Continued) Address [H] 0118 0119 Name SCI1 Timer Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation — S1TM 011A✩ SCI1 Timer Control Register S1CON — 011B✩ SCI1 Transmit Control Register ST1CON — 011C✩ SCI1 Receive Control Register SR1C0N — 16 R/W Reset Status 0000 02 8 88 08 011D 011E✩ TBC Clock Dividing Counter TBCKDVC — R 011F✩ TBC Clock Dividing Register TBCKDVR — R/W 8 F0 F0 0120 0121 0122 0123 0124 0125 0126 0127 ✩ mark in the address column indicates that there is a nonexistent bit in its register. *1 The 8/16 bit operation for the ADCR items is a special word manipulation. If a byte access is made, high-order 8 bits of the A/D Result register are accessed, and if a word access is made, the 10-bit contents of the A/D Result register are accessed. Data can be written in the even number A/D Result registers and the odd number A/D Result registers separately. When data is first written in the A/D Result register 0 (ADCR0), data is also written in other even number A/D Result registers at a time. When data is first written in the A/D Result register 1 (ADCR1), data is also written in other odd A/D Result registers at a time. *2 Do not access the emulator use area. *3 The initial values of PRPHF (SFR=107H) are as follows: At reset by RES pin: VBFF (bit 6) is "1"; CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". At reset by WDT and BRK instructions and operation code trap: VBFF (bit 6) holds the value just before reset; CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". In both cases, the OE pin status is read for OERD (bit 7). 16/27 ¡ Semiconductor MSM66589/66P589/66Q589 ADDRESSING MODES The MSM66589/66P589/66Q589 provides independent 64K-byte data and 128K-byte program spaces with various types of addressing modes. These modes are shown below for both RAM (for data space) and ROM (for program space). RAM Addressing Mode (for data space) • Register addressing Example INC USP USP • Page addressing a) sfr page Example L A, sfr IRQ0 SFR 0000H 0040H b) Fixed page Example ST A, fix 0C0H RAM 0200H 02C0H c) Current page Example ROR off 078H RAM xx00H xx78H • Direct data addressing Example CLR dir 780H RAM 0700H 0780H 17/27 ¡ Semiconductor MSM66589/66P589/66Q589 • Pointing register indirect addressing a) DP/X1 indirect Example XCHG A, [DP] RAM DP b) Post increment DP indirect Example ADD A, [DP+] RAM DP After access, DP is incremented by 2. c) Post decrement DP indirect Example SUB A, [DP-] RAM DP After access, DP is decremented by 2. d) DP/USP indirect with 7-bit displacement Example AND A, 12[DP] –64 to +63 RAM DP e) X1/X2 indirect with 16-bit base Example XOR A, 1234H[X1] 0-65535 RAM X1 f) X1 indirect with 8-bit register (A, R0) displacement Example OR A, [X1+A] AL RAM X1 18/27 ¡ Semiconductor MSM66589/66P589/66Q589 • Special bit area addressing a) Fixed page SBA area (02C0H to 02FFH) Example SB sbafix 2D1H.3 RAM 02C0H 02D1H b) Current page SBA area (¥¥C0H to ¥¥FFH) Example RB sbaoff 2E9H.7 RAM ¥¥C0H ¥¥E9H ROM Addressing Mode (for program space) • Immediate addressing Example MOV SSP, #7FFH ROM Address xxxxH • Table data addressing TSR specifies the address segment. a) Direct Example LC A, 5678H ROM 5678H b) RAM addressing indirect Example CMPC A, [USP] ROM USP c) RAM addressing indirect with 16-bit base Example LC A, 1234H[ER0] 0-65535 ROM RAM ER0 19/27 ¡ Semiconductor MSM66589/66P589/66Q589 MEMORY MAP Program Memory Space Segment 0 Segment 1 0000H 0000H Vector table area (74 bytes) 0049H 004AH 0069H 006AH VCAL table area (32 bytes) Internal ROM area 0FFFH 1000H Internal ROM area 0FFFH 1000H ACAL area (2K bytes) ACAL area (2K bytes) 17FFH 1800H 17FFH 1800H 7FFFH 8000H External ROM area * FFFFH * FFFFH For MSM66Q589 (Flash EEPROM version), 8000H to 0FFFFH in Segment 1 are in the internal ROM area. Data Memory Space Expanded SFR Area FIX Area Internal RAM Area Area where local register can be set 01FFH 0200H 0208H 0210H 0238H 11FFH 1200H Expanded SFR Area X1 X2 DP USP X1 X2 DP USP X1 USP X1 X2 DP USP SCB=0 SCB=1 Pointing Register Set ..... 09FFH 0A00H SFR Area .... 0000H 00FFH 0100H 01FFH 0200H 02FFH 0300H SCB=7 0240H External Memory Area Area where ROM window can be set FFFFH 02C0H SBA Area (64 bytes) 0300H Area where SB, RB, JBS, and JBR instructions can be performed in shorter byte count. 20/27 ¡ Semiconductor MSM66589/66P589/66Q589 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Parameter Digital Power Supply Voltage Input Voltage Output Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Power Dissipation Storage Temperature Symbol VDD Condition VI GND=AGND=0 V VO AVDD Ta = 25°C –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 Unit V –0.3 to AVDD+0.3 –0.3 to VREF VREF VAI PD Rating –0.3 to 7.0 Ta=85°C TSTG Per package Per output — 855 50 –50 to +150 mW °C RECOMMENDED OPERATING CONDITIONS Parameter Digital Power Supply Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency Symbol VDD AVDD VREF VAI Condition fOSC£20 MHz VDD=AVDD — — VDDH fOSC fOSC=0 Hz VDD=5 V±10% Ambient Temperature Ta — MOS load Fan Out N TTL load P0, P5_4, P5_5, P7_0, P7_1 P1 to P11 (except P5_4,P5_5, P7_0, P7_1) Range 4.5 to 5.5 4.5 to 5.5 AVDD–0.3 to AVDD AGND to VREF 2.0 to 5.5 0 to 20 –40 to +85 20 2 1 Unit V MHz °C — 21/27 ¡ Semiconductor MSM66589/66P589/66Q589 ELECTRICAL CHARACTERISTICS DC Characteristics (Preliminary) (VDD=5 V±10%, Ta=–40 to +85˚C) Parameter H Level Input Voltage 1 H Level Input Voltage 2, 4, 5, 6, 7 L Level Input Voltage 1 L Level Input Voltage 2, 4, 5, 6, 7 H Level Output Voltage 1, 4 H Level Output Voltage 2 L Level Output Voltage 1, 4 L Level Output Voltage 2 Input Leakage Current 3, 6 Input Current Input Current H Level Output Current 5 Symbol Condition VIH – VIL VOH VOL IIH/IIL 2 L Level Output Current 1, 4 L Level Output Current 2 Output Leakage Current 1, 2, 4 CI CO Analog Reference Current IREF Current Consumption (in STOP mode) IDDS Current Consumption (in HALT mode) IDDH Current Consumption IDD VDD+0.3 0.80VDD VDD+0.3 –0.3 – 0.8 – 0.2VDD – – IOH=–200 mA VDD–0.4 – – IOL=3.2 mA – – 0.4 IOL=1.6 mA – – 0.4 – – 1/–1 – – 1/–250 – – 15/–15 –2 – – –1 – – 10 – – 5 – – – – ±2 – 5 – – – 6 mA 10 µA VI=VDD/0 V IOL Output Capacitance – – –0.3 VO=2.4 V Input Capacitance 2.2 Unit VDD–0.4 IOH ILO Max. IOH=–400 mA 7 1, 4 H Level Output Current 1. 2. 3. 4. 5. 6. 7. * – Typ. Min. VO=VDD/0 V f=1 MHz, Ta=25˚C A/D in operation – 7 – A/D stopped – – VDD=2 V, Ta=25˚C* – 0.2 10 * – 1 100 fOSC=20 MHz No load – 45 – 80 V µA mA µA pF µA mA Applied to P0 Applied to P1 to P11 (except P5_4, P5_5, P7_0, P7_1) Applied to AIN Applied to P5_4, P5_5, P7_0, P7_1 Applied to RES Applied to EA, OE, NMI Applied to OSC0 Ports for input pins are VDD or GND, otherwise no load. 22/27 ¡ Semiconductor MSM66589/66P589/66Q589 AC Characteristics (Preliminary) • External program memory control (VDD=5 V±10%, Ta=–40 to +85°C) Symbol Condition Min. Max. Clock (OSC) pulse width Parameter tøW — 25 — ALE pulse width tAW 2tøW–10 — PSEN pulse width tPW 2tøW–10 — PSEN pulse delay time tPAD tøW–10 tøW+10 Low-order address set-up time tALS 2tøW–10 2tøW+10 Low-order address hold time tALH tøW–10 tøW+10 High-order address set-up time tAHS 3tøW–10 3tøW+10 High-order address hold time CL=50 pF tAPH tøW+10 Instruction set-up time tIS — Instruction hold time tIH tøW–10 Unit nsec • External data memory control (VDD=5 V±10%, Ta=–40 to +85°C) Parameter Symbol Condition Clock (OSC) pulse width tøW — 25 — ALE pulse width tAW 2tøW–10 — RD pulse width WR pulse width tRW tWW 2tøW–10 2tøW–10 — — RD pulse delay time tRAD tøW–10 tøW+10 WR pulse delay time tWAD tøW–10 tøW+10 Low-order address set-up time tALS 2tøW–10 2tøW+10 Low-order address hold time tALH High-order address set-up time High-order address hold time tAHS tAHH CL=50 pF Min. Max. tøW–10 tøW+10 3tøW–10 tøW–0 3tøW+10 tøW+10 Memory data set-up time tMS — Memory data hold time Data set-up time tMH tDD tALH–0 tøW–10 tALH+10 Data hold time tDH tøW–10 tøW+10 Unit nsec 23/27 ¡ Semiconductor MSM66589/66P589/66Q589 CLK tøW tøW ALE tAW PSEN tPAD AD 0-7 tPW PC 0-7 tALS INST 0-7 tALH A 8-16 tIS tIH PC 8-16 tAHS tAPH RD tRAD AD 0-7 tRW RAP 0-7 tALS DIN 0-7 tALH A 8-15 tMS tMH RAP 8-15 tAHH tAHS WR tWAD AD 0-7 tWW RAP 0-7 tALS DOUT 0-7 tALH tDH tDD A 8-15 RAP 8-15 tAHS tAHH 24/27 ¡ Semiconductor MSM66589/66P589/66Q589 A/D CONVERTER CHARACTERISTICS (Preliminary) (Ta=–40 to +85˚C, AVDD=VDD=VREF=5 V±10%, AGND=GND=0 V, fOSC=20 MHz) Parameter Condition Min. Typ. Max. Unit Refer to the recommended circuit. Analog input source impedance RI £ 5 kW tCONV=19.2 msec — — 10 Bit — — — — Symbol n Resolution Linearity Error EL Differential Linearity Error ED Zero Scale Error EZS Full Scale Error EFS Crosstalk ECT tCONV Conversion Time — — Refer to the measuring circuit. — — by ADTM set data 6.4 – VREF AVDD RI 19.2 µs/CH +5 V VDD + – LSB 47 W 0.1 µF Reference Voltage — + 0.1 47 µF µF 0.1 µF 47 µF AI 0-15 + Analog input AGND GND 0V 0.1 µF RI (Analog input source impedance) £ 5 kW Recommended Circuit 25/27 ¡ Semiconductor – MSM66589/66P589/66Q589 5 kW AI0 ~ + Analog input AI1 0.1mF Crosstalk is defined as the difference between the A/D conversion result when applying the identical analog input to AI0 to AI15 and the A/D conversion result in the circuit in the left figure. AI15 VREF or AGND Crosstalk Measuring Circuit Definitions of Terms Resolution The minimum distinguishable analog input value. For 10 bits, 210=1024, i.e. (VREF–AGND) ÷ 1024. Linearity error The variance between the ideal conversion characteristics as a 10-bit A/D converter and the actual conversion characteristics. (Quantized error is therefore not included.) In the ideal conversion, a voltage between VREF and AGND is divided into 1,024 equal steps. Differential linearity error The smoothness of the conversion. The width of analog input voltage corresponding to the change by one bit of digital output is 1 LSB=(VREF–AGND) ÷ 1024 ideally. The variance between this ideal bit size and bit size at arbitrary point in the conversion range. Zero scale error The variance between the ideal conversion characteristics at the switching point of digital output "000H to 001H" and actual conversion characteristics. Full scale error The variance between the ideal conversion characteristics at the switching point of digital output "3FEH to 3FFH" and actual conversion characteristics. 26/27 ¡ Semiconductor MSM66589/66P589/66Q589 PACKAGE DIMENSIONS (Unit : mm) QFP128-P-2828-0.80-BK QFP128-P-2828-0.80-ZK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 5.95 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/27