DS8129A 01

RT8129A
High Efficiency Single Synchronous Buck PWM Controller
General Description
Features
The RT8129A is a high efficiency single phase
synchronous buck controller with 5V/12V supply
voltage. The RT8129A integrates a Constant-On-Time
(COT) PWM controller and a MOSFET drivers with
internal bootstrap diodes, which is specifically designed
to improve converter efficiency at light load condition.
At light load condition, it automatically operates in the
diode emulation mode to reduce switching frequency
and improve conversion efficiency.
Other features include power good indication,
enable/disable control and internal soft-start function.
The RT8129A also provide protection functions
including Over Voltage Protection (OVP), Under
Voltage Protection (UVP), current limit and thermal
shutdown.
This device uses lossless low-side MOSFET RDS(ON)
current sense technique for current limit with adjustable
threshold set by connecting a resistor between the
LGATE/OCSET and GND.
With
above
functions,
the
RT8129A
 Wide Input Voltage Range : 2.5V to 25V
 High Light Load Efficiency
 Integrated High Driving Capability N-MOSFET
Gate
 Drivers and Embedded Switching Boot Diode








Single IC Supply Voltage : 4.5V to 13.2V
Power-Good Indicator
Enable/Disable Control
Internal Soft-Start
Programmable Current Limit Threshold
Under Voltage Protection
Over Voltage Protection
Thermal Shutdown
Applications



Motherboard, Memory/Chip-set Power
Graphic Card, GPU/Memory Core Power
Low Voltage, High Current DC/DC Regulator
Marking Information
provides
customers a cost-effective solution for high efficiency
power conversion. The RT8129A is available in the
WDFN-10L 3x3 package.
5N=YM
DNN
5N= : Product Code
YMDNN : Date Code
Simplified Application Circuit
VIN
RT8129A
VCC
VCC
BOOT
UGATE
PHASE
VPGOOD
PGOOD
VOUT
LGATE/
OCSET
EN
Enable
FB
GND
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8129A-01
October
2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8129A
Ordering Information
Pin Configurations
RT8129A
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :

BOOT
PHASE
UGATE
LGATE/OCSET
GND
1
2
3
4
5
GND
(TOP VIEW)
Package Type
QW : WDFN-10L 3x3 (W-Type)
11
10
9
8
7
6
PGOOD
NC
FB
EN
VCC
WDFN-10L 3x3
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
BOOT
Bootstrap Supply for High Side Gate Driver. Connect this pin to a power
source VCC through a bootstrap diode, and connect a 0.1F or greater
ceramic capacitor from this pin to the PHASE pin to supply the power for
high side gate driver.
2
PHASE
Switch Node. Connect this pin to the switching node of Buck converter.
Connect this pin to the Source of high-side MOSFET together with the Drain
of low-side MOSFET and the inductor. The PHASE voltage is sensed for
zero current detection and over current protection when low side MOSFET
is on.
3
UGATE
High Side MOSFET Gate Driver Output. This pin provides the gate drive for
the converter's high-side MOSFET. Connect this pin to the Gate of high-side
MOSFET.
4
Low Side MOSFET Gate Driver Output. Connect this pin to the Gate of low
side MOSFET. This pin is also used for current limit threshold setting.
LGATE/OCSET
Connect a resistor (ROCSET) from this pin to the GND pin to set the current
limit threshold.
1
5,
GND
11 (Exposed Pad)
Ground. The Exposed Pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
6
VCC
Supply Voltage Input. It is recommended to connect a 4.7F ceramic
capacitor from this pin to the GND pin. VCC also powers the low side gate
driver.
7
EN
Enable Control Input. Drive EN higher than 2V to turn on the controller,
lower than 0.8V to turn it off. If the EN pin is open, it will be pulled to high by
internal circuit.
8
FB
This pin is used for output voltage feedback input and it is also monitored for
power good indication, over voltage and under voltage protections.
Connect this pin to the converter output through voltage divider resistors for
output voltage regulation.
9
NC
No Internal Connection.
PGOOD
Power Good Indication Output. This pin provides an open drain output.
Connect this pin to a voltage source through a pull up resistor. The PGOOD
voltage goes high to indicate the output voltage is in regulation. This pin can
be left open if the power good indication function is not used.
10
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is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Function Block Diagram
Trigger
TON Generator
1-Shot
VREF
PHASE
BOOT
+
R
COMP
S
-
+
125% VREF
75% VREF
PGOOD
+
PGOOD
Monitor
±10% VREF
LDO&
POR
VCC
EN
UV
Latch
S1
Q
-
FB
OV
Latch
S1
Q
Thermal
Shutdown
PHASE
Min TOFF
1-Shot
Trigger
VCC
LGATE/OCSET
GND
ASM
10µA
+
SS
REF
UGATE
Q
-
+
gm
-
Sample
and Hold
VREF
Operation
The RT8129A integrates a Constant-On-Time (COT)
PWM controller and MOSFET driver so that the
external circuit is easily designed and the components
are reduced.
The controller provides the PWM signal which relies on
the FB voltage comparing with internal reference
voltage. The synchronous UGATE driver is turned on at
the beginning of each cycle. After the internal one-shot
timer expires, the UGATE driver will be turned off. The
pulse width of this one-shot is determined by the
controller's input voltage and the output voltage to keep
the frequency fairly constant over the input voltage and
output voltage range. Another one-shot sets a
minimum off-time.
The RT8129A remains in shutdown if the EN pin
voltage is lower than 0.8V. When the EN pin voltage
rises above the2V, the RT8129A will begin a new
initialization and soft-start cycle.
PGOOD
The power good output is an open-drain architecture,
and it requires a pull-up resistor. During soft-start
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
October
Soft-Start
An internal current source charges an internal capacitor
to build the soft-start ramp voltage.
The output voltage will track the internal ramp voltage
during soft-start interval. The typical soft-start time is
2ms.
Current Limit
Enable
DS8129A-01
process, PGOOD is actively held low and is allowed to
be pulled high after soft start process is completed and
no protection occur. In addition, if the FB pin voltage is
higher than 110% of VREF or lower than 90% of VREF
during operation, PGOOD will be pulled low
immediately.
2015
The current limit circuit employs a unique “valley”
current sensing algorithm. If the magnitude of the
current sense signal at PHASE is above the current
limit threshold, the PWM is not allowed to initiate a new
cycle. Thus, the current to the load exceeds the
average output inductor current, the output voltage falls
and eventually crosses the under-voltage protection
threshold, inducing IC shutdown.
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RT8129A
Over Voltage Protection (OVP)
Under Voltage Protection (UVP)
The FB voltage can be continuously monitored for over
voltage protection. When the FB voltage exceeds
The output voltage can be continuously monitored for
under voltage protection. When the FB voltage is less
125% of the reference voltage, UGATE goes low and
LGATE is forced high. The controller is latched until
VCC is re-supplied and exceeds the POR rising
threshold voltage.
than 75% of the reference voltage, under voltage
protection is triggered and then both UGATE and
LGATE gate drivers are forced low. The controller is
latched until VCC or EN pin voltage is re-supplied and
exceeds the POR rising threshold voltage.
There is a 5s delay built into the under voltage
protection circuit to prevent false transitions.
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There is a 3s delay built into the under voltage
protection circuit to prevent false transitions.
is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Absolute Maximum Ratings
(Note 1)

VCC to GND ------------------------------------------------------------------------------------------------------------ 0.3V to 15V

Other Pins --------------------------------------------------------------------------------------------------------------- 0.3V to 6.5V

BOOT to PHASE
DC--------------------------------------------------------------------------------------------------------------------------0.3V to 15V
<100ns --------------------------------------------------------------------------------------------------------------------0.3V to 20V

PHASE to GND
DC------------------------------------------------------------------------------------------------------------------------- 5V to 25V
<100ns ------------------------------------------------------------------------------------------------------------------- 10V to 30V

BOOT to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 40V
<100ns ------------------------------------------------------------------------------------------------------------------- 0.3V to 45V

UGATE to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 40V
<100ns ------------------------------------------------------------------------------------------------------------------- 10V to 45V

UGATE to PHASE
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 15V
<40ns --------------------------------------------------------------------------------------------------------------------- 5V to 20V

LGATE to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 15V
<100ns ------------------------------------------------------------------------------------------------------------------- 5V to 20V

Power Dissipation, PD @ TA = 25C
WDFN-10L 3x3 -------------------------------------------------------------------------------------------------------- 3.27W

Package Thermal Resistance
(Note 2)
WDFN-10L 3x3, JA -------------------------------------------------------------------------------------------------- 30.5C/W
WDFN-10L 3x3, JC -------------------------------------------------------------------------------------------------- 7.5C/W

Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------------------ 150C

Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility

HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
(Note 3)
Recommended Operating Conditions
(Note 4)

Power Input Voltage, VIN ------------------------------------------------------------------------------------------- 2.5V to 25V

Control Voltage, VCC ------------------------------------------------------------------------------------------------ 4.5V to 13.2V

Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C

Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8129A-01
October
2015
is a registered trademark of Richtek Technology Corporation.
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RT8129A
Electrical Characteristics
(TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VCC rising
--
--
4.4
VCC falling
3.9
--
--
--
0.8
--
V
1
--
1
%
0.8
--
3.3
V
270
300
330
kHz
PWM Controller
VCC POR Threshold
Reference Voltage
VREF
Reference and Error Amplifier
Excluding
External Resistive Divider Tolerance
FB Error Comparator
Threshold
Output Voltage Range
(Note 5)
V
PWM Frequency
FSW
Minimum On-Time
TON(MIN)
--
70
--
ns
Minimum Off-Time
TOFF(MIN)
--
300
--
ns
--
10
40
A
Logic-High VENH
2
--
--
Logic-Low
--
--
0.8
EN Threshold
EN Internal Pull Migh Current
EN Input Voltage
VEN = 0V
VENL
V
PGOOD
Over-Voltage Until
PGOOD Goes Low
Measured at FB, with respect to
reference, no load
--
880
902
mV
Under-Voltage Until
PGOOD Goes Low
Measured at FB, with respect to
reference, no load
--
720
--
mV
Fault Propagation Delay
Falling edge, FB forced below
PGOOD trip threshold
--
1
--
s
Output Low Voltage
ISINK = 1mA
--
--
0.4
V
ILEAK
High state, forced to 5V
--
--
1
A
UGATE Gate Driver Source
RUGATEsr
VBOOT − VPHASE = 12V,
ISOURCE = 100mA
--
1.5
3

UGATE Gate Driver Sink
RUGATEsk
VBOOT − VPHASE = 12V,
ISINK = 10mA
--
2.25
4

LGATE Gate Driver Source
RLGATEsr
VCC = 12V, ISOURCE = 100mA
--
1.5
3

LGATE Gate Driver Sink
RLGATEsk
VCC = 12V, ISOURCE = 10mA
--
1
2

From UG falling to LG rising,
PHASE = 1.5V
5
20
--
From LG falling to UG rising
5
20
--
VCC to BOOT, 10mA
--
--
80
Leakage Current
Driver
Dead Time
Internal Boot Charging
Switch on Resistance
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ns

is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
9.5
10
10.5
A
-20
--
20
mV
0.95
1
1.03
V
--
5
--
s
0.57
0.6
0.63
V
1.2
2
2.8
ms
145
--
165
C
Protection
Current Limit Setting Current
IOCSET
Current Limit Threshold Offset
Over Voltage Protection
Threshold
VOVP
OVP latch delay
Under Voltage Protection
Threshold
VUVP
Voltage Ramp Soft-Start Time
Thermal Shutdown Threshold
From FB 0% to FB 100%
TSD
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. No production tested. Test condition VIN = 7V, VOUT = 1.25V, IOUT = 10A using application circuit.
Typical Application Circuit
VIN
DBOOT
RT8129A
R1
6 VCC
VCC
C4
VPGOOD
BOOT 1
3
UGATE
2
PHASE
C1
RPGOOD
10
7
PGOOD
LGATE/ 4
OCSET
DS8129A-01
2015
Q2
R3
R2
C3
C6
COUT
RFB1
C2
8
GND
5,
11 (Exposed Pad)
October
LOUT
VOUT
RLGATE
EN
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
CIN
Q1
RUGATE
ROCSET
FB
Enable
C5
RBOOT CBOOT
C7
RFB2
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RT8129A
Typical Operating Characteristics
Efficiency vs. Load Current
100
90
90
80
80
70
VIN = 5V
60
VIN = 12V
50
VIN = 19V
Efficiency (%)
Efficiency (%)
Efficiency vs. Load Current
100
40
30
70
VIN = 5V
60
VIN = 12V
50
VIN = 19V
40
30
20
20
10
10
VCC = 5V, VOUT = 1.05V, VNN
0
0.01
0.1
1
VCC = 5V, VOUT = 1.2V, DDRIV
0
0.01
10
0.1
90
90
80
80
VIN = 5V
60
VIN = 12V
50
VIN = 19V
40
30
70
VIN = 5V
60
VIN = 12V
50
VIN = 19V
40
30
20
20
10
10
VCC = 5V, VOUT = 1.35V, DDRIII-L
0
0.01
0.1
1
VCC = 5V, VOUT = 1.5V, DDRIII
0
0.01
10
0.1
1
10
100
Load Current (A)
Load Current (A)
Frequency vs. Load Current
Frequency vs. Load Current
350
350
VCC = 5V, VOUT = 1.05V, VNN
VCC = 5V, VOUT = 1.2V, DDRIV
300
Frequency (kHz)1
300
Frequency (kHz)1
10
Efficiency vs. Load Current
100
Efficiency (%)
Efficiency (%)
Efficiency vs. Load Current
100
70
1
Load Current (A)
Load Current (A)
250
VIN = 5V
200
VIN = 12V
VIN = 19V
150
100
250
200
VIN = 5V
150
VIN = 12V
VIN = 19V
100
50
50
0
0
0.01
0.1
1
Load Current (A)
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10
0.01
0.1
1
10
Load Current (A)
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DS8129A-01
October
2015
RT8129A
Frequency vs. Load Current
Frequency vs. Load Current
350
350
VCC = 5V, VOUT = 1.5V, DDRIII
VCC = 5V, VOUT = 1.35V, DDRIII-L
300
Frequency (kHz)1
Frequency (kHz)1
300
250
200
150
VIN = 5V
100
250
200
150
100
VIN = 5V
VIN = 12V
50
VIN = 12V
50
VIN = 19V
VIN = 19V
0
0
0.01
0.1
1
0.01
10
Frequency vs. Load Current
1
10
Output Voltage vs. Load Current
350
1.060
VIN = 12V, VOUT = 1.2V
300
VCC = 5V
VCC = 12V
Output Voltage (V)
Frequency (kHz)1
0.1
Load Current (A)
Load Current (A)
250
200
150
100
1.055
VIN = 19V
VIN = 12V
VIN = 5V
1.050
1.045
50
VCC = 5V, VOUT = 1.05V,
R1 = 2.49k, R2 = 7.87k, VNN
0
1.040
0.01
0.1
1
10
0.01
Load Current (A)
0.1
1
10
Load Current (A)
Output Voltage vs. Load Current
Output Voltage vs. Load Current
1.205
1.365
1.204
Output Voltage (V)
Output Voltage (V)
1.203
1.202
1.201
1.200
VIN = 19V
1.199
VIN = 12V
1.198
VIN = 5V
1.363
1.361
VIN = 19V
VIN = 12V
1.359
VIN = 5V
1.357
1.197
VCC = 5V, VOUT = 1.35V,
R1 = 2.49k, R2 = 3.57k, DDRIII-L
VCC = 5V, VOUT = 1.2V,
R1 = 1k, R2 = 2k, DDRIV
1.196
1.195
0.01
0.1
1
Load Current (A)
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DS8129A-01
October
2015
10
1.355
0.01
0.1
1
10
Load Current (A)
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9
RT8129A
VREF vs. Temperature
Output Voltage vs. Load Current
0.804
1.530
1.525
0.802
VREF (V)
Output Voltage (V)
0.803
VIN = 19V
1.520
VIN = 12V
VIN = 5V
VCC = 12V
0.801
VCC = 5V
0.800
0.799
1.515
0.798
VCC = 5V, VOUT = 1.5V,
R1 = 1k, R2 = 1.1k, DDRIII
VIN = 12V, No Load
0.797
1.510
0.01
0.1
1
-50
10
-25
0
50
75
100
125
Temperature (°C)
Load Current (A)
Quiescent Current vs. VCC
Shutdown Current vs. VCC
2.5
Shutdown Current (mA)1
6
Quiescent Current (mA)
25
5
4
3
2
1
2.0
1.5
1.0
0.5
VIN = 12V, VOUT = 1.2V, DDR IV, No Load
VIN = 12V, VOUT = 1.2V, DDR IV, No Load
0.0
0
0
2.5
5
7.5
10
12.5
0
15
7.5
10
Power On from EN
Power Off from EN
12.5
15
EN
(5V/Div)
VOUT
VOUT
(500mV/Div)
(500mV/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
PGOOD
(10V/Div)
VIN = 12V, VCC = 5V, VOUT = 1.2V, No Load
Time (1ms/Div)
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10
5
VCC (V)
EN
(5V/Div)
PGOOD
(10V/Div)
2.5
VCC (V)
VIN = 12V, VCC = 5V, VOUT = 1.2V, Load = 100mA
Time (5ms/Div)
is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Power On from VCC
VCC
(5V/Div)
Power Off from VCC
VCC
(5V/Div)
VOUT
VOUT
(500mV/Div)
(500mV/Div)
PHASE
(10V/Div)
PGOOD
(10V/Div)
PHASE
(10V/Div)
PGOOD
(10V/Div)
VIN = 12V, VOUT = 1.2V, No Load
Time (1ms/Div)
Time (5ms/Div)
Load Transient Response
Load Transient Response
ILoad
(10A/Div)
ILoad
(10A/Div)
VIN = 12V, VCC = 5V
VOUT
VOUT
(30mV/Div)
VIN = 12V, VCC = 5V
(30mV/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
VOUT = 1.2V, Load = 0.1 to 10A
Time (20µs/Div)
OVP
UVP
PGOOD
(10V/Div)
FB
(500mV/Div)
(500mV/Div)
VOUT
PHASE
(10V/Div)
VIN = 12V, VCC = 5V, VOUT = 1.2V, No Load
Time (50µs/Div)
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DS8129A-01
VOUT = 1.2V, Load = 10 to 0.1A
Time (20µs/Div)
PGOOD
(10V/Div)
PHASE
(10V/Div)
LGATE
(10V/Div)
VIN = 12V, VOUT = 1.2V, Load = 100mA
October
2015
LGATE
(10V/Div)
VIN = 12V, VCC = 5V, VOUT = 1.2V
Time (20µs/Div)
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11
RT8129A
OCP
VIN = 12V, VCC = 5V,
VOUT = 1.2V,
ROCSET = 13k,
ILoad
(10A/Div)
VOUT
(500mV/Div)
PHASE
(10V/Div)
LGATE
(10V/Div)
RDS,ON(VGS=4.5V) = 7.4m
Time (50µs/Div)
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is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Application Information
The RT8129A is a single-phase synchronous buck
current is also reduced, and eventually comes to the
PWM controller with integrated drivers which is
optimized for high performance graphic microprocessor
and computer applications. A COT (Constant-On-Time)
PWM controller and two MOSFET drivers with internal
bootstrap diodes are integrated so that the external
circuit is easily designed and the component count is
point that its valley touches zero current, which is the
boundary between continuous conduction and
discontinuous conduction modes. By emulating the
behavior of diodes, the low-side MOSFET allows only
partial of negative current when the inductor
freewheeling current reach negative level. As the load
reduced.
current is further decreased, it takes longer and longer
to discharge the output capacitor to the level that
requires the next “ON” cycle. In reverse, when the
output current increases from light load to heavy load,
the switching frequency increases to the preset value
as the inductor current reaches the continuous
condition.
The topology solves the poor load transient timing
problems of fixed-frequency current-mode PWM and
avoids the problems caused by widely varying
switching frequencies in conventional constant-on-time
and constant off-time PWM schemes.
RT8129A also features complete fault protection
functions including OVP, UVP and Current Limit.
PWM Operation
The switching waveforms may appear noisy and
asynchronous
when
light
loading
causes
diode-emulation operation, but this is a normal
The RT8129A integrates a Constant-On-Time PWM
controller, and the controller provides the PWM signal
which relies on the FB voltage comparing with internal
reference voltage as shown in Figure 1. Referring to
the function block diagram of TON generator, the
synchronous UGATE driver will be turned on at the
operating condition that results in high light-load
efficiency. Trade-offs in DEM noise vs. light-load
beginning of each cycle. After the internal one-shot
timer expires, the UGATE driver will be turned off. The
pulse width of this one shot is determined by the
converter's input voltage and the output voltage to keep
the frequency fairly constant over the input voltage
range. Another one-shot sets a minimum off-time.
resistance remains fixed) and less output voltage ripple.
The disadvantages for using higher inductor values
include larger physical size and degrade load-transient
response (especially at low input-voltage levels).
efficiency is made by varying the inductor value.
Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in
higher full-load efficiency (assuming that the coil
Enable and Disable
The EN pin allows for power sequencing between the
controller bias voltage and another voltage rail. The
VFB
VPEAK
VFB
VVALLEY
RT8129A remains in shutdown if the EN pin is lower
than 800mV. When EN pin rises above the 2V, the
RT8129A will begin a new initialization and soft-start
cycle.
VREF
t
tON
Figure 1. Constant On-Time PWM Control
Diode-Emulation Mode
In diode-emulation mode, the RT8129A automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. As the output current
decreases from heavy-load condition, the inductor
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DS8129A-01
October
2015
Power-On Reset (POR), UVLO
Power-on reset (POR) occurs when VCC rises above
to approximately 4.4V (typical), the RT8129A will reset
the fault latch and preparing the PWM for operation.
Below 4V (typical), the VCC under voltage-lockout
(UVLO) circuitry inhibits switching by keeping UGATE
and LGATE low.
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RT8129A
VIN Detection
Power-Good Output (PGOOD)
When VCC exceeds its POR rising threshold, LGATE
will be forced low UGATE and UGATE will output
The power good output is an open drain architecture,
and it requires a pull-up resistor. During soft-start,
continuous pulses (~25kHz, 100ns), for input voltage
VIN detection. If the PHASE pin voltage exceeds 1V for
3 consecutive cycles when the UGATE is turned on,
VIN is recognized as ready. The controller will initiate
soft-start operation.
PGOOD is actively held low and is allowed to transition
high after soft start is completed. In addition, if the FB
pin voltage is higher than 110% of VREF or lower than
90% of VREF, PGOOD will go low immediately.
Soft-Start
The RT8129A provides an internal soft-start function.
The RT8129A provides cycle-by-cycle current limit
control by detecting the PHASE voltage drop across
The soft-start function is used to prevent large inrush
current and output voltage overshoot while the
the low-side MOSFET when it is turned on. The current
limit circuit employs a unique “valley” current sensing
converter is being powered-up. The soft-start function
automatically begins after the chip is enabled.
algorithm. If the magnitude of the current sense signal
at PHASE is above the current limit threshold, the
PWM is not allowed to initiate a new cycle.
When soft-start process starts, an internal current
source charges the internal soft-start capacitor such
that the internal soft-start voltage ramps up uniformly.
The FB voltage will track the internal soft-start voltage
during the soft-start interval. The PWM pulse width
increases gradually to limit the input current. After the
internal soft-start voltage exceeds the reference
voltage, the FB voltage no longer tracks the soft-start
voltage but rather follows the reference voltage.
Therefore, both the duty cycle of the UGATE and the
input current are limited during the soft-start interval. If
the protection is not triggered during soft-start process,
the soft-start process is finished until the signal Internal
SSOK goes high, Figure 2 shows the internal soft-start
sequence.
VCC POR
Threshold
VCC
EN
Current Limit
In an over-current condition, the current to the load
exceeds the average output inductor current. Thus, the
output voltage falls and eventually crosses the
under-voltage
shutdown.
2V
Internal
SS
threshold,
inducing
IC
Current Limit Threshold Setting
Current limit threshold is externally programmed by
adding a resistor (ROCSET) between LGATE and GND.
Once VCC exceeds the POR threshold, an internal
current source IOCSET flows through ROCSET. The
voltage across ROCSET is stored as the over current
protection threshold VOCSET. After that, the current
source is switched off.
ROCSET can be determined using the following
equation :
0.8V
FB
protection
ROCSET 
IVALLEY  RLGDS(ON) 
IOCSET
Where IVALLEY represents the desired inductor limit
current (valley inductor current) and IOCSET is current
limit setting current.
Internal
SSOK
PGOOD
UGATE
LGATE
POR
VIN Detection
OCP
Programming
Soft Start
Normal operation
Off
Diode Emulation with
LGATE turns on to
Ultrasonic Mode
discharge output voltage
(Load Current Dependent) if the phase voltage >1V
If ROCSET is not present, there is no current path for
IOCSET to build the OCP threshold. In this situation, the
OCP threshold is internally preset to 640mV. The
recommended range for ROCSET is 5k to 60k which
means the threshold voltage range is 50mV to 600mV.
Figure 2. Soft-Start Sequence
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is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
Output Over-Voltage Protection (OVP)
VOUT
The voltage on the FB pin is monitored for over-voltage
protection. When the FB voltage exceeds than 1V
(typically 125% x VREF), over voltage protection is
triggered and low-side MOSFET is forced on. This
activates low-side MOSFET to discharge the output
capacitor. The RT8129A is latched once OVP is
triggered and can only be released by VCC power-on
reset. A 5s delay is used in OVP detection circuit to
prevent false trigger.
Output Under-Voltage Protection (UVP)
The voltage on the FB pin is monitored for under
voltage protection. When the FB voltage is less than
0.6V (typically 75% x VREF) during normal operation,
under voltage protection is triggered and then UGATE
and LGATE gate drivers are forced low. The RT8129A
is latched once UVP is triggered and can only be
released by VCC or EN power-on reset. There is a 3s
RFB1
FB
RFB2
Figure 4. Setting VOUT with a Resistive Voltage Divider
MOSFET Gate Driver
The RT8129A integrates high current gate drivers for
the MOSFET to obtain high efficiency power
conversion in synchronous buck topology. A dead time
is used to prevent the crossover conduction for high
side and low side MOSFET. Because both the two gate
signals are off during the dead time, the inductor
current freewheels through the body diode of the low
side MOSFET. The freewheeling current and the
forward voltage of the body diode contribute to the
power loss. The RT8129A employs adaptive dead time
The output voltage waveform is shown as Figure 3,
control scheme to ensure safe operation without
sacrificing efficiency. Furthermore, elaborate logic
circuit is implemented to prevent short through
conduction. For high output current applications, two or
more power MOSFET are usually paralleled to reduce
RDS(ON).
which can be adjusted from 0.8V to 3.3V by setting the
feedback resistors, RFB1 and RFB2 (see Figure 4).
The gate driver needs to provide more current to switch
on/off these paralleled MOSFET. The gate driver with
Choose RFB2 to be approximately 10k and solve for
RFB1 using the equation below :
lower source/sink current capability result in longer
rising/ falling time in gate signals, and therefore higher


R
VOUT  VREF   1  FB1 
R

FB2 
switching loss. The RT8129A embeds high current gate
drivers to obtain high efficiency power conversion.
where the VREF is 0.8V (typical).
Inductor Selection
delay built into the UVP circuit to prevent false
transitions. During soft-start, the UVP blanking time is
equal to PGOOD blanking time.
Output Voltage Setting
Inductor plays an importance role in step-down
converters because the energy from the input power
VOUT
ΔVOUT
VOUT
VVALLEY
t
tON
Figure 3. Output Voltage Waveform
rail is stored in it and then released to the load. From
the viewpoint of efficiency, the dc resistance (DCR) of
inductor should be as small as possible to minimize the
copper loss. In addition, because inductor cost most of
the board space, its size is also important. Low profile
inductors can save board space especially when the
height has limitation. However, low DCR and low profile
inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which means the lower power loss. However,
the inductor current rising time increases with
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8129A-01
October
2015
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15
RT8129A
inductance value. This means the transient response
will be slower. Therefore, the inductor design is a
trade-off between performance, size and cost.
MOSFET Selection
In general, inductance is designed such that the ripple
current ranges between 20% ~ 40% of full load current.
The inductance can be calculated using the following
equation.
For low-voltage high-current applications, the duty
cycle of the high-side MOSFET is small. Therefore, the
switching loss of the high-side MOSFET is of concern.
Power MOSFETs with lower total gate charge are
preferred in such kind of application.
LMIN 
VIN  VOUT
V
 OUT
FSW  k  IOUT_rated
VIN
where k is the ratio between inductor ripple current and
rated output current.
Input Capacitor Selection
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFET.
However, the small duty cycle means the low-side
MOSFET is on for most of the switching cycle.
Therefore, the conduction loss tends to dominate the
total power loss of the converter. To improve the overall
efficiency, the MOSFET with low RDS(ON) are preferred
Voltage rating and current rating are the key
parameters in selecting input capacitor. Generally,
input capacitor has a voltage rating 1.5 times greater
than the maximum input voltage is a conservatively
safe design.
in the circuit design. In some cases, more than one
MOSFET are connected in parallel to further decrease
the on-state resistance. However, this depends on the
low-side MOSFET driver capability and the budget.
The input capacitor is used to supply the input RMS
For continuous operation, do not exceed absolute
current, which can be approximately calculated using
the following equation.
maximum junction temperature. The maximum power
Thermal Considerations
dissipation depends on the thermal resistance of the

VOUT 
V
IRMS  IOUT 
  1  OUT 
VIN 
VIN 
IC package, PCB layout, rate of surrounding airflow,
and
difference
between
junction
and
ambient
The next step is to select proper capacitor for RMS
current rating. Use more than one capacitor with low
equivalent series resistance (ESR) in parallel to form a
capacitor bank is a good design. Besides, placing
ceramic capacitor close to the drain of the high-side
temperature. The maximum power dissipation can be
MOSFET is helpful in reducing the input voltage ripple
at heavy load.
TA is the ambient temperature, and JA is the junction
Output Capacitor Selection
For recommended operating condition specifications,
The output filter capacitor must have ESR low enough
to meet output ripple and load transient requirement,
yet have high enough ESR to satisfy stability
requirements. Also, the capacitance must be high
enough to absorb the inductor energy going from a full
load to no load condition without triggering the OVP
circuit. Organic semiconductor capacitor(s) or special
polymer capacitor(s) are recommended.
the maximum junction temperature is 125C. The
calculated by the following formula :
PD(MAX) = (TJ(MAX)  TA) / JA
where TJ(MAX) is the maximum junction temperature,
to ambient thermal resistance.
junction to ambient thermal resistance, JA, is layout
dependent. For WDFN-10L 3x3 package, the thermal
resistance, JA, is 30.5C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum
power dissipation at TA = 25C can be calculated by
the following formula :
PD(MAX) = (125C  25C) / (30.5C/W) = 3.27W for
WDFN-10L 3x3 package
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is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015
RT8129A
The maximum power dissipation depends on the
Layout Consideration
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 5
Layout is very important in high frequency switching
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
3.5
converter design. If designed improperly, the PCB
could radiate excessive noise and contribute to the
converter instability. Certain points must be considered
before starting a layout for RT8129A.
Four-Layer PCB

3.0
Connect RC low pass filter as close as possible VCC
pin.
2.5

Keep current protection setting network as close as
2.0
possible to the IC. Routing of the network should
1.5
avoid coupling to high-voltage switching node.
1.0

Connections from the drivers to the respective gate
of the high-side or the low-side MOSFET should be
0.5
as short as possible to reduce stray inductance.
0.0
0
25
50
75
100
125

All sensitive analog traces and components such as
Ambient Temperature (°C)
FB, EN, PGOOD, and VCC should be placed away
Figure 5. Derating Curve of Maximum Power
from high-voltage switching nodes such as PHASE,
Dissipation
LGATE, UGATE, or BOOT nodes to avoid coupling.
Use internal layer(s) as ground plane(s) and shield
the
feedback
trace
from
power
traces
and
components.

Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling
(including
the
chip
power
ground
connections). Power components should be placed
to minimize loops and reduce losses.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8129A-01
October
2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT8129A
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8129A-01
October
2015