RT8202L/M Single Synchronous Buck Controller General Description Features The RT8202L/M PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. z Ultra-High Efficiency z Resistor Programmable Current Limit by Low Side RDS(ON) Sense (Lossless Limit) 4700ppm/°°C RDS(ON) Current Sensing Quick Load Step Response within 100ns 1% VFB Accuracy over Line and Load Adjustable 0.75V to 3.3V Output Voltage Range 3V to 26V Battery Input Voltage Range Resistor Programmable Frequency Integrated Bootstrap Switch Over Voltage Protection Under Voltage Protection Voltage Ramp Soft-Start Built In Soft Discharge Output Power Good Indicator RoHS Compliant and 100% Halogen Free The constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. z z z z z z z The RT8202L/M achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs. The RT8202L is available in a WQFN-16L 4x4 package and the RT8202M is available in a WQFN-16L 3x3 package. Ordering Information RT8202L/M z z z z z z Applications z Notebook Computers CPU Core Supply Chipset/RAM Supply as Low as 0.75V Package Type QW : WQFN-16L 4x4 (W-Type) QW : WQFN-16L 3x3 (W-Type) z Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Pin Configurations RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. NC BOOT 14 13 VOUT 1 12 UGATE VDD 2 11 PHASE FB 3 10 OC PGOOD 4 9 VDDP GND 17 5 6 7 8 PGND ` 15 LGATE Richtek products are : 16 NC Note : EN/DEM L : WQFN-16L 4x4 M : WQFN-16L 3x3 TON (TOP VIEW) GND z WQFN-16L 4x4 (RT8202L)/ WQFN-16L 3x3 (RT8202M) DS8202L/M-04 April 2011 www.richtek.com 1 RT8202L/M Marking Information RT8202LGQW RT8202MGQW EK= : Product Code JJ= : Product Code YMDNN : Date Code EK=YM DNN YMDNN : Date Code JJ=YM DNN RT8202LZQW RT8202MZQW EK : Product Code EK YM DNN JJ : Product Code YMDNN : Date Code YMDNN : Date Code JJ YM DNN Typical Application Circuit VIN 3V to 26V RTON C4 RT8202L/M VDDP 5V 16 TON 9 VDDP R2 C1 R1 2 VDD C2 BOOT 13 R3 UGATE 12 R4 PHASE 11 LGATE 8 PGOOD 4 PGOOD OC 10 CCM/DEM 15 EN/DEM FB 3 Q1 Q2 RILIM L1 R5* C5* C8 R6 C6* C7* R7 6 , 17 (Exposed Pad) GND 7 PGND VOUT C3 VOUT 1 * Optional www.richtek.com 2 DS8202L/M-04 April 2011 RT8202L/M Function Block Diagram TRIG On-time Compute 1-SHOT VOUT TON SS (Internal) + + GM - - - R Comp S + BOOT Q PWM DRV UGATE PHASE Min. TOFF Q TRIG + 115% VREF FB Latch S1 Q UV Latch S1 Q DRV PGND - SS Ramp + 20µA Thermal Shutdown + GND OC - EN/DEM DS8202L/M-04 April 2011 LGATE Diode Emulation - 90% VREF VDD VDDP 1-SHOT + 70% VREF OV PGOOD www.richtek.com 3 RT8202L/M Functional Pin Description Pin No. Pin Name Pin Function Output Voltage Sense Pin. Connect this pin to the output of PWM converter. VOUT is also for the output soft discharge when shutdown. Analog Supply Voltage Input for Internal Analog Integrated Circuit. Bypass this pin to GND with a 1μF ceramic capacitor. 1 VOUT 2 VDD 3 FB Feedback Input of PWM Controller. Connect FB to a resistor voltage divider from VOUT to GND to adjust the output voltage from 0.75V to 3.3V. 4 PGOOD Power Good Signal Open-Drain Output of PWM Controller. This pin will be pulled high when the output voltage is within the target range. NC No Internal Connection. 5, 14 6, GND 17 (Exposed Pad) 7 PGND 8 LGATE 9 VDDP 10 OC 11 PHASE 12 UGATE 13 BOOT 15 EN/DEM 16 TON www.richtek.com 4 Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Power Ground. Low Side N-MOSFET Gate-Drive Output for PWM. This pin swings between PGND to VDDP. Gate Driver Supply for External MOSFETs. Bypass this pin to PGND with a 1μF ceramic capacitor. PWM Current Limit Setting and Sense. Connect a resistor between OC to PHASE for current limit setting. Inductor Connection. This pin is not only the zero-current-sense input for the PWM converter, but also the UGATE high side gate driver return. High Side N-MOSFET Floating Gate-Driver Output for PWM controller. This pin swings between PHASE and BOOT. Boost Capacitor connection for PWM Controller. Connect an external ceramic capacitor from this pin to PHASE. PWM Enable and Operation Mode Selection Input. Connect this pin to VDD for diode-emulation mode, connect this pin to GND for shutdown mode and floating the pin for CCM mode. On Time/Frequency Adjustment Pin. Connect this pin to VIN through a resistor. TON is an input of the PWM controller. DS8202L/M-04 April 2011 RT8202L/M Absolute Maximum Ratings (Note 1) Input Voltage, TON to GND ------------------------------------------------------------------------------------------------ –0.3V to 32V z BOOT to PHASE ------------------------------------------------------------------------------------------------------------ –0.3V to 6V z UGATE to PHASE DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V z LGATEx to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V z PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 32V < 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V z PGND to GND ---------------------------------------------------------------------------------------------------------------- –0.3V to 0.3V z VDD, VDDP, VOUT, EN/DEM, FB, PGOOD to GND ---------------------------------------------------------------- –0.3V to 6V z OC to GND -------------------------------------------------------------------------------------------------------------------- –0.3V to 28V z Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 -------------------------------------------------------------------------------------------------------------- 1.471W WQFN-16L 4x4 -------------------------------------------------------------------------------------------------------------- 1.852W z Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA --------------------------------------------------------------------------------------------------------- 68°C/W WQFN-16L 3x3, θJC -------------------------------------------------------------------------------------------------------- 7.5°C/W WQFN-16L 4x4, θJA --------------------------------------------------------------------------------------------------------- 54°C/W WQFN-16L 4x4, θJC -------------------------------------------------------------------------------------------------------- 7°C/W z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C z Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C z Storage Temperature Range ---------------------------------------------------------------------------------------------- –65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 200V z Recommended Operating Conditions z z z z (Note 4) Input Voltage, VIN ------------------------------------------------------------------------------------------------------------ 3V to 26V Supply Voltage, VDD, VDDP ------------------------------------------------------------------------------------------------ 4.5V to 5.5V Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C DS8202L/M-04 April 2011 www.richtek.com 5 RT8202L/M Electrical Characteristics (VDD = VDDP = 5V, VIN = 15V, VEN/DEM = VDD, RTON = 1MΩ, TA = 25°C, unless otherwise specified) Parameter Quiescent Current Symbol IQ Test Conditions IVDD + IVDDP, VFB = 0.8V, forced above the regulation point Min Typ Max Unit -- -- 1250 μA -- 15 -- IVDD + IVDDP -- 1 10 ITON -- 1 5 −10 −1 -- μA 0.742 0.75 0.758 V −1 0.1 1 μA 0.75 -- 3.3 V 267 334 401 ns 250 400 550 ns EN/DEM = GND, V OUT = 0.5V -- 20 -- Ω LGATE = High 18 20 22 μA On the basis of 25°C -- 4700 -- ppm/°C GND to OC −10 -- 10 mV PHASE to GND, EN/DEM = 5V −10 -- 5 mV GND − PHASE, RILIM = 10kΩ 170 200 230 mV UVP detect, FB falling edge 60 70 80 % OVP detect, FB rising edge 110 115 120 % -- 20 -- μs 3.7 3.9 4.1 V -- 150 -- mV 1.5 -- ms -- 4.5 -- ms TON Operating Current Shutdown Current ISHDN EN/DEM = 0V FB Reference Voltage VFB FB Input Bias Current VFB = 0.75V Output Voltage Range VOUT On-Time tON Minimum Off-Time tOFF VOUT Shutdown Discharge Resistance Current Sensing Current Limit Source Current Current Limiter Temperature TC ICS Coefficient Current Comparator Offset Voltage Zero Crossing Threshold Voltage Fault Protection Current Limit Sense Voltage Output Under Voltage VUVP Threshold Over Voltage Protection VOVP Threshold Over Voltage Fault Delay Under Voltage Lockout Threshold Under Voltage Lockout Hysteresis Soft-Start Ramp Time VDD = 4.5V to 5.5V VUVLO VIN = 15V, VOUT = 1.25V FB forced above over voltage threshold Falling edge, PWM disabled below this level ΔVUVLO tSS Under Voltage Blank Time From EN high to internal VREF reaches 0.71V (0Æ95%) From EN signal going high μA Thermal Shutdown Thermal Shutdown Hysteresis Driver On-Resistance T SD -- 155 ΔTSD -- 10 -- °C UGATE Driver Source RUGATEsr -- 2 -- Ω UGATE Driver Sink RUGATEsk -- 1.5 -- Ω UGATE, High State, BOOT to PHASE forced to 5V UGATE, Low State, BOOT to PHASE forced to 5V °C To be continued www.richtek.com 6 DS8202L/M-04 April 2011 RT8202L/M Parameter LGATE Driver Source LGATE Driver Sink Internal BOOT Charging Switch On-Resistance Dead Time Symbol Test Conditions RLGATEsr LGATE, High State RLGATEsk LGATE, Low State Min --- Typ 1.5 0.7 Max --- Unit Ω Ω VDDP to BOOT, 10mA -- -- 90 Ω LGATE Rising (VPHASE = 1.5V) -- 30 -- UGATE Rising -- 30 -- EN/DEM Low -- -- 0.8 EN/DEM High 2.9 -- -- EN/DEM Float -- 2 -- EN/DEM = VDD -- 1 10 −10 1 -- 87 90 93 % -- 2.5 -- μs -- -- 0.4 V -- -- 1 μA ns Logic I/O Logic Input Voltage Logic Input Current EN/DEM = 0 PGOOD (upper side threshold decide by OV threshold) Measured at FB, with respect to Trip Threshold (falling) reference, Hysteresis = 3% Falling edge, FB forced below PGOOD Fault Propagation Delay trip threshold Output Low Voltage ISINK = 1mA Leakage Current High state, forced to 5V V μA Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The case measurement position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8202L/M-04 April 2011 www.richtek.com 7 RT8202L/M Typical Operating Characteristics Switching Frequency vs. Output Current Efficiency vs. Output Current 100 DEM 80 Efficiency (%) Switching Frequency (kHz)1 90 70 PWM 60 50 40 30 20 10 0 0.001 VIN = 8V, VOUT = 1.05V 0.01 0.1 1 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 PWM DEM VIN = 8V, VOUT = 1.05V 0.01 Output Current (A) Efficiency (%) Switching Frequency (kHz)1 90 DEM 70 PWM 60 50 40 30 20 10 0 0.001 VIN = 12V, VOUT = 1.05V 0.01 0.1 1 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 DEM VIN = 12V, VOUT = 1.05V 0.01 Efficiency (%) Switching Frequency (kHz)1 90 DEM PWM 60 50 40 30 20 0 0.001 VIN = 20V, VOUT = 1.05V 0.01 0.1 1 Output Current (A) www.richtek.com 8 0.1 1 10 100 Switching Frequency vs. Output Current Efficiency vs. Output Current 10 100 Output Current (A) 100 70 10 PWM Output Current (A) 80 1 Switching Frequency vs. Output Current Efficiency vs. Output Current 100 80 0.1 Output Current (A) 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 PWM DEM VIN = 20V, VOUT = 1.05V 0.01 0.1 1 10 100 Output Current (A) DS8202L/M-04 April 2011 RT8202L/M Standby Current vs. Input voltage Shutdown Current vs. Input voltage 10 Shutdown Current (μA)1 Standby Current (μA)1 520 500 480 460 440 420 9 8 7 6 5 4 3 2 1 VEN/DEM = 5V, No Load 400 7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 Input Voltage (V) Input Voltage (V) Power On from EN_PWM Mode Power On from EN_DEM Mode VOUT (1V/Div) VOUT (1V/Div) VPHASE (10V/Div) VPHASE (10V/Div) VEN/DEM (2V/Div) VEN/DEM (5V/Div) VPGOOD (5V/Div) EN/DEM = GND, No Load 0 VIN = 12V, EN/DEM = Floating, No Load VPGOOD (5V/Div) 25 VIN = 12V, VEN/DEM = 5V, No Load Time (1ms/Div) Time (1ms/Div) Power Off from EN Load Transient Response VOUT (50mV/Div) VOUT (1V/Div) IL (20A/Div) VEN/DEM (2V/Div) VUGATE (20V/Div) VUGATE (20V/Div) VLGATE (5V/Div) VLGATE (5V/Div) VIN = 12V, EN/DEM = Floating, No Load Time (10ms/Div) DS8202L/M-04 April 2011 VIN = 12V, EN/DEM = Floating, IOUT = 0A to20A Time (40μs/Div) www.richtek.com 9 RT8202L/M Over Voltage Protection Under Voltage Protection VOUT (1V/Div) VOUT (1V/Div) VPGOOD (5V/Div) VPGOOD (5V/Div) VUGATE (20V/Div) VLGATE (5V/Div) VIN = 12V, VEN/DEM = 5V, No Load Time (40μs/Div) www.richtek.com 10 VLGATE (5V/Div) VIN = 12V, EN/DEM = Floating, No Load Time (40μs/Div) DS8202L/M-04 April 2011 RT8202L/M Applications Information The RT8202L/M PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. RichTek's Mach ResponseTM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed frequency current mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant- off-time PWM schemes. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. PWM Operation The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. Referring to the function diagrams of the RT8202L/M, the synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.). On-Time Control (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. DS8202L/M-04 April 2011 tON = 3.85p x RTON x VOUT (VIN − 0.5) And then the switching frequency is : Frequency = VOUT (VIN x t ON ) RTON is a resistor connected from the input supply (VIN) to the TON pin. Mode Selection (EN/DEM) Operation The EN/DEM pin enables the supply. When EN/DEM is tied to VDD, the controller is enabled and operates in diode-emulation mode. When the EN/DEM pin is floating, the RT8202L/M will operate in forced-CCM mode. Diode-Emulation Mode (EN/DEM = High) In diode-emulation mode, the RT8202L/M automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increasing VOUT ripple or load regulation. As the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point when its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current when the inductor freewheeling current becomes negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light load operation can be calculated as follows (Figure 1) : (VIN − VOUT ) x tON 2L where tON is the On-time. ILOAD ≈ www.richtek.com 11 RT8202L/M IL IL Slope = (VIN -VOUT) / L IL, PEAK IL, PEAK ILOAD ILOAD = IL, PEAK / 2 0 tON t ILIM t 0 Figure 1. Boundary Condition of CCM/DEM Figure 2. Valley Current Limit The switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, however, this is a normal operating condition that results in high light load efficiency. Trade-offs in DEM noise vs. light load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load transient response (especially at low input voltage levels). Current sensing of the RT8202L/M can be accomplished in two ways. Users can either use a current sense resistor or the on-state of the low side MOSFET (RDS(ON)). For resistor sensing, a sense resistor is placed between the source of low side MOSFET and PGND (Figure 3(a)). RDS(ON) sensing is more efficient and less expensive (Figure 3(b)). However, there is a compromise between current limit accuracy and sense resistor power dissipation. Forced-CCM Mode (EN/DEM = floating) The low noise, forced-CCM mode (EN/DEM = floating) disables the zero crossing comparator, which controls the low side switch on-time. This causes the low side gate-drive waveform to become the complement of the high side gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio VOUT/VIN. The benefit of forcedCCM mode is to keep the switching frequency fairly constant, but it comes at a cost. The no load battery current can be as high as 10mA to 40mA, depending on the external MOSFETs. Current Limit Setting (OCP) The RT8202L/M has a cycle-by-cycle current limiting control. The current limit circuit employs a unique“valley” current sensing algorithm. If the magnitude of the current sense signal at OC is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure 2). www.richtek.com 12 PHASE LGATE OC RILIM (a) PHASE LGATE OC RILIM (b) Figure 3. Current Sense Methods In both cases, the RILIM resistor between the OC pin and PHASE pin sets the over current threshold. This resistor RILIM is connected to a 20μA current source within the RT8202L/M which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM DS8202L/M-04 April 2011 RT8202L/M resistor, positive current limit will activate. The high side MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. Choose a current limit resistor by the following equation : I x RSENSE RILIM = LIMIT 20μA Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current sense signal seen by OC and PGND. Mount the IC close to the low-side MOSFET and sense resistor with short, direct traces, making a Kelvin sense connection to the sense resistor. MOSFET Gate Driver (UGATE, LGATE) The high side driver is designed to drive high current, low RDS(ON) N-MOSFET(s). When configured as a floating driver, 5V bias voltage is delivered from the VDDP supply. The average drive current is proportional to the gate charge at VGS = 5V times the switching frequency. The instantaneous drive current is supplied by the flying capacitor between the BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low RDS(ON) N-MOSFET(s). The internal pull down transistor that drives LGATE low is robust, with a 0.7Ω typical on resistance. A 5V bias voltage is delivered form VDDP supply. The instantaneous drive current is supplied by the flying capacitor between VDDP and PGND. For high current applications, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time (Figure 4). DS8202L/M-04 April 2011 +5V BOOT VIN R UGATE PHASE Figure 4. Reducing the UGATE Rise Time Power Good Output (PGOOD) The power good output is an open-drain output and requires a pull up resistor. When the output voltage is 15% above or 10% below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. In soft-start, PGOOD is actively held low and is allowed to transition high until soft-start is over and the output reaches 93% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false transition. POR, UVLO and Soft-Start Power on reset (POR) occurs when VDD rises above to approximately 4.1V. The RT8202L/M will reset the fault latch and prepare the PWM for operation. At below 3.7V (min), the VDD undervoltage lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. A built in soft-start is used to prevent surge current from power supply input after EN/DEM is enabled. It clamps the ramping of internal reference voltage which is compared with the FB signal. The typical soft-start duration is 1.5ms. Output Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage protection. When the output voltage exceeds 15% of its set voltage threshold, over voltage protection is triggered and the low side MOSFET is latched on. This activates the low side MOSFET to discharge the output capacitor. The RT8202L/M is latched once OVP is triggered and can only be released by VDD or EN/DEM power on reset. There is a 20μs delay built into the over voltage protection circuit to prevent false transitions. www.richtek.com 13 RT8202L/M Output Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 70% of its set voltage threshold, under voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. In order to remove the residual charge on the output capacitor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is 2.5μs delay built into the under voltage protection circuit to prevent false transitions. During soft-start, the UVP will be blanked around 4.5ms. Output Voltage Setting (FB) The output voltage can be adjusted from 0.75V to 3.3V by setting the feedback resistors R6 and R7 (Figure 5). Choose R7 to be approximately 10kΩ, and solve for R6 using the equation : R6 ⎞ ⎛ VOUT = VFB x ⎜ 1 + ⎟ R7 ⎠ ⎝ where VFB is 0.75V. VIN VOUT UGATE VOUT R6 FB R7 GND Figure 5. Setting The Output Voltage Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : t x (VIN − VOUT ) L = ON LIR x ILOAD(MAX) Find a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must www.richtek.com 14 Output Capacitor Selection The output filter capacitor must have ESR low enough to meet output ripple and load transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : VP − P ESR ≤ ILOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an acceptable level of output voltage ripple : VP − P ESR ≤ LIR x ILOAD(MAX) Organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended. PHASE LGATE be large enough not to saturate at the peak inductor current (IPEAK) : ⎛ LIR ⎞ IPEAK = ILOAD(MAX) + ⎜ x ILOAD(MAX) ⎟ 2 ⎝ ⎠ Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : f 1 f= < SW 2 x π x ESR x COUT 4 Do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic and unstable operation. However, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VOUT or the FB divider close to the inductor. There are two related but distinct ways, double pulsing and feedback loop instability to identify the unstable operation. DS8202L/M-04 April 2011 RT8202L/M Loop instability can result in oscillation at the output after line or load perturbations and trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for WQFN-16L 3x3 package PD(MAX) = (125°C− 25°C) / (54°C/W) = 1.852W for WQFN-16L 4x4 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT8202L/M package, the derating curves in Figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 Double pulsing occurs due to noise on the output or because the ESR is too low such that there is not enough voltage ramp in the output voltage signal. This“fools” the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. The easiest method for stability checking is to apply a zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC probe. Do not allow more than one ringing cycle after the initial step response under shoot or over shoot. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8202L/M, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-16L 3x3 packages, the thermal resistance, θJA, is 68°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WQFN-16L 4x4 packages, the thermal resistance, θJA, is 54°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : DS8202L/M-04 April 2011 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Four-Layer PCB WQFN-16L 4x4 WQFN-16L 3x3 0 25 50 75 100 125 Ambient Temperature (°C) Figure 6. Derating Curve for the RT8202L/M Package Layout Consideration Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to converter instability. Certain points must be considered before starting a layout for the RT8202L/M. ` Connect RC low-pass filter from VDDP to VDD, 1μF and 20Ω are recommended. Place the filter capacitor close to the IC. ` Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high-voltage switching node. ` Connections from the drivers to the respective gate of the high side or low side MOSFET should be as short as possible to reduce stray inductance. www.richtek.com 15 RT8202L/M ` All sensitive analog traces and components such as VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and TON should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` Power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. www.richtek.com 16 DS8202L/M-04 April 2011 RT8202L/M Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package DS8202L/M-04 April 2011 www.richtek.com 17 RT8202L/M D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 D 3.950 4.050 0.156 0.159 D2 2.000 2.450 0.079 0.096 E 3.950 4.050 0.156 0.159 E2 2.000 2.450 0.079 0.096 e L 0.650 0.500 0.026 0.600 0.020 0.024 W-Type 16L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 18 DS8202L/M-04 April 2011