Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74HCT4094
CMOS IC
8-STAGE SHIFT&STORE BUS
REGISTER
„
DESCRIPTION
The U74HCT4094 consists of an 8-stage shift register and
8-stage D-type latch with 3-stage parallel outputs. Data is shifted
serially through the shift register on the positive going transition of
the clock input singal. The output of the last stage QS1 can be
used to cascade several devices.
The output of QS1 is transferred to a second output(QS2) on
the following negative transition of the clock input singal. The data
of each stage of the shift register is provided with a latch which
latches data on the negative going transition of the Strobe input
signal. When the strobe input is held high, data propagates
through the latch to a 3-state output buffer.
The buffer is enabled when Output Enable input is taken high.
„
FEATURES
* Operate from 4.5V to 5.5V
* Low Input Current: 0.1µA
* High Noise Immunity Characteristic of CMOS Devices
* Inputs are TTL Voltage Compatible.
„
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
U74HCT4094L-P16-R
U74HCT4094G-P16-R
U74HCT4094L-P16-T
U74HCT4094G-P16-T
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Copyright © 2011 Unisonic Technologies Co., Ltd
Package
Packing
TSSOP-16
TSSOP-16
Tape Reel
Tube
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U74HCT4094
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PIN CONFIGURATION
„
FUNCTION TABLE
CMOS IC
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
OE
STR
D
QP0
QPn
QS1
QS2
↑
L
X
X
Z
Z
Q’6
NC
↓
L
X
X
Z
Z
NC
QP7
↑
H
L
X
NC
NC
Q’6
NC
↑
H
H
L
L
QPn-1
Q’6
NC
↑
H
H
H
H
QPn-1
Q’6
NC
↓
H
H
H
NC
NC
NC
QP7
Note:H : HIGH voltage level; L : LOW voltage level.
X : Don’t care.High impedance OFF-state.
NC: No change.
↑ : Low-to-High CP transition.
↓ : High-to-Low CP transition.
Q’6: the information in the seventh register stage is transferred to the 8th register stage and QSn output at the
positive clock edge
„
LOGIC SYMBOL
2
3
1
CP
STR
D
QS1
9
QS2
10
QP0
4
QP1
5
QP2
6
QP3
7
QP4
14
QP5
13
QP6
12
QP7
11
OE
15
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U74HCT4094
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LOGIC DIAGRAM
„
TIMING DIAGRAM
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CMOS IC
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U74HCT4094
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CMOS IC
ABSOLUTE MAXIMUM RATING
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
SYMBOL
VCC
VIN
RATINGS
-0.5 ~ 7.0
-0.5 ~ VCC +1.5
VOUT
-0.5 ~ VCC +0.5
UNIT
V
V
V
VCC or GND Current
ICC
±50
Input Current
IIN
±20
Output Current
IOUT
±25
Storage Temperature
TSTG
-65 ~ + 150
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise or Fall Times
„
mA
mA
mA
℃
ELECTRICAL
SYMBOL
VCC
VIN
VOUT
TA
tR, tF
TEST CONDITIONS
Operating
MIN
4.5
0
0
-40
VCC=4.5V to 5.5V
TYP
MAX
5.5
VCC
VCC
+125
500
UNIT
V
V
V
℃
ns
CHARACTERISTICS(TA=25℃)
PARAMETER
High-level input voltage
Low-lever output voltage
SYMBOL
VIH
VIL
High-Level Output Voltage,
VOH
Low-Level Output Voltage,
VOL
Input Leakage Current
Output OFF -state current
Quiescent Supply Current
II(LEAK)
IOZ
Icc
Additional Quiescent Supply Current
△ICC
TEST CONDITIONS
VCC=4.5V to 5.5V
VCC=4.5V to 5.5V
VCC=4.5V, IOH=-20μA
VCC=4.5V, IOH=-4mA
VCC=4.5V, IOL=20μA
VCC=4.5V, IOH=4mA
VCC=5.5V,VIN= 3V or GND
VCC=5.5V,VOUT=VCC or GND
VCC=5.5V, VIN=3V or GND, IOUT=0
STR
OE
VIN=VCC-2.1V,
other inputs at VCC or GND CP
D
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MIN TYP MAX UNIT
2.0 1.6
V
1.2 0.8
V
4.4
V
3.98
V
0.1
V
0.26
V
±0.1
μA
±0.5
μA
4
μA
100 360
150 540
μA
150 540
40 144
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SWITCHING CHARACTERISTICS(TA=25℃,see TEST CIRCUIT AND WAVEFORMS)
PARAMETER
Propagation Delay from Input
(CP) to Output(QS1)
Propagation Delay from Input
(CP) to Output(QS2)
Propagation Delay from Input
(CP) to Output (QPn)
Propagation Delay from Input
(STR) to Output (QPn)
3-state Output Enable Time from
Input (OE) to Output(QPn)
3-State Output Disable Time from
Input (OE) to Output(QPn)
Output Transition Time(QSn、QPn)
Clock Pulse Width HIGH or LOW(CP)
Strobe Pulse Width HIGH(STR)
Set-up Time(D to CP)
Set-up Time(D to STR)
Hold Time(D to CP)
Hold Time(D to STR)
Maximum Clock Pulse Frequency
„
CMOS IC
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNIT
tPHL/tPLH
VCC=4.5V
23
39
ns
tPHL/tPLH
VCC=4.5V
21
36
ns
tPHL/tPLH
VCC=4.5V
25
43
ns
tPHL/tPLH
VCC=4.5V
22
39
ns
tPZH/tPZL
VCC=4.5V
20
35
ns
tPHZ/tPLZ
VCC=4.5V
21
35
ns
tTLH/ tTHL
tW
tW
tSU
tSU
tH
tH
f(MAX)
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
VCC=4.5V
7
7
5
4
9
0
-4
80
15
ns
ns
ns
ns
ns
ns
ns
MHz
16
16
10
20
4
0
30
OPERATING CHARACTERISTICS
PARAMETER
Power Dissipation Capacitance
SYMBOL
CPD
TEST CONDITIONS
No Load
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RATINGS
92
UNIT
pF
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CMOS IC
TEST CIRCUIT AND WAVEFORMS
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Note: CL =50pF, RL =1kΩ
VCC
Timing
Input
tW
50%
0V
tSU
th
VCC
VI
50%
50%
VCC
Data
Input
50%
0V
50%
0V
Pulse Width
Setup Time and Hold Time
VCC
OE
50%
tPZL
tPLZ
VCC
50%
0V
tPLH
VO
50%
0V
VCC
VI
50%
VO
50%
10%
tPHL
VOH
50%
VO
50%
VOL
Propagation Delay Times
VOL
tPHZ
tPZH
50%
90%
VOH
0V
Enable and Disable Times
Note: CL includes probe and jig capacitance.
PRR ≤10MHz, Zo = 50Ω, tR ≤6ns, tF ≤6ns.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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