INTEGRATED CIRCUITS 74LV4094 8-stage shift-and-store bus register Product specification 1998 Jun 23 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 FEATURES DESCRIPTION • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT4094. The 74LV4094 is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered 3-State outputs (QP0 to OP7). The parallel outputs may be connected directly to the common bus lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift register is transferred to the storage register when the strobe input (STR) is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094 devices. Data is available at QS1 on the positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at QS2 on the next negative going clock edge and is for cascading 74LV4094 devices when the clock rise time is slow. Tamb = 25°C • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Output capability: standard • ICC category: MSI Applications: • Serial-to-parallel data conversion • Remote control holding register QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns PARAMETER SYMBOL TYPICAL CL = 15 pF; VCC = 3.3 V tPHL/tPLH Propagation delay CP to QS1 CP to QS2 CP to QPn STR to QPn fMAX Maximum clock frequency CI Input capacitance CPD CONDITIONS Power dissipation capacitance per gate UNIT 14 13 18 17 VCC = 3.3 V VI = GND to VCCNO TAG ns 95 MHz 3.5 pF 83 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40°C to +125°C 74LV4094 N 74LV4094 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV4094 D 74LV4094 D SOT109-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION STR 1 16 VCC 1 STR Strobe input D 2 15 OE 2 D Serial input CP 3 14 QP4 3 CP Clock input 13 QP5 4, 5, 6, 7, 14, 13, 12, 11 QP0 to QP7 Parallel outputs QP0 4 QP1 5 12 QP6 8 GND Ground (0 V) QP2 6 11 QP7 9, 10 QS1, QS2 Serial outputs QP3 7 10 QS2 15 OE Output enable input GND 8 9 QS1 16 VCC Positive supply voltage SV01611 1998 Jun 23 2 853-2078 19619 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 3 1 1 C2 15 STR QS1 CP 2 EN3 9 SRG8 QS2 10 QP0 4 QP1 5 QP2 6 QP3 7 QP4 14 QP5 13 QP6 12 QP7 11 3 C1/ 2 1D 2D 3 4 5 D 6 7 14 13 12 11 OE 9 15 SV01612 10 SV01613 FUNCTIONAL DIAGRAM 2 3 1 15 D CP 8-STATE SHIFT REGISTER STR QS2 10 QS1 9 8-BIT STORAGE REGISTER OE 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 Q51 QP6 QP7 4 5 6 7 14 13 12 11 SV01614 LOGIC DIAGRAM STAGES 1 TO 6 STAGE 0 D D Q STAGE 7 D Q FF0 D Q7’ Q FF7 CP D CP CP CP Q QS2 CP latch D Q D latch Q latch CP CP STR OE QP0 QP1 QP3 QP2 1998 Jun 23 QP5 QP4 QP7 QP6 3 SV01615 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 FUNCTION TABLE INPUTS PARALLEL OUTPUT SERIAL OUTPUTS CP OE STR D QP0 QPn QS1 ↑ L X X Z Z Q’6 NC ↓ L X X Z Z NC QP7 ↑ H L X NC NC Q’6 NC ↑ H H L L QPn–1 Q’6 NC ↑ H H H H QPn–1 Q’6 NC ↓ H H H NC NC NC QP7 ↑ = LOW-to–HIGH CP transition ↓ = HIGH-to-LOW CP transition Q’6 = the information in the 8th register stage is transferred to the 8th register stage and QSn clock edge. NOTES: H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state NC = no change TIMING DIAGRAM CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT CP D STR OE INTERNAL Q’0 (FF0) OUTPUT Z–state QP0 INTERNAL Q’6 (FF6) OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 Z–state SV01616 1998 Jun 23 QS2 4 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 ABSOLUTE MAXIMUM RATINGSNO TAG, NO TAG In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). PARAMETER SYMBOL VCC DC supply voltage IIK DC input diode current IOK IO IGND, ICC Tstg PTOT CONDITIONS RATING UNIT –0.5 to +7.0 V VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 DC VCC or GND current for types with – standard outputs mA 50 Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) mA –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs CONDITIONS MIN TYP MAX UNIT See Note NO TAG 1.0 3.3 3.6 V 0 – VCC V 0 – VCC V +85 +125 °C 500 200 100 ns/V See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Jun 23 5 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions, voltages are referenced to GND (ground = 0 V) LIMITS SYMBOL VIH VIL PARAMETER HIGH level Input voltage LOW level Input voltage -40°C to +85°C TEST CONDITIONS MIN NO TAG VCC = 1.2 V VCC 0.6 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 VCC = 1.2 V 0.4 VOH VOH HIGH level output voltage; STANDARD outputs VOL LOW level output voltage; all outputs MAX MIN UNIT MAX VCC V GND GND VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8 VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage; all outputs TYP -40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0.25 0.40 0.50 V 1.0 1.0 µA 5 10 µA V LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA Input leakage current VCC = 3.6 V; VI = VCC or GND IOZ 3-State output OFF-state current VCC = 3.6 V; VI = VIH or VIL; VO = VCC or GND ICC Quiescent supply current; SSI VCC = 3.6; VI = VCC or GND; IO = 0 20.0 40 µA Quiescent supply current; flip-flops VCC = 3.6; VI = VCC or GND; IO = 0 20.0 80 µA Quiescent supply current; MSI VCC = 3.6 V; VI = VCC or GND; IO = 0 20.0 160 Quiescent supply current; LSI VCC = 3.6 V; VI = VCC or GND; IO = 0 500 1000 Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 VOL II ICC ∆ICC NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 23 6 µA µA Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5ns; CL = 50pF LIMITS CONDITION SYMBOL PARAMETER WAVEFORM VCC (V) tPHL/tPLH tPHL/tPLH tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tw tw –40 to +85 °C MIN 31 58 70 2.7 23 43 51 3.0 to 3.6 172 34 41 1.2 80 2.0 27 51 61 2.7 20 38 45 3.0 to 3.6 142 30 36 1.2 115 2.0 39 75 90 2.7 29 55 66 3.0 to 3.6 222 44 53 1.2 105 2.0 36 68 82 2.7 26 50 60 3.0 to 3.6 202 40 48 1.2 100 2.0 34 65 77 2.7 25 48 56 3.0 to 3.6 192 38 45 1.2 65 2.0 24 40 49 2.7 18 32 37 3.0 to 3.6 142 26 Propagation g delay y CP to QS2 Propagation g delay y CP to QPn Propagation g delay y STR to QPn 3-State Output enable time OE to Q QPn 3-State Output disable time OE to Q QPn Clock pulse width HIGH or LOW 2.0 34 41 2.7 25 6 30 20 52 24 2.0 34 9 41 2.7 25 6 30 3.0 to 3.6 20 52 24 22 9 26 2.7 16 6 19 3.0 to 3.6 13 52 15 Set-u time Set-up CP to STR 7 ns ns ns ns ns ns ns 25 2.0 Set-up time D to CP ns 30 9 3.0 to 3.6 Strobe pulse width; HIGH UNIT MAX 90 ns 50 2.0 43 17 51 2.7 31 13 38 3.0 to 3.6 1998 Jun 23 MIN 2.0 1.2 tsu MAX 1.2 Propagation g delay y CP to QS1 1.2 tsu TYP1 –40 to +125 °C 25 10 NO TAG 30 ns Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 CONDITION SYMBOL PARAMETER –40 to +85 °C WAVEFORM VCC (V) MIN 1.2 Th Hold time D to CP MIN UNIT MAX –10 5 –4 5 2.7 5 –3 5 5 –2 NO TAG 5 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. 8 MAX 2.0 3.0 to 3.6 1998 Jun 23 TYP1 –40 to +125 °C ns Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 AC CHARACTERISTICS (Continued) GND = 0 V; tr = tf ≤ 2.5ns; CL = 50pF SYMBOL PARAMETER WAVEFORM CONDITION –40 to +85 °C VCC (V) TYP1 MIN 1.2 MIN MAX UNIT –25 5 –9 5 2.7 5 –6 5 3.0 to 3.6 5 –52 5 2.0 14 52 12 2.7 19 70 16 3.0 to 3.6 24 872 20 Maximum clock pulse frequency fmax MAX 2.0 Hold time D to STR Th –40 to +125 °C ns MHz NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC ≥ 2.7 V VX = VOL + 0.1 × VCC at VCC < 2.7 ς VY = VOH ± 0.3 V at VCC ≥ 2.7 V VY = VOH ± 0.1 × VCC at VCC < 2.7V VCC 1/fmax VCC CP INPUT CP INPUT VM tsu GND VOH QPn, QS1 OUTPUT VM GND tW tPHL tPLH th VCC STR INPUT VM GND VOL VM tW tPLH VOH QS2 OUTPUT tPLH tPHL QPn OUTPUT VM VM VOL VOL SV01620 SV01619 Figure 2. Strobe (STR) to output (QPn) propagation delays and the strobe pulse width and the clock set-up and hold times for strobe input. Figure 1. Clock (CP) to output (QPn, QS1, QS2) propagation delays, the clock pulse width and the maximum clock frequency. 1998 Jun 23 tPHL VOH 9 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 VCC VCC OE INPUT VM GND tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL VM CP INPUT GND tPZL tsu tsu th th VCC VM VX D INPUT VOH GND VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH GND VM tPZH tPHZ QPn, QS1, QS2 OUTPUT VM outputs disabled outputs enabled VM VOL outputs enabled SV01618 The shaded areas indicate when the input is permitted to change for predictable output performance. SV01617 Figure 3. 3-State enable and disable times for input OE. Figure 4. Data set-up and hold times for the data input (D). TEST CIRCUIT tW 90% S1 Vcc VS1 Open GND NEGATIVE PULSE 90% VM VI VM 10% 10% 0V Vl RL = 1k VO PULSE GENERATOR D.U.T. RL = 1k RT CL= 50pF tTHL (tf) tTLH (tr) tTLH (tr) tTHL (tf) 90% POSITIVE PULSE VI 90% VM VM 10% tW Test Circuit for Outputs 10% 0V VM = 1.5V Input Pulse Definition DEFINITIONS SWITCH POSITION VCC VI RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VS1 TEST S1 tPLH/tPHL Open < 2.7V VCC 2 VCC tPLZ/tPZL VS1 2.7–3.6V 2.7V 2 VCC tPHZ/tPZH GND ≥ 4.5 V VCC 2 VCC SY00044 Figure 5. Load circuitry for switching times. 1998 Jun 23 10 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 Jun 23 11 SOT38-4 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Jun 23 12 SOT109-1 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 NOTES 1998 Jun 23 13 Philips Semiconductors Product specification 8-stage shift-and-store bus register 74LV4094 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 08-98 9397-750-04662