AN99123 Reset Voltage and Timing Requirements for MirrorBit® Flash AN99123 describes the considerations of reset control signal timing when using MirrorBit NOR flash devices in an application. 1 Synopsis MirrorBit NOR flash has several unique reset control signal timing requirements. Timing requirements vary by MirrorBit process and family (110 nm, 90 nm, 65 nm, GLxxxN, WSxxxP, etc…). System designers must accommodate these requirements for reliable operation. 2 3 Applicable Device Families 110 nm MirrorBit Process: S29GLxxxN, S29PLxxxN, S29WSxxxN, S29NSxxxN 90 nm MirrorBit Process: S29GLxxxP, S29NSxxxP, S29WSxxxP 65 nm MirrorBit Process: S29GLxxxR, S29WSxxxR, S29NSxxxR, S29VS/XSxxxR 65 nm MirrorBit Eclipse™ Process: S29GLxxxS ( 1 GBit), S70GL02GS Parameters of Interest VLKO Low VCC Lock-Out Voltage tVCS VCC > VCC-MIN setup requirement prior to RESET# negation tVIOS VIO > VIO-MIN setup requirement prior to RESET# negation tRP RESET# pulse width (assertion period) tRH RESET# high requirement prior to CE# assertion tREADY tRB 4 Period from RESET# assertion to RY/BY# negation PERIOD from RY/BY# negation to CE# assertion Reset Requirements - 110 nm Process Node Products The second generation MirrorBit devices have reset timing similar to the first generation of MirrorBit devices. The power and timing requirements for Power-On-Reset and Warm-RESET (also known as Hard Reset) of the 110 nm process node products are reviewed in this section. 4.1 Power-On-Reset Requirements During Power-On, VCC should rise monotonically and must remain greater than VLKO (Low VCC Lock-Out Voltage) during all reset operations. VIO can either be tied to VCC or can be driven to a different voltage level (see Figure 1). In the latter case, VIO must exceed VIO_MIN before RESET# is negated and must be maintained between VIO_MIN and VCC +100 mV. During VCC ramp-up, RESET# must be asserted (low). From the period in time when VCC exceeds VCC_MIN, RESET# must remain asserted for a period of tVCS prior to negation (see Figure 1). Control signal transitions can be initiated tRH following RESET# negation. www.cypress.com Document No. 001-99123 Rev. *A 1 Reset Voltage and Timing Requirements for MirrorBit® Flash 4.1.1 Power-On-Reset Timing Table 1. 110 nm Process Node Products - Power-On-Reset Timing Parameter Description S29WSxxxN S29NSxxxN S29GLxxxN S29PLxxxN 1 ms 1 ms 50 µs 250 µs 1 ms 50 µs 250 µs 10 µs 50 ns 200 ns tVCS VCC Setup Time to RESET# negation (min) tVIOS VIO Setup Time to RESET# negation (min) 1 ms tRH RESET# high prior to CE# assertion (min) 200 ns Notes: 1. For S29WSxxxN and S29NSxxxN, VCC ramp rate must exceed 1V/100 µs otherwise a hardware reset would be required. 2. For S29PLxxxN, VCC ramp rate must exceed 1V/400 µs otherwise a hardware reset would be required. 3. For S29PLxxxN and S29WSxxxN, VIO is internally connected to VCC. 4. For S29NSxxxN, VIO pin is named VCCQ. Figure 1. 110 nm Process Node Products- Power-On Reset Timing VCC VIO VCC_MIN VIO_MIN VIO ≤ VCC + 200 mV tRH CE# tVIOS tVCS RESET# 4.2 Warm-Reset Requirements Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Timing requirements vary by the state of the device prior to RESET# assertion, specifically whether or not the device is performing an embedded operation (program or erase operation in progress). 4.2.1 Warm-Reset Timing While Embedded Operation Not In Progress In the event of the Warm-Reset being initiated when an embedded operation is not in progress (see Figure 2), the internal reset operation requires tRP to be completed. Control signal transitions can be initiated tRH following internal reset operation completion. RY/BY# will stay in the ready state as the device operates during nonembedded operations. The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions. Table 2. 110 nm Process Node Products - Warm Reset Timing - Embedded Operation Not in Progress Parameter Description S29WSxxxN S29NSxxxN S29GLxxxN S29PLxxxN tRP RESET# Pulse Width (min) 30 µs 200 ns 500 ns 30 µs tRH RESET# high prior to CE# assertion (min) 200 ns 10 µs 50 ns 200 ns Figure 2. 110 nm Process Node Products- Warm Reset Timing – Embedded Operation Not In Progress CE# tRH tRP RESET# www.cypress.com Document No. 001-99123 Rev. *A 2 Reset Voltage and Timing Requirements for MirrorBit® Flash 4.2.2 Warm-Reset Timing While Embedded Operation In Progress In the event of the Warm-Reset being initiated when an embedded operation is in progress (see Figure 3), the internal reset operation requires tREADY to be completed. tREADY is comprised of the time required to gracefully exit an embedded programming operation, followed by the standard internal reset operation and the set-up time from reset operation completion until a control signal transition detection can be guaranteed. The complete reset operation is triggered by the falling edge of RESET#. RESET# must remain asserted for a period of tRP. Control signals transition can be initiated tREADY after the falling edge of RESET#. Table 3. 110 nm Process Node Products - Warm Reset Timing - Embedded Operation in Progress Parameter tREADY Description RESET# assertion to RY/BY# negation (min) S29WSxxxN S29NSxxxN S29GLxxxN S29PLxxxN 30.2 µs 10.2 µs 20 µs 30.2 µs tRB RY/BY# high to CE# assertion (min) 0 ns 0 ns 0 ns 0 ns tRP RESET# Pulse Width (min) 30 µs 200 ns 500 ns 30 µs tRH RESET# high prior to CE# assertion (min) 200 ns 10 µs 50 ns 200 ns Notes: 1. For S29WSxxxN, S29NSxxxN and S29PLxxxN, tREADY = tRP + tRH. No additional waiting time is required. 2. For GLxxxN, The sum of tRP and tRH must be equal to or greater than tREADY. A typical implementation would have RESET# asserted a period of tREADY with a short delay from RESET# negation before asserting CE# and initiating a read operation. An alternate implementation is asserting RESET# for a shorter period of tRP and employing a delay loop to prevent flash control signal accesses for tREADY from the assertion of RESET#. An additional option is to monitor RY/BY# following the rising edge of a RESET# pulse at least tRP in duration. When RY/BY# is detected high, control signal transitions can be initiated. Figure 3. 110 nm Process Node Products - Warm Reset Timing – Embedded Operation In Progress tREADY tRB RY/BY# CE#, OE# tRH RESET# tRP 5 Reset Requirements - 90 nm Process Node Products New reset conditions are required for the 90 nm MirrorBit devices because of circuit changes implemented to reduce die size and to improve endurance of Advanced Sector Protection PPB bits. The Power-On-Reset and Warm Reset requirements for these new device families are reviewed in this section. 5.1 Power-On-Reset Requirements During Power-On, VCC should rise monotonically and must remain greater than VLKO during all reset operations. VIO can either be tied to VCC or can be driven to a different voltage level. In the latter case, VIO must exceed VIO_MIN before RESET# is negated and must be maintained between VIO_MIN and VCC +100 mV. During VCC ramp-up, RESET# must be asserted (low). From the period in time when VCC exceeds VCC_MIN, RESET# must remain asserted for a period of tVCS) prior to negation (see Figure 4). Control signal transitions can be initiated tRH following RESET# negation. www.cypress.com Document No. 001-99123 Rev. *A 3 Reset Voltage and Timing Requirements for MirrorBit® Flash 5.1.1 Power-On-Reset Timing Table 4. 90 nm Process Node Products - Power-On-Reset Timing Parameter Description S29WSxxxP S29NSxxxP S29GLxxxP 30 µs 30 µs 35 µs tVCS VCC Setup Time to RESET# negation (min) tVIOS VIO Setup Time to RESET# negation (min) 30 µs 30 µs 35 µs tRH RESET# high prior to CE# assertion (min) 200 ns 200 ns 200 ns Notes: 1. For S29WSxxxP, VCC ramp rate must exceed 1V/400 µs otherwise a hardware reset would be required. 2. For S29WSxxxP and S29NSxxxP, VIO pin is named VCCQ. 3. VCC and VIO (resp. VCCQ) must be ramped up simultaneously for proper power-up. 4. If RESET# is not stable for tVCS or tVIOS: The device does not permit any read and write operations, a valid read operation returns FFh and a hardware reset is required. Figure 4. 90 nm Process Node Products- Power-On Reset Timing VCC VIO tVIOS tVCS tRP RESET# tRH tRPH CE# 5.2 Warm-Reset Requirements Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Timing requirements vary by the state of the device prior to RESET# assertion, specifically whether or not the device is performing an embedded operation (program or erase operation in progress). During Warm-Reset operations, VCC must be maintained greater than VLKO. 5.2.1 Warm-Reset Timing While Embedded Operation Not In Progress In the event of the Warm-Reset being initiated when an embedded operation is not in progress (see Figure 5), the internal reset operation requires tRP to be completed. Control signal transitions can be initiated tRH following internal reset operation completion. RY/BY# will stay in the ready state as the device operates during nonembedded operations. The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions. Table 5. 90 nm Process Node Products - Warm Reset Timing - Embedded Operation Not in Progress Parameter www.cypress.com Description S29WSxxxP S29NSxxxP S29GLxxxP tRP RESET# Pulse Width (min) 30 µs 50 ns 35 µs tRH RESET# high prior to CE# assertion (min) 200 ns 200 ns 200 ns Document No. 001-99123 Rev. *A 4 Reset Voltage and Timing Requirements for MirrorBit® Flash Figure 5. 90 nm Process Node Products– Warm Reset Timing – Embedded Operation Not In Progress VCC ≥ VLKO VCC RY/BY# tRH CE#, OE# tRP RESET# 5.2.2 Warm-Reset Timing While Embedded Operation In Progress In the event of the Warm-Reset being initiated when an embedded operation is in progress (see Figure 6), the internal reset operation requires tREADY to be completed. tREADY is comprised of the time required to gracefully exit an embedded programming operation, followed by the standard internal reset operation and the set-up time from reset operation completion until a control signal transition detection can be guaranteed. The complete reset operation is triggered by the falling edge of RESET#. RESET# must remain asserted for a period of tRP. Control signals transition can be initiated by tREADY after the falling edge of RESET#. Table 6. 90 nm Process Node Products - Warm Reset Timing - Embedded Operation in Progress Parameter tREADY Description S29WSxxxP S29NSxxxP S29GLxxxP 30.2 µs 10 µs 35.2 µs RESET# assertion to RY/BY# negation (min) tRB RY/BY# high to CE# assertion (min) 0 ns 0 ns 0 ns tRP RESET# Pulse Width (min) 30 µs 50 ns 35 µs tRH RESET# high prior to CE# assertion (min) 200 ns 200 ns 200 ns Notes: 1. For S29WSxxxP and S29GLxxxP, tREADY = tRP + tRH. No additional waiting time is required. 2. For NSxxxP, The sum of tRP and tRH must be equal to or greater than tREADY. A typical implementation would have RESET# asserted a period of tREADY with a short delay from RESET# negation before asserting CE# and initiating a read operation. An alternate implementation is asserting RESET# for a shorter period of tRP and employing a delay loop to prevent flash control signal accesses for tREADY from the assertion of RESET#. An additional option is to monitor RY/BY# following the rising edge of a RESET# pulse at least tRP in duration. When RY/BY# is detected high, control signal transitions can be initiated. Figure 6. 90 nm Process Node Products - Warm Reset Timing – Embedded Operation In Progress tREADY tRB RY/BY# CE#, OE# tRH RESET# tRP www.cypress.com Document No. 001-99123 Rev. *A 5 Reset Voltage and Timing Requirements for MirrorBit® Flash 6 Reset Requirements - 65 nm Process Node Products New reset conditions are required for the 65 nm MirrorBit devices because of circuit changes implemented to reduce die size. The Power-On-Reset and Warm Reset requirements for these new device families are reviewed in this section. 6.1 Power-On-Reset Requirements During Power-On, the VCC and VIO ramp rate could be non-linear. However, VCC and VIO must remain greater than VLKO during all reset operations. It is also recommended to ramp up those two signals simultaneously. 6.1.1 Power-On-Reset Timing Table 7. 65 nm Process Node Products - Power-On-Reset Timing Parameter Description S29WSxxxR S29NSxxxR S29GLxxxR S29VS/XSxxxR tVCS VCC Setup Time to RESET# negation (min) 300 µs 300 µs 300 µs 300 µs tVIOS VIO Setup Time to RESET# negation (min) 300 µs 300 µs 300 µs 300 µs tRH RESET# high prior to CE# assertion (min) 200 ns 200 ns 150 ns 200 ns tRP RESET# Pulse Width (min) 50 ns 50 ns 200 ns 50 ns tRPH RESET# Low to CE# Low (min) 10 µs 10 µs 35 µs 10 µs Notes: 1. VCC and VIO ramp rate could be non-linear. 2. RESET# must be high after VCC and VIO are higher than VCC minimum. 3. The sum of tRP and tRH must be equal to or greater than tRPH. Figure 7. 65 nm Process Node Products - Power-On Reset Timing VCC VIO tVIOS tVCS tRP RESET# tRH tRPH CE# 6.2 Warm-Reset Requirements Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. Starting from the 65 nm MirrorBit products, the warm reset timing requirements will be totally independent from the state of the device prior to RESET# assertion, namely whether an embedded operation was in progress or not. During Warm-Reset operations, VCC must be maintained greater than VLKO. During Warm-Reset (see Figure 8), the internal reset operation requires tRP to be completed. Control signal transitions may be initiated tRH following RESET# negation. www.cypress.com Document No. 001-99123 Rev. *A 6 Reset Voltage and Timing Requirements for MirrorBit® Flash 6.2.1 Warm-Reset Timing Table 8. 65 nm Process Node Products - Warm Reset Timing Parameter Description S29WSxxxR S29NSxxxR S29GLxxxR S29VS/XSxxxR 10 µs 10 µs 35 µs 10 µs tRPH RESET# Low to CE# Low (min) tRP RESET# Pulse Width (min) 50 ns 50 ns 200 ns 50 ns tRH RESET# high prior to CE# assertion (min) 200 ns 200 ns 150 ns 200 ns Notes: 1. The sum of tRP and tRH must be equal to or greater than tRPH. 2. CE#, OE# and WE# must be at logic high during Reset Time. The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions. An equally effective and alternate implementation for the 65 nm MirrorBit devices is asserting RESET# for a short period followed by a long delay to allow the completion of the internal reset operation prior to initiating control signal transitions. Figure 8. 65 nm Process Node Products – Warm Reset Timing tRP RESET# tRH tRPH CE# 7 Reset Requirements - 65 nm Eclipse MirrorBit Products New reset conditions are required for the 65 nm Eclipse MirrorBit devices because of circuit changes implemented to reduce die size. The Power-On-Reset and Warm Reset requirements for these new device families are reviewed in this section. 7.1 Power-On-Reset Requirements During Power-On, VCC and VIO ramp rate could be non-linear. However, VCC and VIO must remain greater than VLKO during all reset operations. It is also recommended to ramp up those two signals simultaneously. 7.1.1 Power-Up Sequencing VCC must always be greater than or equal to VIO (VCC VIO). VIO must track the rise and fall of VCC within 200 mV (VIO VCC - 200 mV) when VIO is below the VIO minimum. The device ignores all inputs until a time delay of tVCS has elapsed after the moment that VCC and VIO both rise above, and stay above, the minimum VCC and VIO thresholds. During tVCS the device is performing power on reset operations. Table 9. 65 nm Eclipse Products - Power-Up Timing S29GLxxxS 1 Gbit S70GL02GS tVCS VCC Setup Time to RESET# negation (min) 300 µs 600 µs tVIOS VIO Setup Time to RESET# negation (min) 300 µs 600 µs Parameter www.cypress.com Description Document No. 001-99123 Rev. *A 7 Reset Voltage and Timing Requirements for MirrorBit® Flash Figure 9. 65 nm Eclipse Products - Power-up Timing 7.1.2 Power-On-Reset Timing Table 10. 65 nm Eclipse Products - Power-On-Reset Timing S29GLxxxS 1 Gbit S70GL02GS tVCS VCC Setup Time to RESET# negation (min) 300 µs 600 µs tVIOS VIO Setup Time to RESET# negation (min) 300 µs 600 µs tRH RESET# high prior to CE# assertion (min) 50 ns 50 ns tRP RESET# Pulse Width (min) 200 ns 200 ns tRPH RESET# Low to CE# Low (min) 35 µs 70 µs Parameter Description Notes: 1. VCC and VIO ramp rate could be non-linear. 2. RESET# Low is optional during POR. If RESET# is asserted during POR, the later of tRPH, tVIOS, or tVCS will determine when CE# may go Low. If RESET# remains low after tVIOS, or tVCS is satisfied, tRPH is measured from the end of tVIOS, or tVCS. RESET# must also be high tRH before CE# goes low. 3. The sum of tRP and tRH must be equal to or greater than tRPH. 4. RY/BY# pin is low during power-up. Figure 10. 65 nm Eclipse Products - Power On Reset Timing VCC VIO tVIOS tVCS tRP RESET# tRH tRPH CE# www.cypress.com Document No. 001-99123 Rev. *A 8 Reset Voltage and Timing Requirements for MirrorBit® Flash 7.2 Warm-Reset Requirements Warm-Reset, also known as Hard Reset, requires RESET# to pulse from high to low to high. For the 65 nm MirrorBit Eclipse products, the warm reset timing requirements will be also totally independent from the state of the device prior to RESET# assertion, namely whether an embedded operation was in progress or not. During Warm-Reset operations, VCC must be maintained greater than VLKO. During Warm-Reset (see Figure 11), the internal reset operation requires tRP to be completed. Control signal transitions may be initiated tRH following RESET# negation. 7.2.1 Warm-Reset Timing Table 11. 65 nm Eclipse Products - Warm Reset Timing S29GLxxxS 1 Gbit S70GL02GS tRPH RESET# Low to CE# Low (min) 35 µs 70 µs tRP RESET# Pulse Width (min) 200 ns 200 ns tRH RESET# high prior to CE# assertion (min) 50 ns 50 ns Parameter Description Notes: 1. The sum of tRP and tRH must be equal to or greater than tRPH. 2. CE#, OE# and WE# are recommended to be at logic high during Reset Time. The typical implementation would have RESET# asserted for at least the time required to complete the internal reset operation and a short delay following RESET# negation prior to initiating control signal transitions. An equally effective and alternate implementation for the 65 nm MirrorBit Eclipse devices is asserting RESET# for a short period followed by a long delay to allow the completion of the internal reset operation prior to initiating control signal transitions. Figure 11. 65 nm Eclipse Products - Warm Reset Timing tRP RESET# tRH tRPH CE# www.cypress.com Document No. 001-99123 Rev. *A 9 Reset Voltage and Timing Requirements for MirrorBit® Flash Document History Page Document Title: AN99123 - Reset Voltage and Timing Requirements for MirrorBit® Flash Document Number: 001-99123 Rev. ECN No. Orig. of Change ** – – *A 4980968 MSWI www.cypress.com Submission Date Description of Change 11/14/2006 to Initial version 10/04/2010 Updated document format Removed all references to AM29LVxxxM, MBM29PLxxxM, S29GLxxxM, S29PLxxxP and S29GLxxxA Added POR and Reset requirements for 90 nm, 65 nm and 65 nm Eclipse products 10/22/2015 Updated in Cypress template Document No. 001-99123 Rev. *A 10 Reset Voltage and Timing Requirements for MirrorBit® Flash Worldwide Sales and Design Support Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. 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The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-99123 Rev. *A 11