AN98576 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Author: Cypress Associated Part Family: S25FL-P, S25FL1-K AN98576 provides migration guidelines for migrating from S25FL-P to S25FL1-K Cypress SPI Flash Families. Discussions will focus on same density migrations, specifically cases of migrating from the S25FL032P to S25FL132K and when migrating from the S25FL064P to the S25FL164K. Concerns regarding migration from/to other densities can be extrapolated from the provided discussions. Contents 1 2 3 1 Introduction ............................................................... 1 Feature Comparison ................................................. 1 2.1 Packaging - All Densities .................................. 2 2.2 Sector Architecture ........................................... 2 2.3 Sector Protection .............................................. 3 2.4 Status and Configuration Registers .................. 5 Software Considerations ........................................... 7 3.1 S25FL-P versus S25FL1-K Command Set Comparison ...................................................... 7 3.2 OTP Related Commands ..................................8 Timing Considerations ............................................... 9 4.1 Power-Up Timing ..............................................9 4.2 Data in Setup/Hold Time .................................10 4.3 Further Timing Comparison ............................10 5 Conclusion............................................................... 10 Document History Page ...................................................11 Worldwide Sales and Design Support ..............................12 4 Introduction This application note provides migration guidelines for migrating from S25FL-P to S25FL1-K Cypress SPI Flash Families. Discussions will focus on same density migrations, specifically cases of migrating from the S25FL032P to S25FL132K and when migrating from the S25FL064P to the S25FL164K. Concerns regarding migration from/to other densities can be extrapolated from the provided discussions. The application note is based on information available to date from data sheets and other application notes publicly available from Cypress. Please also refer to the latest relevant specifications. 2 Feature Comparison S25FL-P products are well suited for migrations to S25FL1-K products. Some of the reasons are compatible pinouts, packages, command set, and 4/64 kB block/sector structure. Both product families support Dual I/O and Quad I/O modes. The major difference is the different OTP handling, which requires some software changes when this feature is in use. Table 1. Cypress S25FL-P and S25FL1-K Feature Comparison (Sheet 1 of 2) S25FL032P S25FL064P S25FL132K S25FL164K Standard Pinout Standard Packages 4/64 kB Block/sector (1) (2) Multi I/O (3) (3) Standard Command Set www.cypress.com Document No. 001-98576 Rev. *A 1 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 1. Cypress S25FL-P and S25FL1-K Feature Comparison (Sheet 2 of 2) S25FL032P S25FL064P S25FL132K S25FL164K (4) (5) Block Protection OTP Notes: : Feature is supported. 1. Supporting uniform 64-kB sectors with some 4-kB boot sectors. 2. Supporting both uniform 64-kB sectors and uniform 4-kB sectors. 3. Supporting Dual and Quad I/O. 4. 506 bytes (33 regions). 5. 4 x 256-byte security registers. 2.1 Packaging - All Densities The most common packages for S25FL-P and S25FL1-K are the SOIC packages. The pinout is identical, thus, this will allow a direct replacement without PCB redesign. Figure 1 shows those SOIC packages and pinouts. Please refer to the data sheets for detailed package information. Figure 1. SOIC 150/208/300 mil Package and Pinout (16-pin and 8-pin Versions) HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 NC 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC CS# 7 10 GND SO/IO1 8 9 CS# 1 8 VCC SO (IO1) 2 7 HOLD# (IO3) WP# (IO2) 3 6 SCK GND 4 5 SI (IO0) W#/ACC/IO2 Table 2 summarizes the full set of available packages for S25FL-P and S25FL1-K. Table 2. S25FL-P and S25FL1-K Available Packages Cypress S25FL-P S25FL032P Cypress S25FL1-K S25FL064P SOIC8 208 mil SOIC16 300 mil Note: 2.2 S25FL132K S25FL164K SOIC8 150 mil USON 5x6 WSON 6x8 BGA 6x8 : Package is available. Sector Architecture The sector architecture between S25FL-P and S25FL1-K can be considered compatible. S25FL-P contains 64-kB sectors while offering top or bottom parameter blocks of 4-kB (two 64-kB sectors are broken down into sixteen 4kB sub-sectors each). S25FL1-K offers both 4-kB and 64-kB uniform sector architecture. www.cypress.com Document No. 001-98576 Rev. *A 2 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories To summarize, both device families support similar flexible erase architecture of 4 kB, 64kB, and chip erase operations (see Table 12, . Command Set of S25FL-P and S25FL1-K on page 7). The 8-kB sector erase command is only supported by the S25FL-P. Page programming size of 256 bytes is also identical. Table 3 shows a summary of the erase and programming granularity. When migrating from S25FL-P to S25FL1-K, if the 64-kB erase command is used exclusively, then software changes are not mandatory. Table 3. Erase and Programming Granularity Cypress S25FL-P Cypress S25FL1-K Sector Size 4 kB (1), 64 kB 4 kB, 64 kB Erase Size 4-kB, 8-kB, 64-kB, chip erase 4-kB, 64-kB, chip erase Page Prog. Size 256 bytes 256 bytes Note: 1. Top or Bottom 32 parameter sectors (4-kB) but not uniform across the device. 2.3 Sector Protection Both S25FL-P and S25FL1-K offer the same Sector Protection based on Block Protect Bits (BP2, BP1, BP0). Therefore there is no software change required when migrating to the S25FL1-K. Using BP bits, all, none, or a portion of the memory array can be protected from Program and Erase instructions. By default, the BP Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register SR (SR[4], SR[3], SR[2]) that provide Write Protection control and status (Status Register is also referred to as SR1 in the S25FL1-K case). The factory default setting for the Block Protect Bits is 0 (none of the array is protected). BP bits can be set using the Write Status Register Instruction. The TBPROT bit on the S25FL-P is located at bit 5 of the Configuration Register (CR[5]) while the equivalent bit on S25FL1-K (TB) is located at bit 5 of the Status Register-1 (SR1[5]). The non-volatile Top/Bottom Protection bit (TBPROT/TB) controls if the BP Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array. The non-volatile Sector/Block Protect bit (SEC) on S25FL1-K devices controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array. The Complement Protect bit (CMP) on S25FL1-K is a non-volatile read/write bit in the status register SR2 (SR2[6]). It is used in conjunction with SEC, TBPROT/TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TBPROT/TB, BP2, BP1, and BP0 will be reversed. The SEC and CMP Bits functionality is not available on S25FL-P. Therefore when migrating to the S25FL1-K, no software adaptation is required in this area. Table 4, 5 and 6 respectively show the S25FL032P (TBPROT = 0), S25FL032P (TBPROT = 1) and S25FL132K sector protection. Table 4. S25FL032P Status Register Memory Protection (TBPROT = 0) Status Register Block BP2 www.cypress.com BP1 BP0 Memory Array Protected Address Range Protected Sectors Unprotected Address Range Unprotected Sectors Protected Portion of Total Memory Area 0 0 0 None 0 000000h-3FFFFFh SA63:SA0 0 0 0 1 3F0000h-3FFFFFh (1) SA63 000000h-3EFFFFh SA62:SA0 1/64 0 1 0 3E0000h-3FFFFFh (2) SA63:SA62 000000h-3DFFFFh SA61:SA0 1/32 0 1 1 3C0000h-3FFFFFh (4) SA63:SA60 000000h-3BFFFFh SA59:SA0 1/16 1 0 0 380000h-3FFFFFh (8) SA63:SA56 000000h-37FFFFh SA55:SA0 1/8 000000h-2FFFFFh SA47:SA0 1/4 1 0 1 300000h-3FFFFFh (16) SA63:SA48 1 1 0 200000h-3FFFFFh (32) SA63:SA32 000000h-1FFFFFh SA31:SA0 1/2 1 1 1 000000h-3FFFFFh (64) SA63:SA0 None None All Document No. 001-98576 Rev. *A 3 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 5. S25FL032P Status Register Memory Protection (TBPROT = 1) Status Register Block Memory Array Protected Address Range Protected Sectors Unprotected Address Range Unprotected Sectors Protected Portion of Total Memory Area BP2 BP1 BP0 0 0 0 None 0 000000h-3FFFFFh SA0:SA63 0 0 0 1 000000h-00FFFFh (1) SA0 010000h-3FFFFFh SA1:SA63 1/64 0 1 0 000000h-01FFFFh (2) SA0:SA1 020000h-3FFFFFh SA2:SA63 1/32 0 1 1 000000h-03FFFFh (4) SA0:SA3 040000h-3FFFFFh SA4:SA63 1/16 1 0 0 000000h-07FFFFh (8) SA0:SA7 080000h-3FFFFFh SA8:SA63 1/8 1 0 1 000000h-0FFFFFh (16) SA0:SA15 100000h-3FFFFFh SA16:SA63 1/4 1 1 0 000000h-1FFFFFh (32) SA0:SA31 200000h-3FFFFFh SA32:SA63 1/2 1 1 1 000000h-3FFFFFh (64) SA0:SA63 None None ALL Table 6. S25FL132K Status Register Memory Protection (CMP = 0)(4) Status Register (1) S25FL1-K Family (32 MBit) Block Protection (CMP=0) (3) SEC TB BP2 BP1 BP0 Protected Block(s) X X 0 0 0 None None None None 0 0 0 0 1 63 3F0000h – 3FFFFFh 64 kB Upper 1/64 0 0 0 1 0 62 and 63 3E0000h – 3FFFFFh 128 kB Upper 1/32 0 0 0 1 1 60 thru 63 3C0000h – 3FFFFFh 256 kB Upper 1/16 Protected Addresses Protected Density Protected Portion (2) 0 0 1 0 0 56 thru 63 380000h – 3FFFFFh 512 kB Upper 1/8 0 0 1 0 1 48 thru 63 300000h – 3FFFFFh 1 MB Upper 1/4 0 0 1 1 0 32 thru 63 200000h – 3FFFFFh 2 MB Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64 kB Lower 1/64 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128 kB Lower 1/32 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/16 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512 kB Lower 1/8 0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1 MB Lower 1/4 0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2 MB Lower 1/2 X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4 MB All 1 0 0 0 1 63 3FF000h – 3FFFFFh 4 kB Upper 1/1024 1 0 0 1 0 63 3FE000h – 3FFFFFh 8 kB Upper 1/512 1 0 0 1 1 63 3FC000h – 3FFFFFh 16 kB Upper 1/256 1 0 1 0 X 63 3F8000h – 3FFFFFh 32 kB Upper 1/128 1 1 0 0 1 0 000000h – 000FFFh 4 kB Lower 1/1024 1 1 0 1 0 0 000000h – 001FFFh 8 kB Lower 1/512 1 1 0 1 1 0 000000h – 003FFFh 16 kB Lower 1/256 1 1 1 0 X 0 000000h – 007FFFh 32 kB Lower 1/128 Notes: 1. X = don’t care.1. 2. Lower or Upper portion of the array 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. 4. The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (SR2[6]). It is used in conjunction with SEC, TB, BP2, BP1, and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1, and BP0 will be reversed. For instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not; when CMP=1, the top 4-kB sector will become unprotected while the rest of the array become read-only. www.cypress.com Document No. 001-98576 Rev. *A 4 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories 2.4 Status and Configuration Registers The Status Register can be read to determine the device's ready/busy status as well as the status of many other functions such as Hardware Locking and Software Protection. The status register is referred to as SR on S25FL-P and SR1 on S25FL1-K. We will use the term SR from here on to refer to the status register. The configuration register is used instead to change some device settings and configurations. The configuration register is referred to as CR on S25FL-P and SR2 on S25FL1-K. We will use the term CR from here on to refer to the configuration register. All SR Bits except SR[5] and SR[6] provide the same information on S25FL-P and S25FL1-K. SR[5] and SR[6] are used to report erase and program errors respectively on S25FL-P while they contain TB (for the Top / Bottom selector) and SEC (for setting of Sector protection granularity) on S25FL1-K respectively. Therefore, a software change might be needed here to stop using SR[5] and SR[6] bits for error reporting and make a correct use of them if needed. CR[0] and CR[1] provide the same information on S25FL-P and S25FL1-K while the rest of the bits are used for different purposes. Please refer to the Table 9 and 10 for more details about those bits specific usage. A software change might also be needed here to make correct use of bits CR[2] through CR[7] if needed. Cypress S25FL1-K devices have one additional Status Register (SR3) which can be used to configure the burst wrap feature. The Write Status Register instruction allows up to three Status Registers (SR/SR1, CR/SR2 and SR3) to be written in one command sequence. The read-only Status Register bit locations will not be affected by the Write Status Register instruction. Table 7 and 9 show the S25FL-P status register (SR) and configuration register (CR) respectively while Table 8, 10 and 11 show the S25FL1-K status register-1 (SR1), status register-2 (SR2) and status register-3 (SR3) respectively. Table 7. S25FL-P Status Register (SR) Bit www.cypress.com Status Register Bit Bit Function Description 1 = Protects when W#/ACC is low 0 = No protection, even when W#/ACC is low 7 SRWD Status Register Write Disable 6 P_ERR Programming Error Occurred 0 = No Error 1 = Error occurred 5 E_ERR Erase Error Occurred 0 = No Error 1 = Error occurred 4 BP2 3 BP1 2 BP0 1 WEL Write Enable Latch 0 WIP Write in Progress Block Protect Protects selected Block from Program or Erase 1 = Device accepts Write Registers, program or erase commands 0 = Ignores Write Registers, program or erase commands 1 = Device Busy a Write Registers, program or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands Document No. 001-98576 Rev. *A 5 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 8. S25FL1-K Status Register 1 (SR1) Bits Field Name Function Default State Description 7 SRP0 Status Register Protect 0 0 0 = WP# input has no effect or Power Supply Lock Down mode 1 = WP# input can protect the Status Register or OTP Lock Down 6 SEC Sector / Block Protect 0 0 = BP2-BP0 protect 64-kB blocks 1 = BP2-BP0 protect 4-kB sectors 5 TB Top / Bottom Protect 0 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 4 BP2 Type Non-volatile and volatile versions 0 Block Protect Bits 3 BP1 2 BP0 0 000b = No protection 1 WEL Write Enable Latch Volatile, Read only 0 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 BUSY Embedded Operation Status Volatile, Read only 0 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress 0 Table 9. S25FL-P Configuration Register (CR) Bit Bit Name Bit Function Description 7 NA - Not Used 6 NA - Not Used 5 TBPROT Configures start of block protection 1 = Bottom Array (low address) 0 = Top Array (high address) (Default) 4 NA - Do Not Use 3 BPNV Configures BP2-0 bits in the Status Register 1 = Volatile 0 = Non-volatile (Default) 2 TBPARM Configures Parameter sector location 1 = Top Array (high address) 0 = Bottom Array (low address) (Default) 1 QUAD Puts the device into Quad I/O mode 1 = Quad I/O 0 = Dual or Serial I/O (Default) 0 FREEZE Locks BP2-0 bits in the Status Register 1 = Enabled 0 = Disabled (Default) Table 10. S25FL1-K Status Register 2 (SR2) www.cypress.com Bits Field Name Function Type Default State 7 SUS Suspend Status Volatile, Read Only 0 0 = Erase / Program not suspended 1 = Erase / Program suspended 6 CMP Complement Protect Non-volatile and volatile versions 0 0 = Normal Protection Map 1 = Inverted Protection Map 5 LB3 4 LB2 3 LB1 2 LB0 0 Security Register Lock Bits OTP 0 0 1 Description OTP Lock Bits 3:0 for Security Registers 3:0 0 = Security Register not protected 1 = Security Register protected Security register 0 contains the Serial Flash Discoverable Parameters and is always programmed and locked by Cypress. Document No. 001-98576 Rev. *A 6 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 10. S25FL1-K Status Register 2 (SR2) Bits Field Name 1 QE Function Type Quad Enable Default State Description 0 0 = Quad Mode Not Enabled, the WP# pin and HOLD# are enabled 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and WP# and HOLD# functions are disabled 0 0 = SRP0 selects whether WP# input has effect on protection of the status register 1 = SRP0 selects Power Supply Lock Down or OTP Lock Down mode Non-volatile and volatile versions 0 SRP1 Status Register Protect 1 Table 11. S25FL1-K Status Register 3 (SR3) Bits Field Name Function 7 RFU Reserved 6 W6 5 W5 Type Burst Wrap Length Default State 0 Reserved for Future Use 1 00 = 8-byte wrap. Data read starts at the initial address and wraps within an aligned 8-byte boundary 01 = 16-byte wrap. Data read starts at the initial address and wraps within an aligned 16-byte boundary. 10 = 32-byte wrap. Data read starts at the initial address and wraps within an aligned 32-byte boundary. 11 = 64-byte wrap. Data read starts at the initial address and wraps within an aligned 64-byte boundary. 1 Volatile W4 Burst Wrap Enable Latency Control (LC) Variable Read Latency Control 4 1 3 2 1 0 0 0 0 3 3.1 Description 0 0 = Wrap Enabled 1 = Wrap Disabled Defines the number of read latency cycles in Fast Read, Dual Out, Quad Out, Dual IO, and Quad IO commands. Binary values for 1 to 15 latency cycles. A value of zero disables the variable latency mode. Software Considerations S25FL-P versus S25FL1-K Command Set Comparison S25FL-P and S25FL1-K have a wide range of common instructions (op-codes) in their command-set. While Cypress S25FL1-K devices have some additional commands that are related to Erase/Program Suspend/ Resume and Burst Read mode, S25FL-P Devices have additional commands for 8-kB sector erase (P8E), quad page programming (QPP) and clearing the status register (CLSR). Table 12 shows a comparison summary of the command set of S25FL-P and S25FL1-K device families. Table 12. Command Set of S25FL-P and S25FL1-K (Sheet 1 of 2) Name www.cypress.com Description S25FL032P S25FL064P S25FL132K S25FL164K READ Read Data (Single output) 03H 03H FAST_READ Fast Read (Single output) 0BH 0BH DOR Dual Output Fast Read 3BH 3BH QOR Quad Output Fast Read 6BH 6BH DIOR Dual I/O Fast read BBH BBH QIOR Quad I/O Fast read EBH EBH RDID Read Identification (JEDEC) 9FH 9FH Document No. 001-98576 Rev. *A 7 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 12. Command Set of S25FL-P and S25FL1-K (Sheet 2 of 2) Name READ_ID Description S25FL032P S25FL064P S25FL132K S25FL164K 90H 90H Read Mfg. ID and device ID Set Burst with Wrap - 77H Continuous Read Mode Reset - FFH WREN Write Enable 06H 06H WRDI Write Disable 04H 04H - 50H 20H 20H Write Enable for volatile status Reg. P4E 4-kB Sector Erase P8E 8-kB Sector Erase 40H - SE 64-kB Block Erase D8H D8H BE Bulk Erase C7H, 60H C7H, 60H - 75H - 7AH 02H 02H Erase/Program Suspend Erase/Program Resume PP QPP DP RES RES RDSR Page Program Quad Page Programming 32H - Deep Power-Down B9H B9H Release from Deep Power-Down ABH ABH ABH ABH Release from Deep Power-Down / Read Electronic Signature Read Status Register / Status Register-1 05H 05H RCR Read Configuration Register / Status Register-2 35H 35H - 33H WRR Write Status Register 01H 01H CLSR Clear Status Register 30H - Read SFDP Register - 5AH Read Security Registers - 48H Erase Security Registers - 44H Read Status Register-3 Program Security Registers 3.2 - 42H OTPR Read OTP 4BH - OTPP Program OTP 42H - OTP Related Commands The OTP (One Time Programmable) area is a specific region that can be used to store a serial number or a security-oriented key. The S25FL-P has a 506 Bytes (33 Regions) OTP area: Two 8-byte (ESN), thirty 16-byte, and one 10-byte regions that can be individually locked. Cypress factory programs and locks the lower 8-byte ESN with a 64-bit unique number. The upper 8-byte ESN is left blank for customer use or, if ordered, Cypress can program (and lock) in a unique customer ID. The thirty 16-byte and one 10-byte OTP regions are for customer usage and can be individually locked by the end user. On the other hand, the S25FL1-K family provides four 256-byte Security Registers. Each register can be used to store information that can be permanently protected by programming One Time Programmable (OTP) lock bits in Status Register-2 (LB3, LB2 and LB1). Security register 0 is used by Cypress to store and protect the Serial Flash Discoverable Parameters (SFDP) information that is also accessed by the Read SFDP command. The three additional Security Registers can be erased, programmed, and protected individually. These registers may be used by system manufacturers to store and permanently protect security or other important information separate from the main memory array. Since S25FL-P and S25FL1-K present different OTP layouts, software changes are needed to correctly use the OTP feature. Table 13 lists the OTP commands of both S25FL-P and S25FL1-K devices. www.cypress.com Document No. 001-98576 Rev. *A 8 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Table 13. OTP Commands S25FL032P S25FL064P S25FL132K S25FL164K Read Security Registers - 48H Erase Security Registers - 44H Program Security Registers - 42H Name 4 4.1 Description OTPR Read OTP 4BH - OTPP Program OTP 42H - Timing Considerations Power-Up Timing One of the most sensitive electrical specifications is the power-up timing needed to correctly initialize the device. Figure 2 and Table 14 show the power-up characteristics of both S25FL-P and S25FL1-K devices. Figure 2. Power-Up Timing Diagram VCC VCC (max) Program, Erase, and Write instructions are ignored CS# must track VCC VCC (min) t VSL Reset State Read instructions allowed Device is fully accessible VWI t PUW Time Table 14. S25FL-P and S25FL1-K Power-Up Timing Requirements Parameter S25FL-P Symbol S25FL1-K Min Max Min Max Units tVSL - (1) - (1) 10 - µs Delay before Program or Erase tPU/tPUW - 0.3 1 10 ms Write Inhibit Threshold Voltage tWI 2.3 2.4 1.0 2.0 V VCC (min) to CS# Low Note: 1. Those parameters are not described in the corresponding data sheets. It is important to note that the power-up parameters of the S25FL1-K family members are more restrictive. In particular, the delay before the system issues the first Program/Erase operation (tVSL) needs to be up to 30 times longer. On the other hand, writes are inhibited already at 2.3V for the S25FL-P, while S25FL1-K allows writing down to 2.0V. www.cypress.com Document No. 001-98576 Rev. *A 9 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories 4.2 Data in Setup/Hold Time Two AC timing parameters that are critical in SPI designs are Data In Setup Time and Data In Hold Time. They specify how long data needs to be valid before and after the rising edge of the clock signal, respectively. Table 15 shows the Data in Setup/Hold timing characteristics for both S25FL-P and S25FL1-K devices. Table 15. Data in Setup/Hold Timing Characteristics Parameter Symbol S25FL032P S25FL064P S25FL116K S25FL132K Units Data In Setup Time (Min) tDVCH/tSU 3 2 ns Data In Hold Time (Min) tCHDX/tHD 2 5 ns The S25FL-P and S25FL1-K Devices have very similar timing. The minor difference should not impact design but may need to be verified. 4.3 Further Timing Comparison In general, the timing characteristics of both S25FL-P and S25FL1-K are almost identical. Another example is the CS# deselect time which is approximately the same for both device families. Table 16 shows a comparison between S25FL-P and S25FL1-K with regards to the various CS# deselect times. Table 16. CS# Deselect Time Characteristics Parameter Symbol S25FL-P S25FL1-K Units CS# deselect time between Reads (Min) tSHSL1/tCS1 10 7 ns CS# deselect time for Read after Writes (Min) tSHSL2/tCS2 50 40 ns Since the timing requirement is less restrictive for FL1-K devices, there is no need to apply any changes here. 5 Conclusion Similar pinout, packages, command set and sector architecture make migrating from S25FL-P to the S25FL1-K straightforward although it can require some accommodation with regard to the system software. Software changes should be considered when using the following features: Sub-sectors erase commands (20H/40H) OTP feature Detecting errors in embedded operations with Status Register bits SR[5] and SR[6] Configuration Register bits CR[2] through CR[7] Once accommodations are made, S25FL1-K flash will enable access to a superior read throughput up to 54 Mbytes/s using Quad bit data path. www.cypress.com Document No. 001-98576 Rev. *A 10 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Document History Page Document Title: AN98576 - Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Document Number: 001-98576 Rev. ECN No. Orig. of Change 4928028 MSWI ** *A www.cypress.com Submission Date Description of Change 12/17/2012 Initial version 09/21/2015 Updated in Cypress template Document No. 001-98576 Rev. *A 11 Migration from S25FL-P to S25FL1-K Cypress SPI Flash Memories Worldwide Sales and Design Support Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. 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The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-98576 Rev. *A 12