AN98519 Vcc Ramp Rate for MirrorBit® Multi I/O SPI Family Author: Ted Eiden Associated Part Family: S25FL-P AN98519 discusses the power-on requirements for Cypress's 90-nm S25FL-P product family. 1 Introduction Electronic products are expected to begin operating shortly after they are powered on. To meet this expectation, each semiconductor device used in these products is also designed to become operational shortly after power is applied. To become ready for use, the device executes a planned power-on initialization sequence. This initialization sequence is unique to each semiconductor device and ranges from simple to complex. As a requirement to the proper execution of the power-up sequence, power applied through the VCC and GND pins needs to follow certain necessary rules. There are limits to how quickly the VCC ramp rises from its idle value of 0V to its specified target value of VCC. In addition another specification may delay access to the device after Vcc has risen above a minimum level to allow for the initialization sequence to be executed. The power-on requirements for Cypress's 90 nm S25FL-P product family will be documented within this Application Note. 2 Cypress 90 nm MirrorBit Multi-I/O SPI Family Cypress has released its 90 nm MirrorBit Multi-I/O SPI Family to the flash marketplace. These include devices in 32 Mb, 64 Mb, and 128 Mb densities with all three shipping in volume production today. www.cypress.com Document No. 001-98519 Rev. *A 1 Vcc Ramp Rate for MirrorBit® Multi I/O SPI Family Table 1. Cypress Multi I/O SPI Flash Family Device Density Clock Frequency Voltage S25FL032P 32 Mb 104 MHz (single I/O), 80 MHz (dual & quad I/ O) 2.7 - 3.6V Uniform 64 KB with optional 4 KB or 8 KB sub-sectors SOIC-8, SOIC-16, WSON-8, USON8, BGA-24 S25FL064P 64 Mb 104 MHz (single I/O), 80 MHz (dual & quad I/ O) 2.7 - 3.6V Uniform 64 KB with optional 4 KB or 8 KB sub-sectors SOIC-16, WSON8, BGA-24 (1) 128 Mb 104 MHz (single I/O) 2.7 - 3.6V Uniform 64 KB or 256 KB SOIC-16, WSON8 S25FL129P 128 Mb 104 MHz (single I/O), 80 MHz (dual & quad I/ O) 2.7 - 3.6V Uniform 64 KB with optional 4 KB or 8 KB sub-sectors or Uniform 256 KB SOIC-16, WSON8, BGA-24 S25FL128P Sector Architecture Package Note: 1. Single I/O 3 Cypress FL-P VCC Ramp Rate Specifications New specifications are being communicated with respect to VCC ramp rates on Cypress's S25FL-P SPI Flash Product Family. A VCC ramp rate is defined to be the time elapsed during which VCC rises from VSS (0V) to VCC (3V) divided by the VCC voltage increase (3V). The VCC ramp rate during power-up for the FL-P products is specified to be between 8 µs/V and 1s/V in order to ensure proper device operation. In addition, a delay of tPU, specified to be a minimum of 300 µs for the S25FL-P family, must be met before access to the device is allowed. Figure 1 below for further detail. After the power-up sequence has completed, the flash device will go to standby mode and wait for user commands. Figure 1. Power Up Timing Diagram VCC VCC(max) VCC(min) tPU Full Device Access Time 4 Summary In summary, the VCC ramp rate for the Cypress 90nm MirrorBit Multi-I/O SPI Family has been documented here. Given that the VCC ramp rate and the tPU specifications are met, electronic systems using this device will be able to rely on proper operation of the SPI flash device. www.cypress.com Document No. 001-98519 Rev. *A 2 Vcc Ramp Rate for MirrorBit® Multi I/O SPI Family Document History Page Document Title: AN98519 - Vcc Ramp Rate for MirrorBit® Multi I/O SPI Family Document Number: 001-98519 Rev. ECN No. Orig. of Change 4928061 MSWI ** *A www.cypress.com Submission Date Description of Change 06/23/2010 Initial version 09/21/2015 Updated in Cypress template Document No. 001-98519 Rev. *A 3 Vcc Ramp Rate for MirrorBit® Multi I/O SPI Family Worldwide Sales and Design Support Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. 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The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-98519 Rev. *A 4