PIC32MX320/340/360/440/460 Family Silicon Errata and Data Sheet Clarification

PIC32MX320/340/360/440/460
PIC32MX320/340/360/440/460 Family
Silicon Errata and Data Sheet Clarification
The PIC32MX320/340/360/440/460 family devices that
you have received conform functionally to the current
Device Data Sheet (DS60001143J), except for the anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC32MX320/340/360/440/460
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (C0).
Data Sheet clarifications and corrections start on page
23, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® X IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB X IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
5.
Note:
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB X IDE project.
Configure the MPLAB X IDE project for the
appropriate device and hardware debugger.
Select Window > Dashboard, and then click
the Refresh Debug Tool Status icon
(
).
The part number and the Device and
Revision ID values appear in the Output
window.
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The Device and Revision ID values for the various
PIC32MX320/340/360/440/460 silicon revisions are
shown in Table 1.
TABLE 1:
SILICON DEVREV VALUES
Part Number
Revision ID for Silicon Revision(1)
Device ID(1)
B2
B3
B4
B6
C0
PIC32MX360F512L
0x0938053
PIC32MX360F256L
0x0934053
PIC32MX340F128L
0x092D053
PIC32MX320F128L
0x092A053
PIC32MX340F512H
0x0916053
PIC32MX340F256H
0x0912053
PIC32MX340F128H
0x090D053
0x3
0x4
0x5
0x5
0x6
PIC32MX320F128H
0x090A053
PIC32MX320F064H
0x0906053
PIC32MX320F032H
0x0902053
PIC32MX460F512L
0x0978053
PIC32MX460F256L
0x0974053
PIC32MX440F128L
0x096D053
Note 1: Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001143J) for detailed information on Device and Revision IDs for your specific device.
 2009-2016 Microchip Technology Inc.
DS80000440M-page 1
PIC32MX320/340/360/440/460
TABLE 1:
SILICON DEVREV VALUES (CONTINUED)
Revision ID for Silicon Revision(1)
Device ID(1)
Part Number
B2
B3
B4
B6
C0
PIC32MX440F256H
0x0952053
PIC32MX440F512H
0x0956053
0x3
0x4
0x5
0x5
0x6
PIC32MX440F128H
0x094D053
PIC32MX420F032H
0x0942053
Note 1: Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001143J) for detailed information on Device and Revision IDs for your specific device.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
#
Affected
Revisions(1)
Issue Summary
B2 B3 B4 B6 C0
Device
Reset
1.
A Reset (MCLR) Pulse that is shorter than 2 SYSCLK
will not reset the device properly.
X
X
X
X
X
MCLR
Device
Reset
—
2.
All Resets, except Power-on Reset (POR), can cause
a Fail-Safe Clock Monitor event (if enabled) when the
duration of the Reset pulse exceeds the clock period
of the internal fail-safe clock reference clock (31 kHz).
X
X
X
X
X
Device
Reset
Software Reset
3.
Attempting to perform a software device Reset with
PBDIV set to 1:1, and SYSCLK less than 1 MHz will
not reset the device properly.
X
X
X
X
X
External
Voltage
Regulator
—
4.
A VDDCORE voltage less than 1.75V will cause the
CPU to reset when using an external core voltage
supply.
X
X
X
X
X
ADC
Gain and Offset
Errors
5.
When running the Analog-to-Digital Converter (ADC)
module in Internal Reference mode, the gain error is
3-4 LSb and the offset error is 1-2 LSb across voltage
and speed.
X
X
X
X
X
Bus Matrix
Configuration
6.
The BMXDUDBA, BMXDUPBA and BMXPUPBA
registers can be set to values that are outside the
device’s actual memory size limit.
X
X
X
X
X
Oscillator
Clock Fail
Detect
7.
After a clock failure event, any write to the OSCCON
register erroneously clears the fail-safe condition and
attempts to switch to a new clock source that is
specified by the NOSC bits in the OSCCON register.
X
X
X
X
X
DMA
Pattern Match
Mode
8.
In Pattern Match mode, the DMA will generate up to
three additional byte writes to the destination address,
after the Pattern Detection event has occurred, when
performing transfers with the DCHxSSIZ set to greater
than 1.
X
X
X
X
X
Output
Compare
PWM Mode
9.
The Output Compare module in PWM mode outputs a
high of period register (PRx) length when attempting to
use PWM values of 0x00 followed by 0x01.
X
X
X
X
X
PMP
Slave Mode
10.
In PMP Slave 4B Buffer mode, if the underflow Status
bit OBF (PMSTAT<6>) is cleared at the same time a
PMP read is attempted, the PMP could receive
incorrect data.
X
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000440M-page 2
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
#
Affected
Revisions(1)
Issue Summary
B2 B3 B4 B6 C0
I/O Ports
—
11.
When using the hardware assisted read-modify-write
registers, PORTxINV, PORTxSET and PORTxCLR,
the source used for the operation is the LATx register,
not the PORTx register.
X
X
X
X
X
Timers
—
12.
The TMRx register stays at zero for two timer clock
cycles when the PRx register is 0x0000.
X
X
X
X
X
Timers
—
13.
The timer prescaler may not be reset correctly when it
is used with a slow external clock.
X
X
X
X
X
Timers
Asynchronous
Mode
14.
The Timer1 prescaler may not be reset correctly when
it is used with a slow external clock.
X
X
X
X
X
UART
Hardware
Handshake
Mode
15.
The CTS pin does not deassert until at least 2 bytes
are free in the UART FIFO.
X
X
X
X
X
Watchdog
Timer
(WDT)
—
16.
An incorrect WDT Time-out Reset may occur.
X
X
X
X
X
DMA
Channel Abort
17.
DMA channel abort on a channel that is not currently
active may have unintended effects on other active
channels.
X
X
X
X
X
Oscillator
Operating
Condition
18.
The Primary Oscillator Circuit (POSC), when using XT,
XTPLL, HS and HSPLL modes, does not operate over
the voltage and temperature range that is listed as
item D5 in the device data sheet.
X
X
X
X
X
PMP
Wait States
19.
The WAITE field in PMMODE<1:0> does not add a
Wait state to PMP master reads when it is
programmed to the value ‘01’.
X
X
X
X
X
UART
Baud Rate
Generator
20.
Using BRG values of 0, 1 or 2 cause the Start bit to be
shortened.
X
X
X
X
X
Input
Capture
16-bit Mode
with DMA
21.
16-bit DMA transfers from the ICAP module FIFO
buffer do not advance the ICAP FIFO pointer.
X
X
X
X
X
USB
Speed Switch
22.
The USB module does not correctly switch from fullspeed to low-speed after sending a PRE packet to a
hub.
X
X
X
X
X
DMA
Breakpoints
23.
The DMA buffer may be erroneously filled with the last
data read prior to the breakpoint.
X
X
X
X
X
PMP
DMA Read
24.
Events can be missed if the PMDIN register is used as
the DMA source or destination and the PMP IRQ is
used as the DMA trigger.
X
X
X
X
X
Input
Capture
—
25.
When in 16-bit mode, the upper 16 bits of the 32-bit
ICxBUF register contain Timer3 values.
X
X
X
X
X
ICSP™
Programming
26.
When programming the PIC32 using the 2-wire PGC
and PGD pins, programming data appears as an
output on the JTAG TDO pin.
X
X
X
X
X
UART
High-Speed
Mode
27.
In BRGH = 1 mode, the received data is not sampled
in the middle of the bit.
X
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
 2009-2016 Microchip Technology Inc.
DS80000440M-page 3
PIC32MX320/340/360/440/460
TABLE 2:
Module
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Item
#
Affected
Revisions(1)
Issue Summary
B2 B3 B4 B6 C0
Oscillator
Clock Out
28.
A clock signal is present on the CLKO pin, regardless
of the clock source and setting of the CLKO Enable
Configuration bit, under certain conditions.
X
X
X
X
X
ADC
—
29.
Enabling the primary programming/debug port (PGC1/
PGD1) on 64 lead variants disables the external and
internal references for the ADC, making the ADC
unusable.
X
X
X
X
X
Oscillator
Clock Switch
30.
Firmware clock switch requests to switch from FRC
mode, after a FSCM event, may fail.
X
X
X
X
X
USB
5V Tolerance
31.
The D+ and D- pins are not 5V tolerant.
X
X
USB
SE0 Transition
Detection
32.
The single-ended comparator detects SE0 transitions
at a voltage higher than the USB specification.
X
X
Prefetch
Cache
—
33.
If the Predictive Prefetch Cache Enable bits
(PREFEN<1:0>) in the CHECON register are nonzero, improper processor behavior may occur during a
rare boundary condition.
X
Flash
Program
Memory
Programming
Operation
34.
NVM registers must not be written immediately after a
programming operation is complete.
X
ADC
Signal Source
35.
When the ADC is in operation, the current channel is
shorted to VREF during the conversion period (12 TAD)
after sampling.
X
Timers
—
36.
Writes to the timer registers PRx and TIMERx through
the Set/Clear/Invert registers corrupts the data written.
X
X
X
X
X
USB
Clock
37.
The USB clock does not automatically suspend when
entering Sleep mode.
X
X
X
X
X
UART
—
38.
The TRMT bit is asserted before the transmission is
complete.
X
X
X
X
X
Output
Compare
Fault Mode
39.
PWM fault override is not asynchronous.
X
X
X
X
X
SPI
—
40.
The SPIBUSY and SRMT bits assert 1 bit time before
the end of the transaction.
X
X
X
X
X
Output
Compare
—
41.
Faults may be cleared erroneously due to an aborted
read.
X
X
X
X
X
USB
—
42.
The TOKBUSY bit does not correctly indicate status
when a transfer completes within the Start of Frame
(SOF) threshold.
X
X
X
X
X
USB
—
43.
The interval between the first two SOF packets
generated does not meet USB specification.
X
X
X
X
X
Output
Compare
—
44.
If firmware clears a PWM Fault while a Fault condition
is asserted, an interrupt will not be generated for the
current Fault.
X
X
X
X
X
Oscillator
Clock Switch
45.
Clock switching and Two-Speed Start-up may cause a
general exception when the reserved bit 8 of the
DDPCON register is ‘0’.
X
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000440M-page 4
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
#
Affected
Revisions(1)
Issue Summary
B2 B3 B4 B6 C0
UART
—
46.
The RXDA bit does not correctly reflect the RX FIFO
status after an overrun event.
X
X
X
X
X
DMA
CRC Append
Mode
47.
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
X
X
X
X
X
Oscillator
Clock Switch
48.
Clock source switching may cause a general
exception or a POR when switching from a slow clock
to a fast clock.
X
X
X
X
X
JTAG
—
49.
On 64-pin devices, the TMS pin requires an external
pull-up.
X
X
X
X
X
Oscillator
—
50.
Changing the PB divisor on the fly may generate
exceptions.
X
X
X
X
X
DMA
—
51.
A suspend followed by an abort does not reset the
DMA pointers.
X
X
X
X
X
DMA
—
52.
Turning off DMA during a transfer may have
unintended results.
X
X
X
X
X
PMP
Slave Mode
53.
The PMP interrupt is generated at the start of the PMP
write.
X
X
X
X
X
PMP
Slave Mode
54.
The IBOV overflow flag may not become set when an
overflow occurs.
X
X
X
X
X
DMA
—
55.
The channel event bit may be incorrect after a
suspend.
X
X
X
X
X
DMA
—
56.
DMA events are not detected during a DMA suspend.
X
X
X
X
X
SPI
—
57.
Reads of SPIxBUF when SPIRBF is clear will cause
erroneous SPIRBF behavior.
X
X
X
X
X
SPI
Slave Mode
58.
A wake-up interrupt may not be clearable.
X
X
X
X
X
UART
IrDA®
59.
TX data is corrupted when BRG values greater than
0x200 are used.
X
X
X
X
X
UART
IrDA
60.
The IrDA minimum bit time is not detected at all baud
rates.
X
X
X
X
X
RTCC
—
61.
The RTCC alarm registers are reset by any device
Reset.
X
X
X
X
X
Ports
—
62.
I/O pins do not tri-state immediately if previously driven
high.
X
X
X
X
X
UART
UART Receive
Buffer Overrun
Error Status
63.
The OERR bit does not get cleared on a module
Reset. The OERR bit retains its value even after the
UART module is reinitialized.
X
X
X
X
X
ADC
Conversion
Trigger from
INT0 Interrupt
64.
The ADC module conversion triggers occur on the
rising edge of the INT0 signal even when INT0 is
configured to generate an interrupt on the falling edge.
X
X
X
X
X
Comparator
Voltage
Reference
65.
The Internal Voltage Reference (IVREF) is set to 1.2V
(typical) instead of 0.6V as specified in the device data
sheet electrical specifications.
X
Voltage
Regulator
BOR
66.
Device may not exit BOR state if BOR event occurs.
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
 2009-2016 Microchip Technology Inc.
DS80000440M-page 5
PIC32MX320/340/360/440/460
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
#
Affected
Revisions(1)
Issue Summary
B2 B3 B4 B6 C0
2
2
I C™
Slave Mode
67.
The I C module does not respond to address 0x78
when the STRICT and A10M bits are cleared in the
I2CxCON register.
X
X
X
X
X
USB
UIDLE Interrupt
68.
UIDLE interrupts cease if the UIDLE interrupt flag is
cleared.
X
X
X
X
X
CPU
Constant Data
Access from
Flash
69.
A Data Bus Exception (DBE) may occur if an interrupt
is encountered by the CPU while it is accessing
constant data from Flash memory.
X
X
X
X
X
CPU
Data Write to a
Peripheral
70.
A data write operation by the CPU to a peripheral may
be repeated if an interrupt occurs during initial write
operation.
X
X
X
X
Flash
Program
Memory
Erase/
Programming
Operation
71.
A CPU data corruption may occur after a Flash erase
or programming operation is complete if either the
Prefetch module or CPU cache functionality are
enabled.
X
X
X
X
X
USB
Host
72.
The USB bus might not be returned to the J-state
following an acknowledgment packet when running
low-speed through a hub.
X
X
X
X
X
Non-5V
Tolerant
Pins
Pull-ups
73.
Internal pull-up resistors may not guarantee a logical
‘1’ on non-5V tolerant pins when they are configured
as digital inputs.
X
X
X
X
5V Tolerant
Pins
Pull-ups
74.
Internal pull-up resistors may not guarantee a logical
‘1’ on 5V tolerant pins when they are configured as
digital inputs.
X
X
X
X
X
I2C
Slave
Addresses
75.
When the I2C module is operating as a Slave, some
reserved bus addresses may be Acknowledged
(ACKed) when they should be not Acknowledged
(NAKed).
X
X
X
X
X
UART
Synchronization
76.
On a RX FIFO overflow, shift registers stop receiving
data, which causes the UART to lose synchronization.
X
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000440M-page 6
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
4. Module: External Voltage Regulator
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (C0).
A VDDCORE voltage less than 1.75V will cause the
CPU to reset when using an external core voltage
supply.
Work arounds
Work around 1:
Use the internal voltage regulator.
1. Module: Device Reset
Work around 2:
A Reset (MCLR) Pulse that is shorter than
2 SYSCLK will not reset the device properly.
Work around
Ensure that the device is held in Reset for more
than 2 SYSCLK to ensure proper device Reset
operation.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
2. Module: Device Reset
All Resets, except Power-on Reset, can cause a
Fail-Safe Clock Monitor event (if enabled) when
the duration of the Reset pulse exceeds the clock
period of the internal fail-safe clock reference clock
(31 kHz).
Use an external 1.8V regulator, which has a
regulation specification of  2.5%. The Microchip
TC1055-1.8VCT713 Low Drop-Out (LDO)
regulator, or an equivalent, is recommended.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
5. Module: ADC
When running the Analog-to-Digital Converter
(ADC) module in Internal Reference mode, the
gain error is 3-4 LSb and the offset error is 1-2 LSb
across voltage and speed.
Work around
Use in-system calibration and software techniques
to compensate for these errors.
Affected Silicon Revisions
Work around
If long Reset pulses are anticipated, ignore or
disable Fail-Safe Clock Monitor events.
B2
B3
B4
B6
C0
X
X
X
X
X
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
3. Module: Device Reset
Attempting to perform a software device Reset
with PBDIV set to 1:1, and SYSCLK less than
1 MHz will not reset the device properly.
Work arounds
Work around 1:
6. Module: Bus Matrix
The BMXDUDBA, BMXDUPBA and BMXPUPBA
registers can be set to values that are outside the
device’s actual memory size limit.
Work around
Do not write values greater than the specified
memory size of the device to the Bus Matrix
registers. Ensure that the upper bits of the
registers remain clear (‘0’).
Affected Silicon Revisions
Change PBDIV before performing a software
Reset.
Work around 2:
B2
B3
B4
B6
C0
X
X
X
X
X
Set SYSCLK to a value that is greater than 1 MHz.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
DS80000440M-page 7
PIC32MX320/340/360/440/460
7. Module: Oscillator
9. Module: Output Compare
After a clock failure event, any write to the
OSCCON register erroneously clears the fail-safe
condition and attempts to switch to a new clock
source that is specified by the NOSC bits in the
OSCCON register.
The Output Compare module in PWM mode
outputs a high of period register (PRx) length when
attempting to use PWM values of 0x00 followed by
0x01.
Work around
Do not use a PWM value of 0x01.
After a clock failure event, perform the following
steps:
Affected Silicon Revisions
1. Write ‘000’ to the NOSC bits in the OSCCON
register to select the Fast RC oscillator. This
will ensure that an erroneous clock switch
selects the known good on-chip Fast RC
oscillator.
2. Modify the OSCCON register with any value
your application requires.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
8. Module: DMA
In Pattern Match mode, the DMA will generate up
to three additional byte writes to the destination
address, after the Pattern Detection event has
occurred, when performing transfers with the
DCHxSSIZ set to greater than 1.
Work arounds
Work around 1:
Work around
B2
B3
B4
B6
C0
X
X
X
X
X
10. Module: PMP
In PMP Slave 4B Buffer mode, if the underflow
Status bit OBF (PMSTAT<6>) is cleared at the
same time a PMP read is attempted, the PMP
could receive incorrect data.
Work around
The CPU can read the underflow flag OBUF and
set/clear an I/O pin for the external master device
to read. The state of the pin should indicate to the
external master device that an underflow has
occurred and no additional reads should occur
until the underflow status has been cleared by the
CPU.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
The destination buffer needs to be large enough to
accommodate the extra bytes (up to 3 extra bytes).
Work around 2:
Set the destination size register to 1.
Work around 3:
Set the source size register to 1.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 8
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
11. Module: I/O Ports
13. Module: Timers
When using the hardware assisted read-modifywrite registers, PORTxINV, PORTxSET and
PORTxCLR, the source used for the operation is
the LATx register, not the PORTx register. This
only affects users who want to use the pins in a
bidirectional mode or to store sampled PORTx
data in the LATx register.
Work around
Use a software read-modify-write sequence, such
as:
//replaces PORTAINV = mask;
x = PORTA ^ mask;
LATA = x;
//replaces PORTASET = mask;
x = PORTA | mask;
LATA = x;
//replaces PORTACLR = mask;
x = PORTA & ~mask;
LATA = x;
Note:
These sequences are not atomic.
Affected Silicon Revisions
The timer prescaler may not be reset correctly
when it is used with a slow external clock. This can
occur when the timer is disabled and then reenabled. The result could be a spurious count in
the prescaler.
Work around
To ensure a Reset of the prescaler, firmware
must wait for at least 2 input clock periods
before re-enabling the timer.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
14. Module: Timers
The Timer1 prescaler may not be reset correctly
when it is used with a slow external clock. This can
occur when the timer is disabled and then reenabled. The result could be a spurious count in
the prescaler.
Work around
None.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
B2
B3
B4
B6
C0
X
X
X
X
X
12. Module: Timers
The TMRx register stays at zero for two timer clock
cycles when the PRx register is 0x0000.
Work around
15. Module: UART
The CTS pin does not deassert until at least 2
bytes are free in the UART FIFO.
Work around
None.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
The UART TXREG must be read at least 2 times
to rearm the hardware handshaking lines.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 9
PIC32MX320/340/360/440/460
16. Module: Watchdog Timer (WDT)
An incorrect WDT Time-out Reset may occur
when both of these conditions are present:
1. WDT is enabled.
2. Either a MCLR (EXTR) or Software Reset
(SWR) occurs just before WDT is about to
expire.
Work around
To detect incorrect WDT Time-out Reset, always
confirm that only the WDTO bit is set in the RCON
register. If EXTR, SWR, or any other Reset bits are
set, it indicates that an incorrect WDT has
occurred.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
17. Module: DMA
DMA channel abort on a channel that is not
currently active may have unintended effects on
other active channels.
Work around
1. Suspend the channel, rather than abort, by
clearing
the
channel
enable
bit
DCHxCON<CHEN>.
2. Wait until other DMA channels complete
before issuing the abort.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
18. Module: Oscillator
The Primary Oscillator Circuit (POSC), when using
XT, XTPLL, HS and HSPLL modes, does not
operate over the voltage and temperature range
that is listed as item D5 in the device data sheet.
The operation range without the work around is
limited to -40°C through +70°C when VDD < 3.0V.
19. Module: PMP
The WAITE field in PMMODE<1:0> does not add
a Wait state to PMP master reads when it is
programmed to the value ‘01’. The WAITE field
allows Wait states to be added to the end of PMP
read/write operations. This field is intended to add
the following Wait clocks after the read operation
completes:
00 – no Wait states
01 – 1 Wait state
10 – 2 Wait states
11 – 3 Wait states
Current behavior is the following:
00 – no Wait states
01 – no Wait states
10 – 2 Wait states
11 – 3 Wait states
Work around
This erratum only applies to PMP master read
operations. PMP writes work correctly. Use
another Wait state control value that is allowed for
the attached device.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
20. Module: UART
Using BRG values of 0, 1 or 2 cause the Start bit
to be shortened. This results in errors when
receiving the data. This issue exists for BRGH
values of ‘0’ and ‘1’.
Work around
Do not use BRG values of 0, 1 or 2. Select system
and peripheral bus clocks’ frequencies such that
the BRG value for the desired Baud Rate
Generator value is greater than 2.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Work around
Install a 4.1 M resistor in parallel with the crystal.
This allows operation across the temperature
range that is listed in the data sheet.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 10
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
21. Module: Input Capture
23. Module: DMA
16-bit DMA transfers from the ICAP module FIFO
buffer do not advance the ICAP FIFO pointer. This
results in the entire DMA output buffer being filled
with the first value from the ICAP FIFO.
Work around
Configure the DMA to perform 32-bit transfers
from the ICAP FIFO.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
22. Module: USB
The USB module does not correctly switch from
full-speed to low-speed after sending a PRE
packet to a hub.
Work around
The DMA buffer may be erroneously filled with the
last data read prior to the breakpoint. This buffer fill
will continue until the DMA buffer is full. However,
the DMA buffer fills correctly if those same
peripherals are used as DMA destinations, even
when the CPU goes into Debug Exception mode.
This behavior occurs when the DMA controller is
actively transferring data and a debugger hits a
breakpoint, causes a single-step operation, or
halts the target.
Refer to Table 3, which lists the peripherals and
input registers that could affect DMA buffer usage.
TABLE 3: REGISTERS AND
PERIPHERALS AFFECTED BY
BREAKPOINTS DURING DMA
TRANSFERS
Peripheral as DMA
Source
Transfer from
Input Register
Change Notice
PORTx
Connect a low-speed device directly to the PIC32.
SPI
SPIxBUF
PMP
PMDIN
UART
UxRXREG
Input Capture
ICxBUF
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Work around
If the debugger halts during a DMA transfer from
one of these registers, either ignore the DMA
transferred data or restart the debug session.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
24. Module: PMP
Events can be missed if the PMDIN register is
used as the DMA source or destination and the
PMP IRQ is used as the DMA trigger.
Work around
Do not use DMA for PMP read or write operations.
Affected Silicon Revisions
 2009-2016 Microchip Technology Inc.
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 11
PIC32MX320/340/360/440/460
25. Module: Input Capture
When in 16-bit mode, the upper 16 bits of the
32-bit ICxBUF register contain Timer3 values.
Work around
Mask the upper 16 bits of the read value.
Example: result = 0xFFFF & IC1BUF
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
28. Module: Oscillator
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), under any of the following
conditions.
1. During a Power-on Reset.
2. During device programming.
3. After a JTAG erase. A clock is present on the
CLKO pin until the Configuration bit to disable
CLOCKOUT is programmed.
Work around
26. Module: ICSP™
When programming the PIC32 using the 2-wire
PGC and PGD pins, programming data appears
as an output on the JTAG TDO pin.
Work around
Do not connect the TDO pin to a device that would
be adversely affected by rapid pin toggling during
programming.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
27. Module: UART
In BRGH = 1 mode, the received data is not
sampled in the middle of the bit. This reduces the
UART’s baud rate mismatch tolerance.
Work around
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
29. Module: ADC
Enabling the primary programming/debug port
(PGC1/PGD1) on 64-lead variants disables the
external and internal references for the ADC,
making the ADC unusable.
Work around
Use the secondary programming/debug port.
Use BRGH = 0 mode.
Affected Silicon Revisions
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
B2
B3
B4
B6
C0
X
X
X
X
X
30. Module: Oscillator
After a Fail-Safe Clock Monitor (FSCM) event, the
clock source will be FRC. Firmware clock switch
requests to switch from FRC mode after an FSCM
event may fail. If the clock switch does fail,
subsequent retries by firmware will also fail and
the clock source will be FRC.
Work around
None.
Affected Silicon Revisions
DS80000440M-page 12
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
31. Module: USB
34. Module: Flash Program Memory
The D+ and D- pins are not 5V tolerant. During
normal operation these pins are not subject to 5V.
The 5V tolerance specification is intended to
prevent device damage in an abnormal operation
mode such as connecting a shorted USB cable to
the device.
Work around
Do not subject D+ or D- to 5V.
Affected Silicon Revisions
B2
B3
X
X
B4
B6
C0
The single-ended comparator is detecting SE0
transitions at a higher voltage than indicated in the
USB specification. This is a compliance issue
relating to items ST2 and ST3 in the Peripheral
Silicon checklist, which may result in reduced
noise immunity.
Work around
None.
Affected Silicon Revisions
B3
X
X
B4
B6
C0
33. Module: Prefetch Cache
If the Predictive Prefetch Cache Enable bits
(PREFEN<1:0>) in the CHECON register are nonzero, improper processor behavior may occur
during a rare boundary condition. This condition
occurs only when predictive prefetch is enabled,
and can occur in both cacheable and noncacheable memory areas. The prefetch buffer can
be overwritten by the “next” 16-bytes of
instructions causing invalid instruction execution.
This may cause an invalid instruction fault, or
execution of a wrong instruction.
Work around
Make sure that the PREFEN field in CHECON is
programmed to ‘00’. The cache is still used,
although predictive prefetching will be disabled.
Affected Silicon Revisions
B2
B3
B4
Work around
Wait at least 500 ns after seeing a ‘0’ in
NVMCON<15> before writing to any NVM
registers.
32. Module: USB
B2
NVM registers must not be written immediately
after a programming operation is complete. When
a NVM operation completes, the NVMWR bit
(NVMCON<15>) switches states from ‘1’ to ‘0’,
indicating that another NVM operation may be
started. However, there is a period of two internal
FRC clocks after this transition where a write to
NVMCON may not work correctly. Since the
internal FRC clock is 8 MHz, and the system clock
may be much faster, care must be taken to ensure
that the correct delay is met.
B6
C0
X
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
35. Module: ADC
When the ADC is in operation, the current channel
is shorted to VREF during the conversion period
(12 TAD) after sampling. The impact on highimpedance sources is that they may not have time
to recover between conversions. The impact on
low-impedance sources is a high current draw,
which may damage either the source or the
device.
Work around
Place a 5k resistor between the device and any
external capacitance on the board to limit current
draw.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
36. Module: Timers
Writes to the timer registers PRx and TIMERx
through the Set/Clear/Invert registers corrupts the
data written.
Work around
Do not write to the affected Set/Clear/Invert
registers.
Use
software
read-modify-write
sequences to change individual bits or write
directly to the PRx and TIMERx registers.
Affected Silicon Revisions
 2009-2016 Microchip Technology Inc.
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 13
PIC32MX320/340/360/440/460
37. Module: USB
40. Module: SPI
The USB clock does not automatically suspend
when entering Sleep mode.
The SPIBUSY and SRMT bits assert 1 bit time
before the end of the transaction.
Note:
Work around
SPI operation with the DMA module
is not affected by this issue.
Turn off the USB clock before entering Sleep
mode.
Work arounds
Affected Silicon Revisions
Work around 1
B2
B3
B4
B6
C0
X
X
X
X
X
38. Module: UART
Firmware must provide a 1 bit time delay between
the assertion of these bits and performing any
operation that requires the transaction to be
complete.
Work around 2
The TRMT bit is asserted during the STOP bit
generation not after the STOP bit has been sent.
Work around
If firmware needs to be aware when the
transmission is complete, firmware should add a
half bit time delay after the TRMT bit is asserted.
Use the DMA module to transfer data to/from the
SPI module.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
39. Module: Output Compare
The fault override of the PWM output pin(s) does
not occur asynchronously; it is synchronized to the
PB clock. The synchronization takes up to 2 PB
clock periods for the fault event to tri-state the
PWM output pin.
Work around
41. Module: Output Compare
The Output Compare module may reinitialize or
clear a Fault on an aborted read of the OCxCON
register. An aborted read occurs when a read
instruction in the CPU pipeline has started
execution, but is aborted due to an interrupt.
Work around
Disable interrupts before reading the contents of
the OCxCON register, and then re-enable
interrupts after reading the register.
Affected Silicon Revisions
None.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
B2
B3
B4
B6
C0
X
X
X
X
X
42. Module: USB
The TOKBUSY bit does not correctly indicate
status when a transfer completes within the Start
of Frame threshold.
Work around
Use a firmware semaphore to track when a token
is written to U1TOK. Firmware then clears the
semaphore when the transfer is complete.
Affected Silicon Revisions
DS80000440M-page 14
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
43. Module: USB
46. Module: UART
The interval between the first two SOF packets
generated does not meet the USB specification.
The first count could be short due to an
uninitialized counter.
Work around
There is no work around for the non-compliant
timing. It is recommended that firmware not send
data in the first frame.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
44. Module: Output Compare
If firmware clears a PWM Fault while a Fault
condition is asserted, an interrupt will not be
generated for the current Fault.
The RXDA bit does not correctly reflect the RX
FIFO status after an overrun event.
Work around
1. Clear the OERR bit. The FIFO pointer will be
reset and the RXDA bit will reflect the current
FIFO status.
2. If the contents of the FIFO are required, they
can be read by reading the UxRXREG register
four times. There are no status bits that will
correctly reflect when the last valid data was
read.
3. Clear the OERR bit. The FIFO pointer will be
reset and the RXDA will reflect the current
FIFO status.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Work around
Firmware must poll the OCFLT bit to determine if a
Fault condition still exists.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
47. Module: DMA
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
Work around
Use firmware to read the CRC result and append
it to the result buffer.
Affected Silicon Revisions
45. Module: Oscillator
Clock switching and Two-Speed Start-up may
cause a general exception when the reserved bit 8
of the DDPCON register is ‘0’.
Work around
B2
B3
B4
B6
C0
X
X
X
X
X
48. Module: Oscillator
Ensure that the reserved bit 8 of the DDPCON
register to set to ‘1’. For example, DDPCON =
0x100.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Clock source switching may cause a general
exception or a POR when switching from a slow
clock to a fast clock.
Work around
Clock source switches should be performed by
first switching to the FRC, and then switching to
the target clock source.
Affected Silicon Revisions
 2009-2016 Microchip Technology Inc.
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 15
PIC32MX320/340/360/440/460
49. Module: JTAG
53. Module: PMP
On 64-pin devices, an external pull-up resistor is
required on the TMS pin for proper JTAG.
Work around
Connect a 100k-200k pull-up to the TMS pin.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
50. Module: Oscillator
In Slave mode, the PMP interrupt is generated at
the start of the PMP write instead of at the end of
the write generated by the master. When the
master write occurs slowly in relation to the PB
clock, it is possible for the CPU to respond to the
interrupt before the data written by the master has
been latched.
Work around
Poll the PMSTAT register in the ISR to determine
when the data is available.
Affected Silicon Revisions
Changing the PB divisor on the fly may generate
exceptions.
Work around
Ensure 8 NOP instructions precede the write to the
PBDIV bits and 8 NOP instructions follow the write
to the PBDIV bits.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
B2
B3
B4
B6
C0
X
X
X
X
X
54. Module: PMP
In Slave mode, the IBOV overflow flag may not
become set when an overflow occurs.
Work around
Do not allow the PMP buffer to overflow.
Affected Silicon Revisions
51. Module: DMA
If a DMA channel is suspend in the middle of a
transfer and an abort is issued, the channel’s
source, destination and cell pointer registers are
not reset.
Work around
Suspend the channel after the channel is aborted.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
B2
B3
B4
B6
C0
X
X
X
X
X
55. Module: DMA
The channel event bit may remain set if a transaction completes as the user suspends the channel
by clearing the corresponding CHEN bit. This has
the effect that as soon as the channel is reenabled the event that should have been cleared
after the last transfer will still be pending and the
transfer will begin immediately after the channel is
re-enabled without waiting for an interrupt.
Work around
52. Module: DMA
Turning the DMA module off while a transaction is
in progress may cause invalid instruction or data
fetches.
Work around
Ensure all DMA transactions are complete or abort
DMA transactions before turning off the DMA
module.
None.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 16
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
56. Module: DMA
59. Module: UART
DMA events are not detected during DMA
suspend. Any interrupt event that would initiate a
DMA transfer will not be captured while DMA is
suspended. When DMA is re-enabled the event
will have been lost.
Work around
Read the status of the peripheral interrupt flag. If
the interrupt has been asserted, force a DMA
transaction.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
57. Module: SPI
Reads of the SPIxBUF register when the SPIRBF
bit is clear will cause erroneous SPIRBF behavior.
Subsequent data in the buffer will not be reflected
by the SPIRBF bit.
In IrDA® mode with baud clock output enabled, the
UART TX data is corrupted when the BRG value is
greater than 0x200.
Work around
Use the Peripheral Bus (PB) divisor to lower the
PB frequency such that the required UART BRG
value is less than 0x201.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
60. Module: UART
The UART module is not fully IrDA compliant. The
module does not detect the 1.6 µs minimum bit
width at all baud rates as defined in the IrDA specification. The module does detect the 3/16 bit width
at all baud rates.
Work around
Work around
None.
Only read the SPIxBUF register when the SPIRBF
bit is set.
Affected Silicon Revisions
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
58. Module: SPI
In Slave mode when entering Sleep mode after a
SPI transfer with SPI interrupts enabled, a false
interrupt may be generated waking the device.
This interrupt can be cleared; however, entering
Sleep mode may cause the condition to occur
again.
Work around
B2
B3
B4
B6
C0
X
X
X
X
X
61. Module: RTCC
The RTCC alarm registers (RTCALRM,
ALRMTIME and ALRMDATE) are reset by any
device Reset.
Work around
For devices with code-protect disabled: If the
alarm information must be retained through a
Reset, the information must be stored in RAM or
Flash.
Affected Silicon Revisions
Do not use SPI in Slave mode as a wake-up
source from Sleep mode.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 17
PIC32MX320/340/360/440/460
62. Module: Ports
65. Module: Comparator
When an I/O pin is set to output a logic high signal,
and is then changed to an input using the TRISx
registers, the I/O pin should immediately tri-state
and let the pin float. Instead, the pin will continue
to partially drive a logic high signal out for a period
of time.
The Internal Voltage Reference (IVREF) is set to
1.2V (typical) instead of 0.6V as specified in the
device data sheet electrical specifications.
Work around
Affected Silicon Revisions
The pin should be driven low prior to being tri-stated
if it is desirable for the pin to tri-state quickly.
Work around
None.
B2
B3
B4
B6
C0
X
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
63. Module: UART
66. Module: Voltage Regulator
Device may not exit BOR state if BOR event
occurs.
Work arounds
The OERR bit does not get cleared on a module
reset. If the OERR bit is set and the module is disabled, the OERR bit retains its status even after
the UART module is reinitialized.
Work around 1:
VDD must remain within the published specification
(see parameter DC10 of the device data sheet).
Work around 2:
Work around
The user software must check this bit in the UART
module initialization routine and clear it if it is set.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
64. Module: ADC
When the ADC module is configured to start
conversion on an external interrupt (SSRC<2:0> =
001), the start of conversion always occurs on a
rising edge detected at the INT0 pin, even when
the INT0 pin has been configured to generate an
interrupt on a falling edge (INT0EP = 0).
Work around
Generate ADC conversion triggers on the rising
edge of the INT0 signal.
Alternatively, use external circuitry to invert the
signal appearing at the INT0 pin, so that a falling
edge of the input signal is detected as a rising
edge by the INT0 pin.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 18
Reset device by providing POR condition.
Affected Silicon Revisions
B2
B3
B4
B6
X
X
X
X
C0
67. Module: I2C™
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I2C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits. When both bits
are cleared, the device should respond to the
reserved address 0x78, but does not.
Work around
None.
Affected Silicon Revisions
B2
B3
B4
B6
X
X
X
X
C0
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
68. Module: USB
69. Module: CPU
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag, and the bus remains idle, the UIDLE
interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption.
(Resume, Reset, SOF, or Error).
Note:
Resume and Reset are the only interrupts
that should be following UIDLE assertion.
If the UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). This will require
software to clear the UIDLE interrupt
enable bit to exit the USB ISR (if using
interrupt driven code).
When both prefetch and instruction cache are
enabled, a Data Bus Exception (DBE) may occur if
an interrupt is encountered by the CPU while it is
accessing constant data (not instructions) from
Flash memory.
Work around
To avoid a DBE, use one of the following two
solutions:
1.
Structure application code, such that interrupts are not used while the CPU is accessing
data from Flash memory.
Disable either the Prefetch module or CPU
cache functionality as follows (by default both
are disabled on a Power-on Reset):
a) To disable the Prefetch module, set the
Predictive Prefetch Enable bits, PREFEN<1:0>, in the Cache Control Register, CHECON<6:5>, to ‘00’.
b) To disable CPU cache, set the Kseg0
bits, K0<2:0>, in the CP0 Configuration
Register, Config<2:0>, to ‘010’.
2.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
Note:
Disabling either the cache or Prefetch
module will have minimum performance
degradation, with a typical application
realizing 10 percent or less performance
impact.
Affected Silicon Revisions
 2009-2016 Microchip Technology Inc.
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 19
PIC32MX320/340/360/440/460
70. Module: CPU
71. Module: Flash Program Memory
During normal operation, if a CPU write operation
is interrupted by an incoming interrupt, it should be
aborted (not completed) and resumed after the
interrupt is serviced. However, some of these write
operations may not be aborted, resulting in a
double write to peripherals by the CPU (the first
write during the interrupt and the second write after
the interrupt is serviced).
Work around
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
However, the following communication peripherals
will double-send data if their respective transmit
buffers are written twice: SPI, I2C, UART and PMP.
To avoid double transmission of data, utilize DMA
to transfer data to these peripherals or disable
interrupts while writing to these peripherals.
If a Flash erase or programming operation is
performed while either the Prefetch module or
CPU cache functionality are enabled, a CPU data
corruption may occur immediately after either of
these operations are complete.
Work around
To avoid a CPU data corruption, disable both the
Prefetch module and CPU cache functionality
before Flash erase or programming operation as
follows (by default both are disabled on a Power-on
Reset):
1.
To disable the Prefetch module, set the
Predictive Prefetch Enable bits, PREFEN<1:0>, in the Cache Control Register,
CHECON<6:5>, to ‘00’.
To disable CPU cache, set the Kseg0 bits,
K0<2:0>, in the CP0 Configuration Register,
Config<2:0>, to ‘010’.
2.
Corrected Revisions
On corrected revisions, an interrupt occurring
during CPU write operation to a peripheral will be
delayed for up to two Peripheral Bus Clock
(PBCLK) cycles.
Both prefetch module and CPU cache functionality
can be re-enabled after Flash erase/programming
is complete.
Affected Silicon Revisions
Affected Silicon Revisions
B2
B3
B4
B6
X
X
X
X
DS80000440M-page 20
C0
B2
B3
B4
B6
C0
X
X
X
X
X
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
72. Module: USB
74. Module: 5V Tolerant Pins
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the host may persistently drive the bus to an SE0
state (both D+/D- as ‘0’), which would be
interpreted as a bus Reset condition by the hub; or
the host may persistently drive the bus to a J state,
which would make the hub detach condition
undetectable by the host.
Work around
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
available to external device inputs, may not
exceed the minimum value of VIH, and therefore,
qualify as a logic “high”. However, with respect to
PIC32 devices, so long as the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the PIC32 device.
Connect low-speed devices directly to the Host
USB port and not through a USB hub.
Work around
Affected Silicon Revisions
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA
B2
B3
B4
B6
C0
X
X
X
X
X
It is recommend to only use external pull-ups:
Affected Silicon Revisions
73. Module: Non-5V Tolerant Pins
When internal pull-ups are enabled on non-5V
tolerant pins, the level as measured on the pin and
available to external device inputs, may not
exceed the minimum value of VIH, and therefore,
qualify as a logic “high”. However, with respect to
PIC32 devices, so long as the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the PIC32 device.
B2
B3
B4
B6
C0
X
X
X
X
X
75. Module: I2C
When the I2C module is operating as a Slave,
some reserved bus addresses may be
Acknowledged (ACKed) when they should be not
Acknowledged (NAKed).
Work around
As a result, there will be multiple data NAK
interrupts until the Stop condition is asserted.
It is recommend to only use external pull-ups:
Work around
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA
When the address interrupt arrives, check the
address to determine if it is actually a reserved
address. If the address is a reserved address, set
a flag and use the flag to ignore subsequent data
interrupts. When the Stop condition occurs, clear
the flag.
Affected Silicon Revisions
B2
B3
B4
B6
X
X
X
X
C0
 2009-2016 Microchip Technology Inc.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 21
PIC32MX320/340/360/440/460
76. Module: UART
During a RX FIFO overflow condition, the shift
register stops receiving data. This causes the
UART to lose synchronization with the serial data
stream. The only way to recover from this is to turn
the UART OFF and ON until it synchronizes. This
could require several OFF/ON sequences.
Work arounds
Work around 1:
Avoid the RX overrun condition by ensuring that
the UARTx module has a high enough interrupt
priority such that other peripheral interrupt
processing latencies do not exceed the time to
overrun the UART RX buffer based on the
application baud rate. Alternately or in addition to,
set the URXISEL bits in the UxSTA register to
generate an earlier RX interrupt based on RX
FIFO fill status to buy more time for interrupt
latency processing requirements.
Work around 2:
If avoiding RX FIFO overruns is not possible,
implement a ACK/NAK software handshake
protocol to repeat lost packet transfers after
restoring UART synchronization.
Affected Silicon Revisions
B2
B3
B4
B6
C0
X
X
X
X
X
DS80000440M-page 22
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS60001143J):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
1. Module: Comparator Specifications
The minimum, typical and maximum values for the
Internal Voltage Reference (parameter D305) in
Table 29-12 were stated incorrectly in the data sheet.
The correct values are shown in bold type in Table 4.
TABLE 4:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
D305
IVREF
Characteristics
Internal Voltage Reference
Min.
Typical
Max.
Units
Comments
0.57
0.6
0.63
V
—
2. Module: Flash Program Memory
The following Note and Example will be added to
Section 5.0 “Flash Program Memory” in the
next revision of the data sheet.
Note:
Flash LVD Delay (LVDstartup) must be
considered between setting up and
executing any Flash command operation.
See Example 5-1 for a code example to
set up and execute a Flash command
operation.
EXAMPLE 5-1:
NVMCON = 0x4004;
Wait(delay);
// Enable and configure for erase operation
// Delay for 6 µs for LVDstartup
NVMKEY = 0xAA996655;
NVMKEY = 0x556699AA;
NVMCONSET = 0x8000;
// Initiate operation
while(NVMCONbits.WR==1);
// Wait for current operation to complete
 2009-2016 Microchip Technology Inc.
DS80000440M-page 23
PIC32MX320/340/360/440/460
3. Module: Pin Diagrams
In all pin diagrams in the current revision of the
data sheet, the D- and D+ pins are incorrectly
indicated as 5V-tolerant pins through the use of
shading. The D- and D+ pins are not 5V-tolerant
pins and should not be shaded in the pin diagrams.
4. Module: AC Characteristics: Standard
Operating Conditions
The Standard Operating conditions in the following
tables show the incorrect starting voltage range of
2.3V. The correct starting range is: 2.5V:
• Table 29-34: ADC Module Specifications
• Table 29-35: 10-bit ADC Conversion Rate
Parameters
• Table 29-36: Analog-to-Digital Conversion
Timing Requirements
DS80000440M-page 24
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
5. Module: DC Characteristics: I/O Pin Input
Specifications
Certain specifications in Table 29-8 were stated incorrectly in the data sheet. The correct values are shown
in bold type in the following table.
TABLE 29-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VIH
Characteristics
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-temp
Min.
Typical(1)
Max.
Units
Conditions
Input High Voltage
I/O Pins not 5V-tolerant(5)
0.65 VDD
—
VDD
V
(Note 4,6)
I/O Pins 5V-tolerant with
PMP(5)
0.25 VDD + 0.8V
—
5.5
V
(Note 4,6)
I/O Pins 5V-tolerant(5)
0.65 VDD
—
5.5
V
DI28
SDAx, SCLx
0.65 VDD
—
5.5
V
SMBus disabled
(Note 4,6)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V  VPIN  5.5
(Note 4,6)
DI20
DI30
ICNPU
Change Notification
Pull-up Current
—
—
-50
A
VDD = 3.3V, VPIN = VSS
(Note 3, 6)
DI31
ICNPD
Change Notification
Pull-down Current(4)
—
50
—
µA
VDD = 3.3V, VPIN = VDD
Note 1:
2:
3:
4:
5:
6:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
See the “Pin Diagrams” section for the 5V-tolerant pins.
The VIH specification is only in relation to externally applied inputs and not with respect to the userselectable pull-ups. Externally applied high impedance or open drain input signals utilizing the
PIC32 internal pull-ups are guaranteed to be recognized as a logic “high” internally to the PIC32
device, provided that the external load does not exceed the maximum value of ICNPU.
 2009-2016 Microchip Technology Inc.
DS80000440M-page 25
PIC32MX320/340/360/440/460
6. Module: DC Characteristics: Program
Memory
Certain specifications in Table 29-11 were stated
incorrectly in the data sheet. The correct values
are shown in bold type in the following table.
TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
—
E/W
—
Program Flash Memory(3)
D130
EP
Cell Endurance
1000
—
D130a EP
Cell Endurance
20,000
—
—
E/W
D131
VPR
VDD for Read
2.3
—
3.6
V
D132
See Note 4
—
VPEW
VDD for Erase or Write
3.0
—
3.6
V
D132a VPEW
VDD for Erase or Write
2.3
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year
Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
—
TWW
Word Write Cycle Time
—
411
—
Time(2)
—
See Note 4
FRC Cycles See Note 4
D136
TRW
Row Write Cycle
—
26067
—
FRC Cycles See Note 4
D137
TPE
Page Erase Cycle Time
—
201060
—
FRC Cycles See Note 4
TCE
Chip Erase Cycle Time
—
804652
—
FRC Cycles See Note 4
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
This parameter depends on the FRC accuracy (see Table 31-19) and the FRC tuning values (see
Register 8-2).
DS80000440M-page 26
 2009-2016 Microchip Technology Inc.
PIC32MX320/340/360/440/460
APPENDIX A:
REVISION HISTORY
Updated silicon issue 69 (CPU) and 70 (CPU).
Rev A Document (4/2009)
Initial release of this document; issued for revision B2,
B3, and B4 silicon.
Includes silicon issues 1 (Device Reset), 2-3 (Device
Reset), 4 (External Voltage Regulator), 5 (ADC), 6 (Bus
Matrix), 7 (Oscillator), 8 (DMA), 9 (Output Compare), 10
(PMP), 11 (I/O Ports), 12-14 (Timers), 15 (UART), 16
(Watchdog Timer (WDT)), 17 (DMA), 18 (Oscillator), 19
(PMP), 20 (UART), 21 (Input Capture), 22 (USB), 23
(DMA), 24 (PMP), 25 (Input Capture), 26 (ICSP™), 27
(UART), 28 (Oscillator), 29 (ADC), 30 (Oscillator), 31-32
(USB), 33 (Prefetch Cache), 34 (Flash Program Memory) and 35 (ADC), and data sheet clarification 1 (D+ and
D- Inputs).
This document
documents:
replaces
Rev H Document (4/2012)
the
following
errata
• DS80350, “PIC32MX320/340/360/440/460 Rev.
B2 Silicon Errata”
• DS80367, “PIC32MX320/340/360/440/460 Rev.
B3 Silicon Errata”
• DS80402, “PIC32MX320/340/360/440/460 Rev.
B4 Silicon Errata”
Added silicon issue 72 (USB).
Rev J Document (10/2012)
Updated silicon issue 40 (SPI).
Updated the note in the Silicon DEVREV Values table
(see Table 1).
Rev K Document (4/2013)
Added silicon issues 73 (Non-5V Tolerant Pins) and
74 (5V Tolerant Pins).
Added data sheet clarifications 5 (DC Characteristics:
I/O Pin Input Specifications) and 6 (DC Characteristics:
Program Memory).
Rev L Document (1/2014)
Updated current silicon revision to C0.
Updated silicon issue 70 (CPU).
Rev M Document (4/2016)
Added silicon issues 75 (I2C) and 76 (UART).
Rev B Document (9/2010)
Updated silicon issue 24 (PMP).
Added silicon issues 36 (Timers), 37 (USB),
38 (UART), 39 (Output Compare), 40 (SPI), 41 (Output
Compare), 42-43 (USB), 44 (Output Compare), 45
(Oscillator), 46 (UART), 47 (DMA), 48 (Oscillator), 49
(JTAG), 50 (Oscillator), 51-52 (DMA), 53-54 (PMP),
55-56 (DMA), 57-58 (SPI), 59-60 (UART), 61 (RTCC),
62 (Ports) and 63 (UART).
Removed data sheet clarification 1; data sheet was
updated.
Rev C Document (11/2010)
Updated current silicon revision to B6.
Added silicon issues 64 (ADC) and 65 (Comparator), and
data sheet clarification 1 (Comparator Specifications).
Rev D Document (12/2010)
Added silicon issue 66 (Voltage Regulator).
Rev E Document (3/2011)
Added data sheet clarification issues 2 (Revision History)
and 3 (Revision History).
Rev F Document (10/2011)
Added silicon issues 67 (I2C™) and 68 (USB).
Added data sheet clarification issue 4 (Revision History).
Rev G Document (2/2012)
Updated silicon issue 28 (Oscillator).
Added silicon issues 69 (CPU), 70 (CPU), and 71 (Flash
Program Memory).
 2009-2016 Microchip Technology Inc.
DS80000440M-page 27
PIC32MX320/340/360/440/460
NOTES:
DS80000440M-page 28
 2009-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0459-0
DS80000440M-page 29
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS80000440M-page 30
 2009-2016 Microchip Technology Inc.