PIC32MX1XX/2XX 28/36/44-PIN
PIC32MX1XX/2XX 28/36/44-pin Family
Silicon Errata and Data Sheet Clarification
The PIC32MX1XX/2XX 28/36/44-pin family devices that
you have received conform functionally to the current
Device Data Sheet (DS60001168J), except for the
anomalies described in this document.
The errata described in this document will be addressed
in future revisions of the PIC32MX1XX/2XX 28/36/44pin silicon.
Note:
The silicon revision level can be identified using the
current version of MPLAB® X IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB X IDE in conjunction with a hardware
debugger:
The silicon issues discussed in the
following pages are for silicon revisions
with the Device and Revision IDs listed in
Table 1 through Table 4. The last column
of each table represents the latest silicon
revision for the devices listed. The silicon
issues are summarized in Table 5.
1.
2.
3.
4.
Data Sheet clarifications and corrections start on page
12, following the discussion of silicon issues.
5.
Note:
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB X IDE project.
Configure the MPLAB X IDE project for the
appropriate device and hardware debugger.
Select Window > Dashboard, and then click
the Refresh Debug Tool Status icon
(
).
The part number and the Device and
Revision ID values appear in the Output
window.
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The Device and Revision ID values for the various
silicon revisions are provided in Table 1 through
Table 4.
TABLE 1:
SILICON DEVREV VALUES FOR DEVICES WITH 16/32 KB FLASH
Part Number
PIC32MX110F016B
Device ID(1)
A0
A1
0x0
0x1
0x4A07053
PIC32MX110F016C
0x4A09053
PIC32MX110F016D
0x4A0B053
PIC32MX210F016B
0x4A01053
PIC32MX210F016C
0x4A03053
PIC32MX210F016D
0x4A05053
PIC32MX120F032B
0x4A06053
PIC32MX120F032C
0x4A08053
PIC32MX120F032D
0x4A0A053
PIC32MX220F032B
0x4A00053
PIC32MX220F032C
0x4A02053
PIC32MX220F032D
0x4A04053
Note 1:
Revision ID for Silicon Revision(1)
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revision IDs for your specific device.
2011-2016 Microchip Technology Inc.
DS80000531H-page 1
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 2:
SILICON DEVREV VALUES FOR DEVICES WITH 64/128 KB FLASH
Part Number
Device ID(1)
Revision ID for Silicon Revision(1)
A0
PIC32MX130F064B
0x4D07053
PIC32MX130F064C
0x4D09053
PIC32MX130F064D
0x4D0B053
PIC32MX230F064B
0x4D01053
PIC32MX230F064C
0x4D03053
PIC32MX230F064D
0x4D05053
PIC32MX150F128B
0x4D06053
PIC32MX150F128C
0x4D08053
PIC32MX150F128D
0x4D0A053
PIC32MX250F128B
0x4D00053
PIC32MX250F128C
0x4D02053
PIC32MX250F128D
0x4D04053
A1
A3
0x3
0x0
0x1
—
Note 1:
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revision IDs for your specific device.
TABLE 3:
SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH AND 64 KB RAM
Part Number
Device ID(1)
PIC32MX170F256B
0x6610053
PIC32MX170F256D
0x661A053
PIC32MX270F256B
0x6600053
PIC32MX270F256D
0x660A053
PIC32MX270F256DB
0x660C053
Revision ID for Silicon Revision(1)
A1
A2
0x1
0x2
Note 1:
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revision IDs for your specific device.
TABLE 4:
SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH AND 16 KB RAM
Part Number
Device ID(1)
Revision ID for Silicon Revision(1)
A0
PIC32MX130F256B
0x6703053
PIC32MX130F256D
0x6705053
PIC32MX230F256B
0x6700053
PIC32MX230F256D
0x6702053
Note 1:
0x0
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revision IDs for your specific device.
DS80000531H-page 2
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 5:
SILICON ISSUE SUMMARY
Affected Device
Module
Feature
Voltage
Regulator
Oscillator
I2C
USB
ADC
ADC
Legend:
BOR
Clock Switch
Slave Mode
UIDLE Interrupt
N/A
CTMU
Calibration
Item
1.
2.
3.
4.
5
6.
Issue Summary
Device may not exit Brown-out Reset (BOR)
state if a BOR event occurs.
If a Fail-Safe Clock Monitor (FSCM) event
occurs when Primary Oscillator (POSC) mode
is used, firmware clock switch requests to
switch from FRC mode will fail.
The I2C module does not respond to address
0x78 when the STRICT and A10M bits are
cleared in the I2CxCON register.
UIDLE interrupts cease if the UIDLE interrupt
flag is cleared.
The DNL parameter of the ADC module is
not within the published data sheet
specifications when the ADC module is
operating at maximum conversion rate.
Open selection for Channel 0 positive input
is not functional.
Silicon
Flash
Data
Revision
Memory Memory
(KB)
(KB)
A0 A1 A2 A3
16/32
4/8
X
—
64
16
X
—
128
32
X
—
—
256
16
—
—
256
64
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
—
128
32
—
—
256
16
—
—
256
64
—
—
—
—
—
—
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
2011-2016 Microchip Technology Inc.
DS80000531H-page 3
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 5:
SILICON ISSUE SUMMARY (CONTINUED)
Affected Device
Module
Feature
Conversion
Trigger from
INT0 Interrupt
ADC
Parallel
Master Port
(PMP)
RA0 and RA1
Pins
I/O Ports
Data Write to a
Peripheral
CPU
Oscillator
Input Capture
Legend:
Address Pins
Clock Out
Idle Mode and
Sleep Mode
Item
7.
8.
9.
Issue Summary
The ADC module conversion triggers occur
on the rising edge of the INT0 signal even
when INT0 is configured to generate an
interrupt on the falling edge.
When the Parallel Master Port (PMP)
module is enabled, address pins cannot be
used as GPIO output pins.
When I2C1 is enabled, all digital output-only
functions and all analog functions on pins
RA0 and RA1 do not function correctly.
A data write operation by the CPU to a
10. peripheral may be repeated if an interrupt
occurs during initial write operation.
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of
11.
the CLKO Enable Configuration bit, during a
Power-on Reset (POR) condition.
All input capture modes selectable by
ICM<2:0>, with the exception of Interrupt12. only mode, will not work when the CPU
enters Idle mode or Sleep mode.
Silicon
Data
Flash
Revision
Memory Memory
(KB)
(KB)
A0 A1 A2 A3
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
—
—
—
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
DS80000531H-page 4
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 5:
SILICON ISSUE SUMMARY (CONTINUED)
Affected Device
Module
Feature
Watchdog
Timer (WDT)
Non-5V
Tolerant Pins
5V Tolerant
Pins
I/O Ports
I/O Ports
I/O Ports
Legend:
Windowed
Mode
Pull-ups
Pull-ups
Open Drain
RB5 and RB6
Pins
Analog Inputs
Item
13.
Issue Summary
The Watchdog Timer may issue a reset even
if the user tries to clear the module within the
allowed window.
Internal pull-up resistors may not guarantee
14. a logical ‘1’ on non-5V tolerant pins when
they are configured as digital inputs.
Internal pull-up resistors may not guarantee
15. a logical ‘1’ on 5V tolerant pins when they
are configured as digital inputs.
The Open Drain selection (ODCx) on I/O port
pins is not available when the pin is
16.
configured for anything other than a standard
port output.
When the I2C2 module is enabled, all digital
output-only functions and all analog
17.
functions on pins RB5 and RB6 do not
function correctly.
Certain functions are not available when
18. using PGED3/PGEC3 or PGED4/PGEC4
while in Debug mode.
Silicon
Data
Flash
Revision
Memory Memory
(KB)
(KB)
A0 A1 A2 A3
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
—
—
—
—
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
2011-2016 Microchip Technology Inc.
DS80000531H-page 5
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 5:
SILICON ISSUE SUMMARY (CONTINUED)
Affected Device
Module
UART
Timer1
Flash
Memory
Flash
Memory
Flash
Memory
Flash
Memory
Legend:
Feature
Synchronization
Interrupts
Write Protection
Write Protection
Write Protection
Write Protection
Item
Issue Summary
On a RX FIFO overflow, shift registers stop
19. receiving data, which causes the UART to
lose synchronization.
Timer1 will not generate interrupts with an
20. external asynchronous clock input and
prescaler other than 1:1.
The Program Write Protection (PWP) bits are
21. not enabled unless the Boot Write Protect
(BWP) bit is also enabled.
When enabled, the Boot Write Protect
(BWP) bit also protects and overlaps the first
22.
page of user program space below 0x0400 in
addition to the boot segment.
The Program Write Protection (PWP) bit field
23. is off by one page relative to the definition in
the data sheet.
Attempts to protect the entire Flash memory
24. using the following values, will result in no
pages being protected.
Silicon
Data
Flash
Revision
Memory Memory
(KB)
(KB)
A0 A1 A2 A3
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
16/32
4/8
X
X
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
—
—
—
—
—
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
DS80000531H-page 6
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
TABLE 5:
SILICON ISSUE SUMMARY (CONTINUED)
Affected Device
Module
PowerSaving
Modes
CTMU
I2C
Legend:
Feature
Idle
Temperature
Measurement
Slave
Addresses
Item
Issue Summary
On exit from Sleep mode, the SLEEP and
25. IDLE status bits in the RCON register are
being set.
The CTMU internal temperature sensing
26. diode does not function for VDD/AVDD
operating voltages that are less than 2.5V.
When the I2C module is operating as a
Slave, some reserved bus addresses may
27.
be Acknowledged (ACKed) when they
should be not Acknowledged (NAKed).
Silicon
Data
Flash
Revision
Memory Memory
(KB)
(KB)
A0 A1 A2 A3
16/32
4/8
X
X
—
—
64
16
X
X
—
X
128
32
X
X
—
—
256
16
X
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
—
X
X
—
16/32
4/8
X
X
—
—
64
16
X
X
—
128
32
X
X
—
—
256
16
—
—
—
256
64
X
X
—
—
An ‘X’ indicates the issue is present in this revision of silicon;
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
Blank cells indicate an issue has been corrected in this revision of silicon.
2011-2016 Microchip Technology Inc.
DS80000531H-page 7
PIC32MX1XX/2XX 28/36/44-PIN
Silicon Errata Issues
Note 1: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
The table provided in each issue indicates which issues exist for a particular revision of silicon based on
Flash memory size.
2: The following applies to the Affected Silicon Revision tables in each silicon issue:
• An ‘X’ indicates the issue is present in this revision of silicon
• Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue
• Blank cells indicate an issue has been corrected or does not exist in this revision of silicon
1. Module: Voltage Regulator
2. Module: Oscillator
Device may not exit the Brown-out Reset (BOR)
state if a BOR event occurs.
Reset the device by providing the Power-on Reset
(POR) condition.
If the Primary Oscillator (POSC) mode is
implemented and a Fail-Safe Clock Monitor
(FSCM) event occurs (failure of the external
primary clock), the internal clock source will switch
to the FRC oscillator. Subsequent firmware clock
switch requests from the FRC oscillator to other
clock sources will fail and the device will continue
to execute on the FRC oscillator. On repair of the
external clock source and a power-on state, the
device will resume operation with the primary
oscillator clock source.
Affected Silicon Revisions
Work around
Work arounds
Work around 1:
VDD must remain within the published specification
(see parameter DC10 of the device data sheet).
Work around 2:
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
DS80000531H-page 8
Device Silicon Revision
None.
Affected Silicon Revisions
A0
A1
X
X
X
—
—
A2
—
—
—
—
A3
—
—
—
—
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
3. Module: I2C
5. Module: ADC
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I2C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
Affected Silicon Revisions
16/32
64
128
256
256
4/8
16
32
16
64
Work around
Configure the ADC module to operate for a
maximum conversion rate of 500 ksps.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
None.
Device
Data
Flash
Memory
Memory
(KB)
(KB)
If the ADC module is configured to operate at a
maximum conversion rate of 1.1 Msps, missing
codes are possible every 25 codes and the DNL
parameter will not be within the published
specification.
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
6. Module: ADC
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag and the bus remains idle, the UIDLE
interrupt flag will not be set again.
If the ADC module is used in conjunction with the
CTMU module in Absolute Capacitive/Time
Measurement mode, Channel 0 positive input
must remain open (CH0SA<3:0> = 1111 or
CH0SB<3:0> = 1111) during the calibration step.
However, open selection for Channel 0 positive
input is not functional and connects this input to
AVSS.
Work around
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption (i.e.,
Resume, Reset, SOF, or Error).
Connect the ADC module to any unused pin and
perform the CTMU calibration step. This
connection will add a small amount of additional
capacitance, but will have minimal impact on
overall measurements.
4. Module: USB
Note:
Resume and Reset are the only interrupts that should be following UIDLE
assertion. If the UIDLE bit is set, it
should be okay to suspend the USB
module (as long as this code is protected by the GUARD and/or ACTPEND logic). This will require
software to clear the UIDLE interrupt
enable bit to exit the USB ISR (if
using interrupt driven code).
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
—
—
—
—
—
—
—
—
—
—
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
2011-2016 Microchip Technology Inc.
DS80000531H-page 9
PIC32MX1XX/2XX 28/36/44-PIN
7. Module: ADC
9. Module: I/O Ports
When the ADC module is configured to start
conversion
on
an
external
interrupt
(SSRC<2:0> = 001), the start of conversion
always occurs on a rising edge detected at the
INT0 pin, even when the INT0 pin has been
configured to generate an interrupt on a falling
edge (INT0EP = 0).
Work around
Generate ADC conversion triggers on the rising
edge of the INT0 signal.
Alternately, use external circuitry to invert the
signal appearing at the INT0 pin, so that a falling
edge of the input signal is detected as a rising
edge by the INT0 pin.
16/32
64
128
256
256
4/8
16
32
16
64
Digital output VOH/IOH does not meet the
specification in the data sheet and analog signal
input loading increases with an increase in applied
voltage on any enabled analog function on RA0/
RA1. If I2C1 is enabled, any analog or digital
output-only function enabled on RA0/RA1 will also
cause a corresponding 40 mA/pin increase in IDD.
Work around
Disable slew rate control of the I2C1 module by
setting the DISSLW bit (I2C1CON<9>) = 1.
Affected Silicon Revisions
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
When I2C1 is enabled, all digital output-only
functions and all analog functions on pin RA0 and
RA1 do not function correctly.
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
8. Module: Parallel Master Port (PMP)
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
10. Module: CPU
If the PMP module is enabled, any pin with a PMP
addressing capability (PMAx) cannot be used as a
general purpose output pin, even when the
corresponding PTEN<10:0> bit in the PMAEN
register is cleared. All other functionality on these
pins, including GPIO input functionality is not
affected.
During normal operation, if a CPU write operation
is interrupted by an incoming interrupt, it should be
aborted (not completed) and resumed after the
interrupt is serviced. However, some of these write
operations may not be aborted, resulting in a
double write to peripherals by the CPU (the first
write during the interrupt and the second write after
the interrupt is serviced).
Work around
Work around
To use a GPIO pin as an output when this pin is
shared with PMP addressing functionality and
PMP is enabled, do the following:
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
However, the following communication peripherals
will double-send data if their respective transmit
buffers are written twice: SPI, I2C, UART, and
PMP. To avoid double transmission of data, utilize
DMA to transfer data to these peripherals or
disable interrupts while writing to these
peripherals.
1.
2.
Enable PMP addressing by setting the
corresponding PTEN<10:0> bit in the
PMAEN register.
Instead of using corresponding LATx
registers to output GPIO data, use the
PMADDR register.
Affected Silicon Revisions
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
DS80000531H-page 10
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
11. Module: Oscillator
13. Module: Watchdog Timer (WDT)
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), during a Power-on Reset
(POR) condition.
When the Watchdog Timer module is used in
Windowed mode, the module may issue a reset
even if the user tries to clear the module within the
allowed window.
Work around
None.
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
All input capture modes selectable by ICM<2:0>,
with the exception of Interrupt-only mode, will not
work when the CPU enters Idle or Sleep mode.
Configure the Input Capture module for Interruptonly mode (ICM<2:0> = 111) when the CPU is in
Sleep or Idle mode.
Affected Silicon Revisions
4/8
16
32
16
64
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
When internal pull-ups are enabled on non-5V
tolerant pins, the level as measured on the pin and
available to external device inputs may not exceed
the minimum value of VIH, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as VDD 3V and the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
Work around
16/32
64
128
256
256
Affected Silicon Revisions
14. Module: Non-5V Tolerant Pins
12. Module: Input Capture
Device
Data
Flash
Memory
Memory
(KB)
(KB)
Work around
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
2011-2016 Microchip Technology Inc.
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or VDD < 3V
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
DS80000531H-page 11
PIC32MX1XX/2XX 28/36/44-PIN
15. Module: 5V Tolerant Pins
17. Module: I/O Ports
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
available to external device inputs may not exceed
the minimum value of VIH, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as VDD 3V and the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or VDD < 3V
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
When the I2C2 module is enabled, all digital
output-only functions and all analog functions on
pins RB5 and RB6 do not function correctly.
Digital output (VOH/IOH) does not meet the
specifications in the data sheet, and analog signal
input loading increases with an increase in applied
voltage on any enabled analog function on the
RB5 and RB6 pins. If the I2C2 is enabled, any
analog or digital output-only function enabled on
the RB5 and RB6 pins will also cause a
corresponding ~40 mA/pin increase in IDD.
Work around
Disable the I2C2 module slew rate by setting the
DISSLW bit in the I2C2CON register = 1.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
18. Module: I/O Ports
16. Module: I/O Ports
The Open Drain selection (ODCx) on I/O port pins
is not available when the pin is configured for
anything other than a standard port output. In
addition, the Open Drain feature is not available for
dedicated or remappable Peripheral Pin Select
(PPS) output features.
Work around
Affected Silicon Revisions
16/32
64
128
256
256
4/8
16
32
16
64
When using the PGED3/PGEC3 pins while
debugging, these functions are not available:
• VREF+/CVREF+/AN0/C3INC
• VREF-/CVREF-/AN1.
On 44-pin devices, when using the PGED4/
PGEC4 pins while debugging, these functions are
not available:
None.
Device
Data
Flash
Memory
Memory
(KB)
(KB)
Certain functions are not available when using
PGED3/PGEC3 or PGED4/PGEC4 while in
Debug mode.
Device Silicon Revision
• AN6
• AN7
A0
A1
A2
A3
Work around
X
X
X
X
X
X
—
—
—
—
—
—
Use either the PGED1/PGEC1 pin pair or the
PGED2/PGEC2 pin pair for debugging.
—
—
—
—
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
DS80000531H-page 12
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
19. Module: UART
20. Module: Timer1
During a RX FIFO overflow condition, the shift
register stops receiving data. This causes the
UART to lose synchronization with the serial data
stream. The only way to recover from this is to turn
the UART OFF and ON until it synchronizes. This
could require several OFF/ON sequences.
Work arounds
Work around 1:
Avoid the RX overrun condition by ensuring that
the UARTx module has a high enough interrupt
priority such that other peripheral interrupt
processing latencies do not exceed the time to
overrun the UART RX buffer based on the
application baud rate. Alternately or in addition to,
set the URXISEL bits in the UxSTA register to
generate an earlier RX interrupt based on RX
FIFO fill status to buy more time for interrupt
latency processing requirements.
Work around 2:
If avoiding RX FIFO overruns is not possible,
implement a ACK/NAK software handshake
protocol to repeat lost packet transfers after
restoring UART synchronization.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
Timer1 will not generate interrupts with an external
asynchronous clock input and prescaler other than
1:1.
Work around
With external clock asynchronous mode, use 1:1
prescaler mode with a software timer overflow
variable to keep track of desired equivalent > 1:1
prescaler setting. Alternately, use external
synchronous clock mode if this is an option for the
application.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
21. Module: Flash Memory
The Program Write Protection (PWP) bits
(DEVCFG0<18:10>) are not enabled unless the
Boot Write Protect (BWP) bit (DEVCFG0<24> is
also enabled (i.e., = 0).
Work around
None.
Please refer to silicon issues 22, 23, and 24 for
related information.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
2011-2016 Microchip Technology Inc.
Device Silicon Revision
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
DS80000531H-page 13
PIC32MX1XX/2XX 28/36/44-PIN
22. Module: Flash Memory
23. Module: Flash Memory
When enabled, the Boot Write Protect (BWP) bit
inadvertently also protects and overlaps the first
page of PWP user program space below 0x0400,
(i.e., PWP<8:0> = 0x1FE), in addition to the boot
segment, regardless of the state of the Program
Write Protection (PWP) bits (DEVCFG0<18:10>).
If Boot Write Protect is enabled by setting the BWP
bit (DEVCFG0<24>) = 0, users will not be able to
Page Erase or program the first page of the PWP
user program space. Only user run-time Page
Erase/Program operations are affected, which
does not include a Bulk erase of the entire Flash.
Work around
None.
Please refer to silicon issues 21., 23., and 24. for
related information
The Program Write Protection (PWP) bit field is off
by one page relative to the data sheet definition. In
silicon, PWP<8:0> = (n + 1), where ‘n’ is the
DEVCFG0<18:10> value as defined in the data
sheet.
TABLE 6:
PWP BITS (DEVCFG0<18:10>)
Value
Expected
111111111 Disabled
Disabled
111111110 Memory below
0x400 is writeprotected
Disabled
111111101 Memory below
0x800 is writeprotected
Memory below
0x400 is writeprotected
•
•
•
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
Actual
011111111 Memory below
0x40000 is writeprotected
Memory below
0x3FC00 is writeprotected
Work around
Set the PWP<8:0> bits (DEVCFG0<18:10>) =
{DEVCFG0<PWP> - 1} to correct for the first page
protection offset. Please refer to silicon issues
21., 22., and 24. for related information.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
DS80000531H-page 14
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
24. Module: Flash Memory
25. Module: Power-Saving Modes
Attempts to protect the entire Flash memory using
the following values, will result in no pages being
protected.
On exit from Sleep mode, both the SLEEP and
IDLE status bits in the RCON register are set.
Program Write Protection bits (DEVCFG0<PWP>):
Add the following code to the user application at
the point it wakes from Sleep mode:
111101111 = Memory below 0x4000 (16K)
address is write-protected.
Work around
101111111 = Memory below 0x20000 (128K)
address is write-protected.
rcon_var1 = RCON;
// ... enter Sleep mode
if (rcon_var1 & 0x4) Nop();
// If IDLE bit already set previously
// before sleep do nothing
else RCONbits.IDLE = 0x0;
// If IDLE bit is not set previously
// and is after Sleep mode then clear
Work around
Affected Silicon Revisions
111011111 = Memory below 0x8000 (32K)
address is write-protected.
110111111 = Memory below 0x10000 (64K)
address is write-protected.
To protect the entire Flash including the last page,
use the following values:
DEVCFG0<PWP>:
111110000 = Memory below 0x4000 (16K)
address is write-protected.
111100000 = Memory below 0x8000 (32K)
address is write-protected.
111000000 = Memory below 0x10000 (64K)
address is write-protected.
10000000 = Memory below 0x20000 (128K)
address is write-protected.
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
—
X
X
X
—
X
—
—
—
—
X
—
X
—
—
—
26. Module: CTMU
Please refer to silicon issues 21., 22., and 23. for
related information.
The CTMU internal temperature sensing diode
does not function for VDD/AVDD operating voltages
that are less than 2.5V.
Affected Silicon Revisions
Work around
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
None.
Affected Silicon Revisions
A0
A1
A2
A3
X
X
X
X
X
X
—
—
—
—
—
—
—
2011-2016 Microchip Technology Inc.
—
—
—
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
X
—
—
—
—
X
—
—
—
—
—
DS80000531H-page 15
PIC32MX1XX/2XX 28/36/44-PIN
27. Module: I2C
When the I2C module is operating as a Slave,
some reserved bus addresses may be
Acknowledged (ACKed) when they should be not
Acknowledged (NAKed).
As a result, there will be multiple data NAK
interrupts until the Stop condition is asserted.
Work around
When the address interrupt arrives, check the
address to determine if it is actually a reserved
address. If the address is a reserved address, set
a flag and use the flag to ignore subsequent data
interrupts. When the Stop condition occurs, clear
the flag.
Affected Silicon Revisions
Device
Data
Flash
Memory
Memory
(KB)
(KB)
16/32
64
128
256
256
4/8
16
32
16
64
DS80000531H-page 16
Device Silicon Revision
A0
A1
A2
A3
X
X
X
X
X
X
—
X
—
—
—
—
X
—
—
—
—
—
2011-2016 Microchip Technology Inc.
PIC32MX1XX/2XX 28/36/44-PIN
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS60001168J):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
No data sheet clarifications to be reported in this
revision.
2011-2016 Microchip Technology Inc.
DS80000531H-page 17
PIC32MX1XX/2XX 28/36/44-PIN
APPENDIX A:
REVISION HISTORY
Rev A Document (10/2011)
Initial release of this document; issued for revision
A0 silicon.
Includes silicon issues 1 (Voltage Regulator),
2 (Oscillator), 3 (I2C), 4 (USB), 5 (ADC), 6 (ADC),
7 (ADC), 8 (Parallel Master Port (PMP)), and 9 (I/O
Ports).
Rev G Document (4/2015)
Updated the Rev A3 Silicon DEVREV Values for
Devices with 64/128 KB Flash in Table 2.
Updated the title of Table 3 to: Silicon DEVREV
Values for Devices with 256 KB Flash and 64 KB
RAM.
Added Silicon DEVREV Values for Devices with 256
KB Flash and 16 KB RAM (Table 4).
Added silicon revision A1 for 16/32 KB Flash devices.
Updated the Affected Revisions for 256 KB Flash
Memory devices in Table 5 and in silicon issues
22 (Flash Memory) and 23 (Flash Memory).
Added 64/128 KB Flash devices.
Updated issue 9 (I/O Ports).
Added silicon issues 10 (CPU) and 11 (Oscillator).
Added Silicon Issues 25 (Power-Saving Modes) and
26 (CTMU).
Rev B Document (2/2012)
Rev C Document (4/2012)
Updated silicon issue 10 (CPU).
Added silicon issue 12 (Input Capture).
Rev D Document (10/2012)
Updated silicon issue 6 (ADC).
Added silicon issue 13 (Watchdog Timer (WDT)).
Updated the note in the Silicon DEVREV Values tables
(see Table 1 and Table 2).
Added Data Sheet Clarification 1 (Power-Down
Current (IPD)).
Rev H Document (4/2016)
Removed Data Sheet Clarification 1.
Added the PIC32MX270FDB device to TABLE 3:
“Silicon DEVREV Values for Devices with 256 KB
Flash and 64 KB RAM”.
Added silicon issue 27 (I2C).
Rev E Document (4/2013)
Updated the Device ID for the PIC32MX150F128B in
Table 2.
Updated silicon issue 9 (I/O Ports).
Added silicon issues 14 (Non-5V Tolerant Pins) and
15 (5V Tolerant Pins).
Added data sheet clarification 1 (The following typographic corrections and clarifications are to be noted
for the latest version of the device data sheet
(DS60001168J):).
Rev F Document (6/2014)
Updated Device ID values in Table 1, Table 2, and
Table 3.
Added Silicon DEVREV Values for Devices with
256 KB Flash (see Table 3).
Removed Data Sheet Clarification 1.
Updated silicon issue 9 (I/O Ports).
Added silicon issues 16 (I/O Ports), 17 (I/O Ports),
18 (I/O Ports), 19 (UART), 20 (Timer1), 21 (Flash
Memory), 22 (Flash Memory), 23 (Flash Memory), and
24 (Flash Memory).
DS80000531H-page 18
2011-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2011-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0470-5
DS80000531H-page 19
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS80000531H-page 20
2011-2016 Microchip Technology Inc.