LINER LTC1623IS8

LTC1623
SMBus Dual High Side
Switch Controller
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DESCRIPTION
FEATURES
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SMBus and I2C Compatible
Built-In Charge Pumps Drive N-Channel Switches
16 Available Switches on the Same Bus
0.6V VIL and 1.4V VIH for DATA and CLK
Available in 8-Lead MSOP and S0 Packages
Low Standby Current: 14µA
Eight Addresses from Two Three-State Address Pins
Internal Power-On Reset Timer
Internal Undervoltage Lockout
No Need for External Pull-Up Resistors at Output
No Need for Secondary Power Source
The LTC ®1623 SMBus switch controller is a slave device
that controls two high-side N-channel MOSFETs on either
the SMBus or the I2C bus. The LTC1623 operates with an
input voltage from 2.7V to 5.5V with a low standby current
of 14µA (at 3.3V). In accordance with the SMBus specification, the LTC1623 maintains the 0.6V VIL and 1.4V VIH
input thresholds throughout the supply voltage range.
Using the 2-wire interface, CLK and DATA, the LTC1623
monitors the bus for a start condition (DATA going from
high to low while CLK is high). Once detected, the LTC1623
compares its address with the first (address) byte sent
over the bus from the master. If matched, the LTC1623 will
execute the second (command) byte from the master and
independently control the built-in charge pumps to drive
two external switches.
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APPLICATIONS
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Computer Peripheral Control
Laptop Computer Power Plane Switching
Portable Equipment Power Control
Industrial Control Systems
Handheld Equipment
The LTC1623 has two three-state programmable address
pins, thus allowing eight different addresses and a total of
sixteen available switches on the same bus.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
VCC
2.7V TO 5.5V
Gate Drive Voltage
14
TJ = 25°C
10µF
CLK
GA
DATA
GB
Q1
GATE VOLTAGE (V)
(FROM
SMBus)
Q2
LTC1623
(PROGRAMMABLE)
AD0
AD1
GND
* SILICONIX Si69260Q
12
*
VCC
LOAD1
LOAD2
1623 TA01
10
8
6
4
2
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
1623 G01
1
LTC1623
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ABSOLUTE MAXIMUM RATINGS
(Voltages Referred to GND Pin)
Input Supply Voltage (VCC) ..........................– 0.3V to 6V
DATA, CLK (Bus Pins 1, 2) ..........................– 0.3V to 6V
AD0, AD1 (Address Pins 3, 5) ..... – 0.3V to (VCC + 0.3V)
GA,GB (Gate Drive Pins 6, 7) .......... – 0.3V to (VCC + 7V)
Junction Temperature ........................................... 125°C
Operating Temperature Range
LTC1623C.................................................. 0° to 70°C
LTC1623I ............................................ –40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
DATA
CLK
AD0
GND
1
2
3
4
8
7
6
5
VCC
GA
GB
AD1
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/ W
LTC1623CMS8
MS8 PART MARKING
ORDER PART
NUMBER
TOP VIEW
DATA 1
8
VCC
CLK 2
7
GA
AD0 3
6
GB
GND 4
5
AD1
LTC1623CS8
LTC1623IS8
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
LTCH
1623
1623I
TJMAX = 125°C, θJA = 110°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
TA = 25°C, VCC = 5V unless otherwise specified. CGA = 1000pF, CGB = 1000pF
CONDITIONS
MIN
VCC
Operating Supply Voltage Range
IVCC
Supply Current
Charge Pump Off, AD0 and AD1High or Low, VCC = 2.7V
DATA and CLK High
VCC = 3.3V
VCC = 5V
●
●
●
IVCC
Supply Current
GA or GB High (Command Byte 00000001 or 00000010)
Both GA and GB High (Command Byte 00000011)
●
●
VGS
Gate Voltage Above Supply
VCC = 2.7V
VCC = 3.3V
VCC = 5.5V
●
●
●
2.7
4.5
4.5
VUVLO
Undervoltage Lockout
Falling Edge (Note1)
●
1.5
tPOR
Power-On Reset Delay Time
VCC = 2.7V (Note2)
VCC = 5.5V
fOSC
Charge Pump Oscillator Frequency
(Note 3)
tON
Turn-On Time into 1000pF
tOFF
TYP
MAX
UNITS
5.5
V
12
14
17
30
30
30
µA
µA
µA
140
162
250
250
µA
µA
4.2
5.4
6.4
7
7
7
V
V
V
2.7
2.0
2.5
V
300
300
1000
1000
µs
µs
300
kHz
VCC = 2.7V (From ON to GA, GB = VCC + 1V) (Note 4)
VCC = 5.5V (From ON to GA, GB = VCC + 2V) (Note 4)
170
180
µs
µs
Turn-Off Time into 1000pF
VCC = 2.7V (From OFF to GA, GB = 100mV) (Note 5)
VCC = 5.5V (From OFF to GA, GB = 100mV) (Note 5)
17
12
µs
µs
VIL
DATA/CLK Input Low Voltage
VCC = 2.7V to 5.5V
VIH
DATA/CLK Input High Voltage
VCC = 2.7V to 5.5V
2
0.6
1.4
V
V
LTC1623
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC = 5V unless otherwise specified. CGA = 1000pF, CGB = 1000pF
SYMBOL PARAMETER
CONDITIONS
MIN
VIL
AD0 and AD1 Input Low Voltage
VCC = 2.7V to 5.5V
●
VIH
AD0 and AD1 Input High Voltage
VCC = 2.7V to 5.5V
●
VOL
Data Output Low Voltage
VCC = 2.7 to 5.5V, IPULLUP = 350µA
●
CIN
Input Capacitance
(DATA, CLK, AD0, AD1)
IIN
Input Leakage Current (DATA, CLK)
TYP
MAX
0.2
VCC – 0.2
V
V
0.22
0.4
5
Input Leakage Current(AD0, AD1)
UNITS
V
pF
±1
µA
±250
nA
100
kHz
SMBus Related Specs (Note 6)
fSMB
SMBus Operating Frequency
10
tSUSTA
Start Condition Setup Time
4.7
µs
tBUF
Bus Free Time Between Stop and Start
4.7
µs
tHDSTA
Start Condition Hold Time
4.0
µs
tSUSTP
Stop Condition Setup Time
4.0
µs
tHDDAT
Data Hold Time
300
ns
tSUDAT
Data Setup Time
250
ns
tLOW
Clock Low Period
4.7
tHIGH
Clock High Period
4.0
tf
Clock /Data Fall Time
tr
Clock/Data Rise Time
IPULLUP
Current Through External Pull-Up
Resistor on DATA Pin
(Data Pull-Down Current Capacity)
VCC = 2.7V to 5.5V
The ● denotes the specifications which apply over the full operating
temperature range.
Note 1: Approximately 3% hysteresis is provided to ensure stable
operation and eliminate false triggering by minor VCC glitches.
Note 2: Measured from VCC > VUVLO to SMBus ready for data input.
Note 3: The oscillator frequency is not tested directly but is inferred from
turn-on time.
100
µs
50
µs
300
ns
1000
ns
350
µA
Note 4: ON is enabled upon receiving the Stop condition from the SMBus
master.
Note 5: OFF is enabled upon receiving the Stop condition from the SMBus
master.
Note 6: SMBus timing specs are guaranteed but not tested.
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PIN FUNCTIONS
DATA: (Pin 1) Open-Drain Connected Serial Data Interface. Must be pulled high to VCC with external resistor. The
pull-up current must be limited to 350µA.
AD1: (Pin 5) Higher Three-State Programmable Address
Pin. Must be connected directly to VCC, GND, or VCC /2
(using two resistors ≤ 1M). Do not float this pin.
CLK: (Pin 2) Serial Clock Interface. Must be pulled high to
VCC with external resistor. The pull-up current must be
limited to 350µA.
GB: (Pin 6) Gate Drive to External High-Side Switch. Fully
enhanced by internal charge pump. Controlled by 2nd
LSB of command byte.
AD0: (Pin 3) Lower Three-State Programmable Address
Pin. Must be connected directly to VCC, GND, or VCC /2
(using two resistors ≤ 1M). Do not float this pin.
GA: (Pin 7) Gate Drive to External High-Side Switch. Fully
enhanced by internal charge pump. Controlled by LSB of
command byte.
GND: (Pin 4) Ground.
VCC: (Pin 8) Input Supply Voltage. Range from 2.7V to
5.5V.
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LTC1623
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
400
30
350
SUPPLY CURRENT (µA)
STANDBY CURRENT (µA)
Standby Current
35
25
20
VCC = 5V
15
VCC = 2.7V
10
5
VCC = 2.7V
300
250
200
150
BOTH CHANNELS ON
100
ONE CHANNEL ON
50
0
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
0
–60 –40 –20
100
0
20
40
60
Supply Current
Supply Current
400
400
VCC = 5V
350
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
350
300
250
200
BOTH CHANNELS ON
150
ONE CHANNEL ON
100
50
VCC = 6V
300
250
BOTH CHANNELS ON
200
ONE CHANNEL ON
150
100
50
0
–60 –40 –20
0
40
20
80
60
0
–60 –40 –20
100
TEMPERATURE (°C)
0
20
40
60
tON vs Temperature
tOFF vs Temperature
450
18
400
16
350
14
300
12
tOFF (µs)
20
250
150
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
10
8
6
100
4
50
2
0
–60 –40 –20
100
1623 G05
500
200
80
TEMPERATURE (°C)
1623 G03
tON (µs)
100
1623 G04
1623 G02
0
20
40
60
80
100
TEMPERATURE (°C)
0
–60 –40 –20
0
20
40
60
80
100
TEMPERATURE (°C)
1623 G06
4
80
TEMPERATURE (°C)
1623 G07
LTC1623
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TYPICAL PERFORMANCE CHARACTERISTICS
GA, GB Output Voltage
DATA VOL vs Temperature
16
14
500
VCC = 5V
VCC = 5V
I PULLUP = 350µA
450
DATA VOL (mV)
OUTPUT VOLTAGE (V)
400
12
10
8
6
350
300
250
200
150
4
100
2
50
0
–60 –40 –20
0
20
40
60
80
0
–60 –40 –20
100
TEMPERATURE (°C)
0
20
1623 G08
VGS vs Temperature
80
100
Gate Drive Current
100
VCC = 5.5V
VCC = 6V
GATE CURRENT (µA)
5
VCC = 3.3V
Vgs (V)
60
1623 G09
7
6
40
TEMPERATURE (°C)
4
VCC = 2.7V
3
2
VCC = 5V
10
VCC = 3.3V
VCC = 2.7V
1
1
0
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
1623 G10
0.1
0
2
3
4
5
6
1
GATE VOLTAGE ABOVE SUPPLY (VGS)
7
1623 G11
5
LTC1623
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TI I G DIAGRA
tHDSTA
tHIGH
tr
tf
tSUSTP
CLK
t HDDAT
t SUSTA
tLOW
tSUDAT
DATA
STOP
START
1623 TD01
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FU CTIO AL BLOCK DIAGRA
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VCC
UNDERVOLTAGE
LOCKOUT
POWER-ON
RESET
PORB
2V
STARTAND-STOP
DETECTORS
DATA 1
CLK 2
AD0 3
AD1 5
INPUT
BUFFER
INPUT
BUFFER
ADDRESS
DECODER
SHIFT
REGISTER
ACK
GLUE
LOGIC
10k
OUTPUT
LATCHES
COUNTER
ADDRESS
COMPARATOR
1623 BD
6
REGULATING
CHARGE
PUMPS
7 GA
10k
6 GB
LTC1623
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OPERATIO
SMBus Operation
SMBus is a serial bus interface that uses only two bus
lines, DATA and CLK, to control low power peripheral
devices in portable equipment. It consists of masters, also
known as hosts, and slave devices. The master of the
SMBus is always the one to initiate communications to its
slave devices by varying the status of the DATA and CLK
lines. The SMBus specification establishes a set of protocols that devices on the bus must follow during communications.
The protocol that the LTC1623 uses is the Send Byte
Protocol. In this protocol, the master first sends out a Start
signal by switching the DATA line from high to low while
CLK is high. (Because there may be more than one master
on the same bus, an arbitration process takes place if two
masters attempt to take control of the DATA line simultaneously; the first master that outputs a one while the other
master is zero loses the arbitration and becomes a slave
itself.) Upon detecting this Start signal, all slave devices on
the bus wake up and get ready to shift in the next byte of
data.
The master then sends out the first byte. The first seven
bits of this byte consist of the address of the device that the
master wishes to communicate with. The last bit indicates
whether the command will be a read (logic one) or write
(logic zero). Because the LTC1623 is a slave device that
can only be written to by a master, it will ignore the ensuing
commands of the master if it wants to read from the
LTC1623, even if the address sent by the master matches
that of the LTC1623. After reception of the first byte, the
slave device (LTC1623) with the matching address then
acknowledges the master by pulling the data line low
before the rising edge of the ninth clock cycle.
By now, all other nonmatching slave devices will have
gone back to their original standby states to wait for the
next start signal. Meanwhile, upon receiving the acknowledge from the matching slave, the master then sends out
the command byte. In the case of the LTC1623, the two
LSBs of this second byte from the master are the signals
controlling the status of the external switches; a digital
“one” turns on the charge pump to drive up the output gate
voltage while a digital “zero” shuts down the charge pump
and discharges the output gate voltage to zero.
After receiving the command byte, the slave device
(LTC1623) needs to again acknowledge the master by
pulling the DATA line low on the following clock cycle. The
master then ends this Send Byte Protocol by sending the
Stop signal, which is a transition from low to high on the
DATA line while the CLK line is high. Valid data is shifted
into the output latch on the last acknowledge signal; the
external switch will not be enabled, however, until the Stop
signal is detected. This double-buffering feature allows
the user to daisy-chain several differently addressed SMBus
devices such that their output executions are synchronous
to the Stop signal even though valid data were loaded into
their output latches at different times. Figure 1 shows an
example of this special protocol. If somehow either the
Start or the Stop signal is detected in the middle of a byte,
the slave device (LTC1623) will regard this as an error and
reject all previous data. Other than the Stop and Start
conditions, DATA must be stable during CLK high; DATA
can change state only during CLK low.
START ADD1 A COMMAND A START ADD2 A COMMAND A START ADD3 A COMMAND A STOP
1623 F01
Figure 1. Daisy-Chaining Multiple SMBus Devices
Example of Send Byte Protocol to Slave Address 1011000 Turning GA and GB On
CLK
START
DATA
1
0
1
1
0
0
0
(PROGRAMMABLE)
ADDRESS BYTE
0
ACK
(WRITE)
0
0
0
0
0
0
1
1
ACK
STOP
(GB ON)(GA ON)
COMMAND BYTE
1623 TD02
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LTC1623
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OPERATIO
Address
Charge Pump
The LTC1623 has an address of 1011XXX; the four MSBs
are hard-wired, but the 3 LSBs are programmed by the
user with the help of two three-state address pins. Refer to
Table 1 for the pin configurations and their corresponding
addresses.
To fully enhance the external N-channel switches, an
internal charge pump is used to boost the output gate drive
to a minimum of 2.7V and a maximum of 6V above VCC,
depending on VCC itself. The reason for the maximum
output voltage limit is to avoid switch gate source breakdown due to excessive gate overdrive. A feedback network
is used to limit the charge pump output to 6V above VCC.
Because the output will only need to drive the gate of the
external switch by charging and discharging the parasitic
gate capacitances, the internal charge pump, clocked by
an approximately 300KHz oscillator, is appropriately sized
to source less than 100µA.
To conserve standby current, it is preferable to tie the
address pins to either VCC or GND. If more than four
addresses are needed, then either one of the address pins
can be tied to the third state of VCC /2 by using two equal
value resistors (≤1M) shown in Figure 2. Do not connect
both address pins to the VCC /2 state simultaneously
because this is not a valid address.
Power-On Reset and Undervoltage Lockout
The LTC1623 starts up with both gate drives low. An
internal power-on reset (POR) signal inhibits operation
until about 300µs after VCC crosses the undervoltage
lockout threshold (typically 2V). The circuit includes some
hysteresis and delay to avoid nuisance resets. Once operation begins, VCC must drop below the threshold for at least
100µs to trigger another POR sequence.
Table 1. Address Pin Truth Table
AD0
AD1
ADDRESS
GND
GND
1011000
GND
VCC /2
1011001
GND
VCC
1011010
VCC /2
GND
1011011
VCC /2
VCC /2
UNUSED
VCC /2
VCC
1011100
VCC
GND
1011101
VCC
VCC /2
1011110
VCC
VCC
1011111
DATA
CLOCK
1
2
DATA
VCC
CLK
GA
During standby, when both gate drive outputs are disabled, quiescent current is kept to a minimum (13µA
typical) because only the UVLO block is active.
Input Threshold
8
7
1M
LTC1623
3
4
Anticipating the trend toward lower supply voltages, the
SMBus is specified with a VIH of 1.4V and a VIL of 0.6V.
While some SMBus parts may violate this stringent SMBus
specification by allowing a higher VIH value for a correspondingly higher input supply voltage, the LTC1623
meets and maintains the constant SMBus input threshold
specification across the entire supply voltage range of
2.7V to 5.5V.
AD0
GB
GND
AD1
6
5
1M
LOAD1
LOAD2
1623 F02
Figure 2. LTC1623 Programmed with Address 1011001
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LTC1623
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APPLICATIONS INFORMATION
To avoid turning on the external power MOSFETs too
quickly, an internal 10k resistor has been placed in series
with each of the output gate drive pins (see Functional
Block Diagram). Therefore, it only needs an external 0.1µF
capacitor to create enough RC delay (10k • 0.1µF = 1ms)
to slow down the ramp rate of the output gate drive. In
other words, it will take a minimum of 1ms to charge up
the external MOSFET. An additional external 1k resistor
between the 0.1µF capacitor and the gate of the MOSFET
(Figure 3) is required to eliminate possible MOSFET self
oscillations.
For active-low applications in which the load needs to be
on upon power-up, an external P-channel switch can be
used (Figure 3). This load can be switched off later after the
proper protocol has been sent.
Used with the LT ®1431, the LTC1623 makes a 3.3V/3A
extremely low voltage drop regulator (Figures 4 and 5). In
this application, the other output channel can be used to
drive a separate load, or it can also be used to control the
output of the LDO so that the user has total control over the
switching in and switching out of the LDO (Figure 5). Also,
with the help of the LT1304-5, the LTC1623 can be used
to make a boost switching regulator with a low standby
current of 22µA (Figure 6).
VCC
3.5V TO 5.5V
VCC
2.7V TO 5.5V
10µF
CLK
DATA
(FROM SMBus)
10µF
VCC
1k
DATA
0.1µF
(PROGRAMMABLE)
1k
Q2
Si6433DQ
LTC1623 GB
0.1µF
AD0
(PROGRAMMABLE)
1k
GA
Si3442DV
0.1µF
LTC1623
GB
AD0
Q1
Si3442DV
GA
CLK
(FROM
SMBus)
VCC
Si3442DV
AD1
GND
1
GND
5
FAN
DISPLAY
510pF
3.3k
+
8
LT1431
AD1
VOUT
3.3V
3
470µF LOAD
6V
6
10k
680Ω
1623 F04
1623 F03
Figure 3. Dual Load Switch with Q2 On upon Power-Up
Figure 4. 3.3V/3A Extremely Low Voltage Drop
Regulator and Load Switch
VCC
2.7V TO 4.5V
VCC
3.5V TO 5.5V
10µF
10µF
(FROM SMBus)
CLK
DATA
VCC
(FROM
SMBus)
LTC1623
GB
AD0
(PROGRAMMABLE)
Si3442DV
GA
1
AD1
GND
510pF
3.3k
8
LT1431
5
VOUT
3.3V
3
+
(PROGRAMMABLE)
AD0
GB
Si3442DV
0.1µF
22µH*
470µF
6V
3
8
+
100µF
1k
0.1µF
1623 TA03
SWITCHED
VOUT
3.3V
Figure 5. SMBus Controlled Low Dropout Regulator
LT1304-5
7
*SUMIDA CD54-220
100k
2
604k
Si3442DV
1N5817
4
499k
680Ω
LOAD
Si3442DV
AD1 GND
10k
6
1k
V
CLK CC GA
DATA
LTC1623
SHDN
+
5V
200mA
2200µF
LBO
5
1623 F05
Figure 6. Switching Regulator with Low-Battery
Detect Using 22µA Standby Current
9
LTC1623
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
1
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
2 3
4
0.034 ± 0.004
(0.86 ± 0.102)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
TYP
0.006 ± 0.004
(0.15 ± 0.102)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
10
MSOP (MS8) 1197
LTC1623
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SO8 0996
11
LTC1623
U
TYPICAL APPLICATIONS
Single Slot PCMCIA 3.3V/5V Switch
5V
10µF
VCC
1k
Q1
Si3442DY
GA
CLK
DATA
TO PC CARD VCC
0V/3.3V/5V
0.1µF
Q2*
LTC1623
AD0
10k
1µF
1k
1623 TA02
Q3*
GB
AD1
GND
0.1µF
3.3V
*1/2 Si6926DQ
LTC1623 Driving Both High Side and Low Side Switches
VEXT
(30V MAX)
VCC
2.7V TO 5.5V
LOW SIDE
LOAD
10µF
VCC
1k
GA
CLK
(FROM
SMBus)
DATA
0.1µF
Si6954DQ
1k
Si6954DQ
LTC1623 GB
(PROGRAMMABLE)
0.1µF
AD0
AD1
GND
HIGH SIDE
LOAD
1623 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1153/LTC1154
Single High Side Micropower MOSFET Drivers
Circuit Breaker with Auto Reset
LTC1155/LTC1255
Dual High Side Micropower MOSFET Drivers
Latch-Off Current Limit
LTC1163
Triple 1.8V to 6V High Side MOSFET Driver
Three MOSFET Drivers in 8-Lead SO Package
LT1304
Micropower DC/DC Converter
Low-Battery Detector Active in Shutdown
TM
LTC1473
Dual PowerPath Switch Matrix
Current Limit with Timer
LTC1479
PowerPath Controller for Dual Battery Systems
Complete Smart Battery Controller
PowerPath is a trademark of Linear Technology Corporation.
12
Linear Technology Corporation
1623f LT/TP 0598 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1997