DISCRETE SEMICONDUCTORS DATA SHEET BF1109; BF1109R; BF1109WR N-channel dual-gate MOS-FETs Product specification Supersedes data of 1997 Sep 03 1997 Dec 08 NXP Semiconductors Product specification BF1109; BF1109R; BF1109WR N-channel dual-gate MOS-FETs FEATURES PINNING Short channel transistor with high forward transfer admittance to input capacitance ratio PIN DESCRIPTION 1 source Low noise gain controlled amplifier up to 1 GHz 2 drain 3 gate 2 Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 4 gate 1 handbook, 2 columns 3 4 2 1 Top view MSB035 BF1109R marking code: NBp. Fig.2 APPLICATIONS VHF and UHF applications with 9 V supply voltage, such as television tuners and professional communications equipment. handbook, 2 columns 4 3 Simplified outline (SOT143R). ok, halfpage 3 4 2 1 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1109, BF1109R and BF1109WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. 1 2 Top view BF1109 marking code: NFp. Fig.1 Top view MSB014 MSB842 BF1109WR marking code: NB. Simplified outline (SOT143B). Fig.3 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 11 V ID drain current (DC) 30 mA Ptot total power dissipation 200 mW yfs forward transfer admittance Tamb 80 C 30 mS Cig1-ss input capacitance at gate 1 2.2 2.7 pF Crss reverse transfer capacitance f = 1 MHz 25 40 fF F noise figure f = 800 MHz 1.5 2.5 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 dBV Tj operating junction temperature 150 C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. 1997 Dec 08 2 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 11 V ID drain current (DC) 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation 200 mW Tstg storage temperature 65 +150 C Tj operating junction temperature +150 C Tamb 80 C; note 1 Note 1. Device mounted on a printed-circuit board. MGM243 250 handbook, halfpage Ptot (mW) 200 150 100 50 0 0 40 80 120 160 Tamb (°C) Fig.4 Power derating curve. 1997 Dec 08 3 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth j-a thermal resistance from junction to ambient in free air Rth j-s thermal resistance from junction to soldering point VALUE note 1 UNIT 350 K/W 200 K/W Note 1. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0; ID = 10 A 11 V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = 0; IG1-S = 10 A; ID = 0 11 V V(BR)G2-SS gate 2-source breakdown voltage V(BR)DSS drain-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 A 11 V VG2-S (th) gate 2-source threshold voltage VG1-S = 9 V; VDS = 9 V; ID = 20 A 0.3 1.2 V IDSX self-biasing drain current VG2-S = 4 V; VDS = 9 V 8 16 mA IG1-SS gate 1 cut-off current VG1-S = 9 V; VG2-S = 0; ID = 0 20 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 9 V 20 nA DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 9 V; self-biasing current; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 C 24 30 mS Cig1-ss input capacitance at gate 1 f = 1 MHz 2.2 2.7 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 1.5 pF Coss output capacitance f = 1 MHz 1.3 pF Crss reverse transfer capacitance f = 1 MHz 25 40 fF F noise figure f = 800 MHz; YS = YS opt 1.5 2.5 dB Gp power gain GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; f = 200 MHz; see Fig.16 38 dB GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; f = 800 MHz; see Fig.17 20 dB input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 85 dBV input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 100 dBV Xmod cross-modulation 1997 Dec 08 4 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR MDA613 25 MDA614 40 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 20 VG1 = 1.6 V 30 3.5 V 3V VG2-S = 4 V 1.5 V 15 1.4 V 20 2.5 V 1.3 V 10 2V 1.2 V 10 1.1 V 5 1V 1.5 V 1V 0 0 2 0 4 6 8 0 10 VDS (V) VG2-S = 4 V. Tj = 25 C. 0.5 1 1.5 2 2.5 VG1 (V) VDS = 9 V. Tj = 25 C. Fig.5 Output characteristics; typical values. Fig.6 Transfer characteristics; typical values. MDA615 MDA616 16 40 handbook, halfpage handbook, halfpage yfs ID (mA) VG2-S = 4 V (mS) 3.5 V 30 12 (1) (2) (3) 3V 8 20 (4) 4 10 2.5 V 2V 0 0 0 10 20 ID (mA) 0 30 (1) VDS = 9 V. (2) VDS = 7 V. VDS = 9 V. Tj = 25 C. Fig.7 Forward transfer admittance as a function of drain current; typical values. 1997 Dec 08 Fig.8 5 1 2 3 4 5 VG2-S (V) (3) VDS = 5 V. (4) VDS = 3 V. Drain current as a function of gate 2 voltage; typical values. NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR MDA618 MDA617 16 16 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 12 12 8 8 4 4 0 0 0 2 4 6 8 10 VDS (V) VG2-S = 4 V. Tj = 25 C. Fig.9 −4 −2 IG1 (μA) 0 Fig.10 Drain current as a function of gate 1 current; typical values. MDA619 120 handbook, halfpage Vunw (dBμV) 110 100 90 80 20 40 60 gain reduction (dB) VDS = 9 V; VG2nom = 4 V; IDnom = 12 mA; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C. Fig.11 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values (see Fig.18). 1997 Dec 08 −6 VDS = 9 V; VG2-S = 4 V; Tj = 25 C. Drain current as a function of drain-source voltage; typical values. 0 −8 6 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR MDA620 102 handbook, halfpage MDA621 103 handbook, halfpage yis (mS) −103 ϕrs (deg) |yrs| (mS) 10 |yrs| 102 −102 bis 1 ϕrs 10−1 10−2 10 gis 1 10 103 102 −10 10 f (MHz) −1 103 102 f (MHz) VDS = 9 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 9 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C. Fig.12 Input admittance as a function of frequency; typical values. Fig.13 Reverse transfer admittance and phase as a function of frequency; typical values. MDA622 102 handbook, halfpage |yfs| (mS) MDA623 −102 10 handbook, halfpage yos (mS) ϕfs (deg) |yfs| bos 1 −10 ϕfs 10 10−1 gos 1 10 102 f (MHz) 10−2 10 −1 103 VDS = 9 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C. f (MHz) 103 VDS = 9 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C. Fig.14 Forward transfer admittance and phase as a function of frequency; typical values. 1997 Dec 08 102 Fig.15 Output admittance as a function of frequency; typical values. 7 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR VAGC handbook, full pagewidth VDS 1 nF 2 μH 1 nF 1 nF 1 nF 47 kΩ 1 nF L2 G2 D BF1109 BF1109R BF1109WR 5.5 pF input 50 Ω G1 C1 L1 output 50 Ω S 15 pF 10 pF BB405 330 kΩ 1 nF BB405 1 nF 330 kΩ 1 nF Vtun input Vtun output MDA624 VDS = 9 V, GS = 2 mS, GL = 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL = 0.5 mS. C1 adjusted for GS = 2 mS. Fig.16 Gain test circuit. VAGC handbook, full pagewidth VDS 1 nF 1 nF 47 kΩ ;;; 1 nF input 50 Ω 1 nF L1 2 to 18 pF G2 G1 ;;;; ;;;; L3 L2 D BF1109 BF1109R BF1109WR 0.5 to 3.5 pF S 0.5 to 3.5 pF VDS = 9 V, GS = 3.3 mS, GL = 1 mS, f = 800 MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH. Fig.17 Gain test circuit. 1997 Dec 08 8 1 nF output 50 Ω 4 to 40 pF MDA625 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR VG2 handbook, full pagewidth VDS 4.7 nF 10 kΩ 4.7 nF 10 nF Rgen 50 Ω 47 μH G2 D BF1109 BF1109R G1 BF1109WR S 10 nF R1 = 50 Ω 50 Ω MDA626 Vi Fig.18 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 12 mA S11 MAGNITUDE (ratio) S21 ANGLE (deg) S12 S22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.995 3.71 3.013 175.0 0.000 88.2 0.998 1.8 100 0.992 7.29 3.002 170.2 0.001 83.7 0.997 3.5 200 0.984 2.967 160.7 0.002 86.2 0.995 7.0 14.3 300 0.973 21.2 2.922 151.3 0.002 83.2 0.992 10.5 400 0.961 27.9 2.869 142.0 0.003 84.1 0.990 13.9 500 0.944 34.4 2.793 132.9 0.003 85.7 0.987 17.2 600 0.926 40.8 2.730 124.1 0.003 88.4 0.985 20.5 700 0.906 46.9 2.660 1115.3 0.003 94.6 0.983 23.7 800 0.887 52.9 2.605 106.5 0.004 107.2 0.981 26.8 900 0.868 58.8 2.527 97.8 0.004 114.9 0.977 30.0 1000 0.852 64.3 2.457 89.6 0.004 129.7 0.9377 33.1 Table 2 Noise data: VDS = 9 V; VG2-S = 4 V; ID = 12 mA opt f (MHz) Fmin (dB) (ratio) (deg) Rn () 800 1.5 0.684 40.94 40.4 1997 Dec 08 9 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR PACKAGE OUTLINES Plastic surface-mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 04-11-16 06-03-16 SOT143B 1997 Dec 08 EUROPEAN PROJECTION 10 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 1.1 0.9 OUTLINE VERSION SOT143R 1997 Dec 08 A1 max bp b1 c D E 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 e 1.9 e1 HE Lp Q v w y 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 REFERENCES IEC JEDEC JEITA SC-61AA 11 EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 1997 Dec 08 EUROPEAN PROJECTION 12 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 1997 Dec 08 13 NXP Semiconductors Product specification N-channel dual-gate MOS-FETs BF1109; BF1109R; BF1109WR Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1997 Dec 08 14 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/02/pp15 Date of release: 1997 Dec 08