DISCRETE SEMICONDUCTORS DATA SHEET BF1201; BF1201R; BF1201WR N-channel dual-gate PoLo MOS-FETs Product specification Supersedes data of 1999 Dec 01 2000 Mar 29 NXP Semiconductors Product specification BF1201; BF1201R; BF1201WR N-channel dual-gate PoLo MOS-FETs FEATURES PINNING Short channel transistor with high forward transfer admittance to input capacitance ratio PIN DESCRIPTION 1 source Low noise gain controlled amplifier 2 drain Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 3 gate 2 4 gate 1 handbook, 2 columns 3 4 2 1 Top view MSB035 BF1201R marking code: LBp APPLICATIONS Fig.2 VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment. handbook, 2 columns 4 3 Simplified outline (SOT143R). 3 lfpage 4 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1201, BF1201R and BF1201WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. 1 2 Top view 2 1 Top view MSB014 MSB842 BF1201 marking code: LAp. BF1201WR marking code: LA Fig.1 Fig.3 Simplified outline (SOT143B). Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 10 V ID drain current 30 mA Ptot total power dissipation 200 mW yfs forward transfer admittance 23 28 35 mS Cig1-ss input capacitance at gate 1 2.6 3.1 pF Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 400 MHz 1 1.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 105 dBV Tj operating junction temperature 150 C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. 2000 Mar 29 2 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 10 V ID drain current (DC) 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation BF1201; BF1201R Ts 113 C; note 1 200 mW BF1201WR Ts 109 C; note 1 200 mW Tstg storage temperature 65 +150 C Tj operating junction temperature 150 C Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER VALUE UNIT BF1201; BF1201R 185 K/W BF1201WR 155 K/W thermal resistance from junction to soldering point MCD934 250 Ptot (mW) handbook, halfpage 200 (2) (1) 150 100 50 0 0 50 100 200 150 Ts (°C) (1) BF1201WR. (2) BF1201 and BF1201R. Fig.4 Power derating curve. 2000 Mar 29 3 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0; ID = 10 A 10 V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 6 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 V V(BR)DSS drain-source breakdown voltage V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 A 0.3 1.0 V VG2-S(th) gate 2-source threshold voltage VG1-S = VDS = 5 V; ID = 100 A 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 62 k; note 1 11 19 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 4 V 20 nA Note 1. RG1 connects G1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 C 23 28 35 mS Cig1-ss input capacitance at gate 1 f = 1 MHz 2.6 3.1 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 1.1 pF Coss output capacitance f = 1 MHz 0.9 pF 15 30 fF f = 10.7 MHz; GS = 20 mS; BS = 0 5 7 dB f = 400 MHz; YS = YS opt 1 1.8 dB f = 800 MHz; YS = YS opt 1.9 2.5 dB f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; 33.5 dB f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt; 29 dB f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; 24 dB at 0 dB AGC 90 dBV at 10 dB AGC 95 dBV at 40 dB AGC 105 dBV Crss reverse transfer capacitance f = 1 MHz F noise figure Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 Note 1. Measured in Fig.21 test circuit. 2000 Mar 29 4 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR MCD935 25 handbook, halfpage VG2-S = 4 V ID (mA) MCD936 24 3.5 V 3V handbook, halfpage VG1-S = 1.8 V ID (mA) 20 2.5 V 1.7 V 16 1.6 V 15 1.5 V 2V 1.4 V 10 8 1.3 V 1.5 V 1.2 V 5 1V 0 0.5 0 1 1.5 0 2 2.5 VG1-S (V) 0 VDS = 5 V. Tj = 25 C. 2 4 6 8 10 VDS (V) VG2-S = 4 V. Tj = 25 C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. MCD937 100 handbook, halfpage VG2-S = 4 V IG1 (μA) MCD938 40 handbook, halfpage 3.5 V yfs (mS) 80 VG2-S = 4 V 30 3V 3.5 V 60 2.5 V 20 2V 10 3V 40 2.5 V 20 2V 1.5 V 0 0 0.5 0 1 1.5 2 2.5 VG1-S (V) 0 VDS = 5 V. 5 Tj = 25 C. VDS = 5 V. Tj = 25 C. Fig.7 Fig.8 Gate 1 current as a function of gate 1 voltage; typical values. 2000 Mar 29 5 10 15 20 25 ID (mA) Forward transfer admittance as a function of drain current; typical values. NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs MCD939 16 BF1201; BF1201R; BF1201WR MCD940 20 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 16 12 12 8 8 4 4 0 0 0 10 20 30 0 40 50 IG1 (μA) 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 C. VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. Fig.9 Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. Drain current as a function of gate 1 current; typical values. MCD941 25 handbook, halfpage ID (mA) 47 kΩ 56 kΩ 20 MCD942 20 68 kΩ RG1 = 39 kΩ handbook, halfpage ID (mA) 82 kΩ VGG = 5 V 16 62 kΩ 100 kΩ 4.5 V 15 4V 12 3.5 V 10 8 5 4 0 0 2 4 6 3V 0 8 10 VGG = VDS (V) 0 2 4 VG2-S (V) VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21. VDS = 5 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.12 Drain current as a function of gate 2 voltage; typical values. 2000 Mar 29 6 6 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR MCD943 60 IG1 (μA) MCD944 0 VGG = 5 V handbook, halfpage handbook, gain halfpage reduction (dB) −10 4.5 V 4V 40 −20 3.5 V 3V −30 20 −40 −50 0 0 2 4 VG2-S (V) 6 0 1 2 3 VAGC (V) 4 VDS = 5 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; Tamb = 25 C. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. MCD945 120 handbook, halfpage MCD946 20 handbook, halfpage Vunw (dBμV) ID (mA) 110 16 12 100 8 90 4 80 0 10 20 30 40 50 gain reduction (dB) 0 0 VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; funw = 60 MHz; Tamb = 25 C. 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; Tamb = 25 C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. 2000 Mar 29 10 Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. 7 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR MCD947 102 handbook, halfpage MCD948 103 handbook, halfpage Yis (mS) ϕrs (deg) yrs (μS) 10 −103 ϕrs 102 −102 bis yrs gis 1 −10 10 10−1 10 102 103 1 10 f (MHz) −1 103 102 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. MCD949 102 handbook, halfpage yfs (mS) −102 ϕfs (deg) yfs MCD950 10 handbook, halfpage Yos (mS) bos 1 ϕfs 10 −10 10−1 gos 1 10 102 f (MHz) −1 103 10−2 10 102 103 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2000 Mar 29 8 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF RGEN 50 Ω R2 50 Ω RL 50 Ω L1 C2 ≈ 2.2 μH DUT C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.987 4.72 2.775 174.6 0.0006 88.8 0.997 1.84 100 0.985 9.39 2.774 169.5 0.0010 86.7 0.997 3.37 200 0.978 18.59 2.731 159.1 0.0019 79.7 0.996 6.72 300 0.976 27.74 2.671 148.8 0.0026 74.2 0.994 10.02 400 0.949 36.59 2.599 138.8 0.0032 69.9 0.992 13.33 500 0.928 45.08 2.501 129.1 0.0035 65.9 0.989 16.55 600 0.905 53.26 2.400 119.8 0.0035 64.6 0.986 19.64 700 0.882 61.07 2.297 110.9 0.0033 65.7 0.982 22.63 800 0.860 68.48 2.199 102.4 0.0029 69.1 0.979 25.54 900 0.838 75.55 2.096 94.2 0.0024 83.3 0.975 28.44 1000 0.818 82.23 1.997 86.3 0.0021 103.8 0.971 31.42 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C f (MHz) Fmin (dB) opt (ratio) (deg) Rn () 400 1 0.825 38.93 50 800 1.9 0.753 70.65 38.75 2000 Mar 29 9 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR PACKAGE OUTLINES Plastic surface-mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 04-11-16 06-03-16 SOT143B 2000 Mar 29 EUROPEAN PROJECTION 10 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 1.1 0.9 OUTLINE VERSION SOT143R 2000 Mar 29 A1 max bp b1 c D E 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 e 1.9 e1 HE Lp Q v w y 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 REFERENCES IEC JEDEC JEITA SC-61AA 11 EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 2000 Mar 29 EUROPEAN PROJECTION 12 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. DEFINITIONS Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 2000 Mar 29 BF1201; BF1201R; BF1201WR 14 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/02/pp15 Date of release: 2000 Mar 29