DISCRETE SEMICONDUCTORS DATA SHEET BF1202; BF1202R; BF1202WR N-channel dual-gate PoLo MOS-FETs Product specification Supersedes data of 2000 Mar 29 2010 Sep 16 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs FEATURES BF1202; BF1202R; BF1202WR PINNING Short channel transistor with high forward transfer admittance to input capacitance ratio PIN DESCRIPTION 1 source Low noise gain controlled amplifier 2 drain Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 3 gate 2 4 gate 1 handbook, 2 columns 3 4 2 1 Top view MSB035 Marking code legend: BF1202R marking code: LE* * = - : made in Hong Kong APPLICATIONS * = p : made in Hong Kong VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment. Fig.2 Simplified outline (SOT143R). * = t : made in Malaysia handbook, 2 columns 4 3 lfpage 3 4 2 1 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1202, BF1202R and BF1202WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. 1 2 Top view Top view MSB014 MSB842 BF1202 marking code: LD* BF1202WR marking code: LE* Fig.1 Fig.3 Simplified outline (SOT143B). Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 10 V ID drain current 30 mA Ptot total power dissipation 200 mW yfs forward transfer admittance 25 30 40 mS Cig1-ss input capacitance at gate 1 1.7 2.2 pF Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 800 MHz 1.1 1.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 105 dBV Tj operating junction temperature 150 C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. 2010 Sep 16 2 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 10 V ID drain current 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation BF1202; BF1202R Ts 113 C; note 1 200 mW BF1202WR Ts 119 C; note 1 200 mW Tstg storage temperature 65 +150 C Tj operating junction temperature 150 C Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER VALUE UNIT BF1202; BF1202R 185 K/W BF1202WR 155 K/W thermal resistance from junction to soldering point MCD951 250 Ptot handbook, halfpage (mW) 200 (2) (1) 150 100 50 0 0 50 100 200 150 Ts (°C) (1) BF1202WR. (2) BF1202; BF1202R. Fig.4 Power derating curve. 2010 Sep 16 3 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0; ID = 10 A 10 V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 6 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 V V(BR)DSS drain-source breakdown voltage V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 A 0.3 1.0 V VG2-S(th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 100 A 0.3 1.2 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 8 16 mA IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 4 V 20 nA Note 1. RG1 connects G1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 C 25 30 40 mS Cig1-ss input capacitance at gate 1 f = 1 MHz 1.7 2.2 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 1 pF Coss output capacitance f = 1 MHz 0.85 pF 15 30 fF f = 10.7 MHz; GS = 20 mS; BS = 0 9 11 dB f = 400 MHz; YS = YS opt 0.9 1.5 dB f = 800 MHz; YS = YS opt 1.1 1.8 dB f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt 34.5 dB f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt 30.5 dB f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt 26.5 dB 90 dBV Crss reverse transfer capacitance f = 1 MHz F noise figure Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC at 10 dB AGC 92 dBV at 40 dB AGC 100 105 dBV Note 1. Measured in Fig.21 test circuit. 2010 Sep 16 4 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR MCD952 20 handbook, halfpage VG2-S = 4 V ID (mA) 2.5 V 2V 3V VG1-S = 1.5 V ID (mA) 3.5 V 16 MCD953 24 handbook, halfpage 1.4 V 16 12 1.3 V 1.2 V 1.5 V 8 1.1 V 8 1V 4 0.9 V 1V 0 0.4 0 0.8 1.2 0 1.6 2 VG1-S (V) 0 VDS = 5 V. Tj = 25 C. 2 4 6 8 10 VDS (V) VG2-S = 4 V. Tj = 25 C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. MCD954 100 handbook, halfpage VG2-S = 4 V IG1 (μA) MCD955 40 handbook, halfpage 3.5 V 3.5 V yfs 3V VG2-S = 4 V (mS) 80 30 3V 60 2.5 V 20 2.5 V 40 2V 10 20 2V 1.5 V 1V 0 0 0.5 0 1 1.5 2 2.5 VG1-S (V) 0 4 VDS = 5 V. Tj = 25 C. VDS = 5 V. Tj = 25 C. Fig.7 Fig.8 Gate 1 current as a function of gate 1 voltage; typical values. 2010 Sep 16 5 8 12 16 20 ID (mA) Forward transfer admittance as a function of drain current; typical values. NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR MCD956 20 MCD957 16 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 16 12 12 8 8 4 4 0 10 0 20 30 0 40 50 IG1 (μA) 0 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. VDS = 5 V; VG2-S = 4 V. Tj = 25 C. Fig.9 1 Drain current as a function of gate 1 current; typical values. Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. MCD958 20 handbook, halfpage ID (mA) RG1 = 68 kΩ 16 82 kΩ 12 MCD959 16 handbook, halfpage ID (mA) VGG = 5 V 4.5 V 12 100 kΩ 4V 120 kΩ 3.5 V 150 kΩ 3V 8 180 kΩ 8 220 kΩ 4 4 0 0 0 2 4 0 6 VGG = VDS (V) 2 4 VG2-S (V) VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21. VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.12 Drain current as a function of gate 2 voltage; typical values. 2010 Sep 16 6 6 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR MCD960 40 MCD961 0 handbook, halfpage handbook, gain halfpage IG1 (μA) reduction (dB) −10 VGG = 5 V 30 4.5 V −20 4V 20 3.5 V 3V −30 10 −40 0 0 2 4 VG2-S (V) −50 6 0 1 2 3 VAGC (V) 4 VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 120 k; f = 50 MHz; Tamb = 25 C. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. MCD962 120 handbook, halfpage MCD963 16 handbook, halfpage Vunw (dBμV) ID (mA) 110 12 100 8 90 4 80 0 10 20 0 30 40 50 gain reduction (dB) 0 VDS = 5 V; VGG = 5 V; RG1 = 120 k; f= 50 MHz; funw = 60 MHz; Tamb = 25 C. 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 120 k; f = 50 MHz; Tamb = 25 C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; Fig.21. 2010 Sep 16 10 Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. 7 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR MCD964 102 handbook, halfpage MCD965 103 handbook, halfpage Yis (mS) ϕrs (deg) yrs (μS) 10 −103 ϕrs 102 −102 bis yrs gis 1 10−1 10 −10 10 102 103 1 10 f (GHz) −1 103 102 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. MCD966 102 handbook, halfpage yfs (mS) −102 ϕfs (deg) yfs MCD967 10 handbook, halfpage Yos (mS) bos 1 −10 10 ϕfs 1 10 102 10−1 f (MHz) −1 103 10−2 10 gos 102 103 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2010 Sep 16 8 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF RGEN 50 Ω R2 50 Ω RL 50 Ω L1 C2 ≈ 2.2 μH DUT C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.988 3.26 2.989 176.2 0.0005 92.6 0.995 1.50 100 0.988 6.52 3.017 172.5 0.0009 88.0 0.995 3.01 200 0.984 12.99 2.990 165.0 0.0018 82.5 0.994 5.95 300 0.977 19.39 2.949 157.6 0.0027 78.2 0.992 8.86 400 0.965 25.65 2.913 150.3 0.0036 75.4 0.990 11.79 500 0.951 31.76 2.853 143.2 0.0039 71.8 0.988 14.65 600 0.936 37.68 2.793 136.3 0.0042 69.9 0.986 17.41 700 0.919 43.42 2.727 129.5 0.0044 68.9 0.984 20.10 800 0.903 48.94 2.664 123.0 0.0043 68.5 0.980 22.69 900 0.887 54.25 2.593 116.7 0.0041 70.7 0.975 25.27 1000 0.870 59.34 2.518 110.5 0.0038 72.4 0.970 27.90 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C opt f (MHz) Fmin (dB) (ratio) (deg) Rn () 400 0.9 0.805 28.5 50 800 1.1 0.725 47.2 40 2010 Sep 16 9 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR PACKAGE OUTLINES Plastic surface-mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 04-11-16 06-03-16 SOT143B 2010 Sep 16 EUROPEAN PROJECTION 10 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 1.1 0.9 OUTLINE VERSION SOT143R 2010 Sep 16 A1 max bp b1 c D E 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 e 1.9 e1 HE Lp Q v w y 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 REFERENCES IEC JEDEC JEITA SC-61AA 11 EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR Plastic surface-mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 06-03-16 SOT343R 2010 Sep 16 EUROPEAN PROJECTION 12 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2010 Sep 16 13 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 2010 Sep 16 BF1202; BF1202R; BF1202WR 14 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for the marking codes and the package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/03/pp15 Date of release: 2010 Sep 16