DESIGN FEATURES Zero-Drift Operational Amplifier Family in Small-Footprint Packages Features 3µV Maximum DC Offset and 30nV/°C Maximum Drift by David Hutchinson Introduction Extended Input Common Mode Range with Uncompromising CMRR At room temperature, and with the input common mode level at midsupplies, the parts typically have 0.5µV of input-referred offset and are guaranteed to have less than ±3µV. To ensure this DC accuracy over the common mode input range, the LTC2050/LTC2051/LTC2052 have 6 exceptionally high CMRR over a wide range from the negative supply to typically within 0.9V of the positive rail, as shown in Figure 1. For example, as the input is varied over the entire 5V common mode range, the input-referred offset changes typically by less than 0.4µV. Similar levels of PSRR (typically less than 0.1µV of offset per volt of supply change) and the near zero temperature drift ensure that the offset does not exceed 5µV over the entire supply voltage and commercial temperature range. 5 VS = 5V OUTPUT SWING (V) The LTC2050, LTC2051 and LTC2052 are single, dual and quad zero-drift operational amplifiers, available in SOT-23, MS8, and GN16 packages, respectively. The smallest zero-drift op amps available, they occupy minimal board space while providing the lowest input offset (3µV max) and offset drift (30nV/°C max) currently available. In addition, they operate over a wide supply range, from 2.7V to ±5V. They have rail-to-rail outputs that can drive loads as small as 1k to either supply rail and they have an input range from the negative supply to typically less than 1V from the positive supply. 4 3 VS = 3V 2 1 0 0 2 4 6 8 LOAD RESISTANCE (kΩ) 10 Figure 2. Output voltage swing vs load resistance Clock Feedthrough and Input Bias Current The LTC2050/LTC2051/LTC2052 Virtually Eliminated Rail-to-Rail Output Drive with a 1k Load maintain their DC characteristics while driving resistive loads sourcing or sinking currents as high as 5mA. Figure 2 shows the op amps’ rail-torail swing versus output resistance loading. With a 1k or 5k load, the output typically swings to within 100mV or 30mV, respectively, of the rails. The LTC2050 family uses autozeroing circuitry to achieve its zero-drift offset and other DC specifications. The clock used for autozeroing is typically 7.5kHz. There are two types of clock feedthrough in autozeroed op amps like the LTC2050/51/52. The first is caused by the settling of the internal sampling capacitor. The input-referred magnitude of this clock 1mVRMS LTC2050 BW = 95Hz COMMON MODE REJECTION RATIO (dB) 140 100µVRMS/DIV 120 VS = 10V 100 VS = 3V 0mVRMS 80 100Hz VS = 5V 1kHz/DIV 60 10.1kHz R2 40 20 0 0 2 4 6 8 COMMON MODE VOLTAGE (V) 10 R1 – RS + Figure 1. DC CMRR vs input common mode Figure 3. Output spectrum with a gain of 101; R2 = 100k, R1 = Rs= 1k Linear Technology Magazine • November 2000 15 DESIGN FEATURES 60 INPUT BIAS CURRENT (pA) 50 A RS = 1K 5mV/DIV 40 VS = ±5V 30 20 VS = 5V 10 0 VS = 3V –10 B RS = 100k –5 –3 –1 1 3 INPUT COMMON MODE VOLTAGE (V) 5 Figure 5. Input bias current vs input common mode voltage (LTC2050HV) 50µs/DIV High Resistance Bridge Amplifier Application Figure 4. Output with a gain of 101; VS = 5V, R2 = 100kΩ, R1 = 1kΩ, input common mode at V–; trace A: RS = 1kΩ, trace B: RS = 100kΩ V+ 0.1µF 3 VIN+ 10k 5 + 1 LTC2050HV 4 – 2 0.1µF V– 5V 5V A very common application of zero drift amplifiers is amplifying signals from a differential resistive bridge, as shown in Figure 6. The gain is 2R2/R, where R is the bridge resistance. In applications where the bridge resistance is high, input bias current of the op amp can cause errors. With 5V supplies, the LTC2050HV typically has 5pA of input bias current at midsupply (see Figure 5). Therefore, bridge resistances as high as 100k contribute less than 1µV of additional offset due to input bias current and bridge resistance. mon mode level at the negative supply (ground). Trace A shows the output when the source resistance (RS) is 1k, whereas trace B shows the output for RS = 100k. The charge injection of the input switches appears in the high input-resistance case. However, the average value of the charge injection current (which is the input bias current) is less than 15pA, as shown in Figure 5. Therefore, even with 100k source resistance, the spikes in Figure 4, trace B can be reduced to 1.5µV input-referred DC with a feedback capacitor across R2. feedthrough is independent of input source resistance or gain setting resistors. Figure 3 shows the output spectrum of the LTC2050 with a closed-loop gain of 101 with R2 = 100k, and R1 = RS = 1k. There is a residual clock feedthrough of less than 1µVRMS, input referred, at 7.5kHz. This very low clock feedthrough is achieved in the LTC2050/LTC2051/ LTC2052 by internal circuitry that improves settling of the internal autozero storage capacitors. The second form of clock feedthrough is caused by the charge injection of the internal MOS switches connected to the op amp inputs. These current spikes are not evident in the output when the source resistance of the op amp inputs are small (that is, R1 and RS are small in Figure 3). Figure 4 shows the output of the LTC2050HV operating with a gain of 101, 5V supply and the input com- 0.01µF 100k 340k C 0.1µF V GAIN TRIM + 2.49k R2 STRAIN GAUGE 0.001µF 0.1µF 4 R×4 – LTC2050 3 3.01k 5 1 3 OUT + C + 1 8 LT1677 2 R2 7 VIN– 2 6 VOUT – 4 V– Figure 6. Typical differential bridge amplifier 16 0.1µF Figure 7. Zero drift, low noise composite operational amplifier Linear Technology Magazine • November 2000 DESIGN FEATURES Ultralow VOS Drift, Low Noise Composite Amplifier Negative Supply-Current Monitor The LTC2050 family of amplifiers has about 1.5µV peak-to-peak noise between DC and 10Hz. If an application needs less noise but requires the LTC2050’s DC performance, a composite amplifier such as the one shown in Figure 7 may be the solution. The LT1677 is a low noise rail-torail input and output op amp that operates over a very wide supply range (3V to ±15V). The integrator formed by the LTC2050HV nulls the offset of the composite amplifier via the offset trim pins of the LT1677. The resulting offset and drift are those of the LTC2050HV but the noise is close to that of the LT1677 (about 100nV peakto-peak, DC to 10Hz). With the values shown, the warm-up time is about ten seconds. Figure 8 shows the LTC2051 being used to sense the current in the negative power supply. The low offset of the LTC2051 allows the use of a very small sense resistor, RS. The output is level shifted to ground using M1. Conclusion The LTC2050/LTC2051/LTC2052 family of zero-drift operational amplifiers offer smaller packages than any other operational amplifiers with their DC specifications. In addition, they are the first to run on single 2.7V supplies, yet are capable of operation with higher ±5 supplies. V+ 5 M1 BSS138 100Ω 2 3 + 8 1/2 LTC2051 6 – – 7 VOUT 1V/100mA LOAD CURRENT IN MEASURED CIRCUIT 100k 1/2 LTC2051 1 + 4 0.1µF V– RS 0.01Ω V– LOAD ILOAD Figure 8. Negative supply current monitor can cause grief to upstream circuitry unless means are taken to attenuate it. The LT1809 performs admirably in this task. Tracing the reverse signal path from the LTC1420, C1 serves as a storage capacitor and R3 limits the glitch current into the LT1809’s output. The LT1809’s collector output stage incorporates proprietary local feedback to reduce its output impedance (about 20Ω at 100MHz) and this helps attenuate the glitch as well. However, a remnant glitch persists and works its way through R2 and R1, being attenuated by a factor of 2 in the process, and arrives at the LT1809 inverting input. For best performance, the amplitude of the glitch at this point should have been reduced to several millivolts. If it is larger than about 25mV, the rule-of-thumb for BJT differential pairs, the input stage will begin to be driven outside of its linear region and excess distortion will result. The excellent results of Figure 10 indicate that the circuit is not suffering from this effect. Conclusion The LT1806 and LT1809 provide complementary solutions for high speed, low voltage signal conditioning. The LT1806, with its low voltage R3 49.9Ω LT1809 +IN – R1 1k LTC1420 –IN –5V fSAMPLE = 10Msps VIN = 2VP-P fIN = 1.394MHz VS = ±5V 5V 5V + 0 –20 FORWARD SIGNAL VIN = 1VP-P noise of 3.5nV/√Hz and a maximum offset voltage of 550µV, is ideal for applications requiring low noise or DC precision, whereas the LT1809 provides the ultimate in distortion performance. The rail-to-rail inputs and outputs of the devices maximize dynamic range and can simplify designs by eliminating the need for a negative supply. This combination of features in a SOT-23 package makes the devices a top choice for handling the challenges of low voltage signal conditioning. C1 470pF 12 BITS 10Msps AMPLITUDE (dB) LT1806/LT1809, continued from page 10 –40 –60 –80 –100 –5V R2 1k –120 0 SAMPLING GLITCH Figure 9. High speed ADC driver Linear Technology Magazine • November 2000 1 2 3 FREQUENCY (MHz) 4 5 Figure 10. 4096 point FFT of the 12-bit ADC’s output 17